From: Karol Herbst Date: Thu, 19 May 2022 12:43:56 +0000 (+0200) Subject: nouveau/headers: initial sync of headers X-Git-Tag: upstream/23.3.3~4620 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=179f996c04591d67f4032ccf9ffb1dcf92cb8c41;p=platform%2Fupstream%2Fmesa.git nouveau/headers: initial sync of headers Part-of: --- diff --git a/src/nouveau/nvidia-headers/classes/cl0039.h b/src/nouveau/nvidia-headers/classes/cl0039.h new file mode 100644 index 0000000..ba7e8fd --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl0039.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0039_h_ +#define _cl0039_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV03_MEMORY_TO_MEMORY_FORMAT (0x00000039) +/* NvNotification[] elements */ +#define NV039_NOTIFIERS_NOTIFY (0) +#define NV039_NOTIFIERS_BUFFER_NOTIFY (1) +#define NV039_NOTIFIERS_MAXCOUNT (2) +/* NvNotification[] fields and values */ +#define NV039_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV039_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV039_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV039_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000) +#define NV039_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800) +#define NV039_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) +/* pio method data structure */ +typedef volatile struct _cl0039_tag0 { + NvV32 NoOperation; /* ignored 0100-0103*/ + NvV32 Notify; /* NV039_NOTIFY_* 0104-0107*/ + NvV32 Reserved00[0x01e]; + NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/ + NvV32 SetContextDmaBufferIn; /* NV01_CONTEXT_DMA 0184-0187*/ + NvV32 SetContextDmaBufferOut; /* NV01_CONTEXT_DMA 0188-018b*/ + NvV32 Reserved01[0x060]; +#ifdef NV_LDDM + NvU32 LDDMBuffer; /* Buffer Number 0300-0303*/ + NvU32 LDDMSetResource; /* Set Resource 0304-0307*/ + NvU32 LDDMSetResourceState; /* Set Resource State 0308-030B*/ +#endif + NvU32 OffsetIn; /* src offset in bytes 030c-030f*/ + NvU32 OffsetOut; /* dst offset in bytes 0310-0313*/ + NvS32 PitchIn; /* delta in bytes, vert pixel delta 0314-0317*/ + NvS32 PitchOut; /* delta in bytes, vert pixel delta 0318-031b*/ + NvU32 LineLengthIn; /* in bytes 031c-031f*/ + NvU32 LineCount; /* in lines 0320-0323*/ + NvV32 Format; /* out_in U24_U8 0324-0327*/ + NvV32 BufferNotify; /* NV039_BUFFER_NOTIFY_* 0328-032b*/ + NvV32 Reserved02[0x735]; +} Nv039Typedef, Nv03MemoryToMemoryFormat; +#define NV039_TYPEDEF Nv03MemoryToMemoryFormat +/* dma method offsets, fields, and values */ +#define NV039_SET_OBJECT (0x00000000) +#define NV039_NO_OPERATION (0x00000100) +#define NV039_NOTIFY (0x00000104) +#define NV039_NOTIFY_WRITE_ONLY (0x00000000) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_1 (0x00000001) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_2 (0x00000002) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_3 (0x00000003) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_4 (0x00000004) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_5 (0x00000005) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_6 (0x00000006) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_7 (0x00000007) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_8 (0x00000008) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_9 (0x00000009) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_A (0x0000000A) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_B (0x0000000B) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_C (0x0000000C) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_D (0x0000000D) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_E (0x0000000E) +#define NV039_NOTIFY_WRITE_THEN_AWAKEN_F (0x0000000F) +#define NV039_SET_CONTEXT_DMA_NOTIFIES (0x00000180) +#define NV039_SET_CONTEXT_DMA_BUFFER_IN (0x00000184) +#define NV039_SET_CONTEXT_DMA_BUFFER_OUT (0x00000188) + +#ifdef NV_LDDM +// For 32 Bit Handles +#define NV039_LDDM_BIND_RESOURCE (0x00000200) +#define NV039_LDDM_UNBIND_RESOURCE (0x00000204) +#define NV039_LDDM_ENABLE_RESOURCE (0x00000208) +#define NV039_LDDM_UPDATE_OFFSET (0x0000020C) +#define NV039_LDDM_UPDATE_OFFSET_LOCATION 1:0 +#define NV039_LDDM_UPDATE_OFFSET_LOCATION_VIDMEM 0x00000000 +#define NV039_LDDM_UPDATE_OFFSET_LOCATION_PCI 0x00000001 +#define NV039_LDDM_UPDATE_OFFSET_OFFSET 31:2 + +#define NV039_LDDM_DISABLE_RESOURCE (0x00000210) +#define NV039_LDDM_ENABLE_RESOURCE_IMMEDIATE (0x00000214) + + +#endif + +#define NV039_SET_HRESOURCE (0x00000218) +#define NV039_SET_HDMA (0x0000021C) +#define NV039_SET_HDMA_CONTEXT (0x00000220) +#define NV039_SET_START_PAGE (0x00000224) +//#define NV039_SET_COUNT (0x00000228) +#define NV039_SET_HIGH_PTE_DATA (0x0000022C) +#define NV039_SET_LOW_PTE_DATA (0x00000230) + +#define NV039_OFFSET_IN (0x0000030C) +#define NV039_OFFSET_OUT (0x00000310) +#define NV039_PITCH_IN (0x00000314) +#define NV039_PITCH_OUT (0x00000318) +#define NV039_LINE_LENGTH_IN (0x0000031C) +#define NV039_LINE_COUNT (0x00000320) +#define NV039_FORMAT (0x00000324) +#define NV039_FORMAT_IN 7:0 +#define NV039_FORMAT_OUT 31:8 +#define NV039_BUFFER_NOTIFY (0x00000328) +#define NV039_BUFFER_NOTIFY_WRITE_ONLY (0x00000000) +#define NV039_BUFFER_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) +/* obsolete stuff */ +#define NV3_MEMORY_TO_MEMORY_FORMAT (0x00000039) +#define Nv3MemoryToMemoryFormat Nv03MemoryToMemoryFormat +#define nv3MemoryToMemoryFormat Nv03MemoryToMemoryFormat +#define nv03MemoryToMemoryFormat Nv03MemoryToMemoryFormat + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0039_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl0042.h b/src/nouveau/nvidia-headers/classes/cl0042.h new file mode 100644 index 0000000..6b568dd --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl0042.h @@ -0,0 +1,97 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl0042_h_ +#define _cl0042_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_CONTEXT_SURFACES_2D (0x00000042) +/* NvNotification[] elements */ +#define NV042_NOTIFIERS_NOTIFY (0) +#define NV042_NOTIFIERS_MAXCOUNT (1) +/* NvNotification[] fields and values */ +#define NV042_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV042_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV042_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV042_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000) +#define NV042_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800) +#define NV042_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) +/* pio method data structure */ +typedef volatile struct _cl0042_tag0 { + NvV32 NoOperation; /* ignored 0100-0103*/ + NvV32 Notify; /* NV042_NOTIFY_* 0104-0107*/ + NvV32 Reserved00[0x01e]; + NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/ + NvV32 SetContextDmaImageSource;/* NV01_CONTEXT_DMA 0184-0187*/ + NvV32 SetContextDmaImageDestin;/* NV01_CONTEXT_DMA 0188-018b*/ + NvV32 Reserved01[0x05d]; + NvV32 SetColorFormat; /* NV042_SET_COLOR_FORMAT_* 0300-0303*/ + NvU32 SetPitch; /* destin_source U16_U16 0304-0307*/ + NvU32 SetOffsetSource; /* byte offset of top-left pixel 0308-030b*/ + NvU32 SetOffsetDestin; /* byte offset of top-left pixel 030c-030f*/ + NvV32 Reserved02[0x73c]; +} Nv042Typedef, Nv04ContextSurfaces2d; +#define NV042_TYPEDEF Nv04ContextSurfaces2d +/* dma method offsets, fields, and values */ +#define NV042_SET_OBJECT (0x00000000) +#define NV042_NO_OPERATION (0x00000100) +#define NV042_NOTIFY (0x00000104) +#define NV042_NOTIFY_WRITE_ONLY (0x00000000) +#define NV042_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) +#define NV042_SET_CONTEXT_DMA_NOTIFIES (0x00000180) +#define NV042_SET_CONTEXT_DMA_IMAGE_SOURCE (0x00000184) +#define NV042_SET_CONTEXT_DMA_IMAGE_DESTIN (0x00000188) +#define NV042_SET_COLOR_FORMAT (0x00000300) +#define NV042_SET_COLOR_FORMAT_LE_Y8 (0x00000001) +#define NV042_SET_COLOR_FORMAT_LE_X1R5G5B5_Z1R5G5B5 (0x00000002) +#define NV042_SET_COLOR_FORMAT_LE_X1R5G5B5_O1R5G5B5 (0x00000003) +#define NV042_SET_COLOR_FORMAT_LE_R5G6B5 (0x00000004) +#define NV042_SET_COLOR_FORMAT_LE_Y16 (0x00000005) +#define NV042_SET_COLOR_FORMAT_LE_X8R8G8B8_Z8R8G8B8 (0x00000006) +#define NV042_SET_COLOR_FORMAT_LE_X8R8G8B8_O8R8G8B8 (0x00000007) +#define NV042_SET_COLOR_FORMAT_LE_X1A7R8G8B8_Z1A7R8G8B8 (0x00000008) +#define NV042_SET_COLOR_FORMAT_LE_X1A7R8G8B8_O1A7R8G8B8 (0x00000009) +#define NV042_SET_COLOR_FORMAT_LE_A8R8G8B8 (0x0000000A) +#define NV042_SET_COLOR_FORMAT_LE_Y32 (0x0000000B) +#define NV042_SET_PITCH (0x00000304) +#define NV042_SET_PITCH_SOURCE 15:0 +#define NV042_SET_PITCH_DESTIN 31:16 +#define NV042_SET_OFFSET_SOURCE (0x00000308) +#define NV042_SET_OFFSET_DESTIN (0x0000030C) +/* obsolete stuff */ +#define NV4_CONTEXT_SURFACES_2D (0x00000042) +#define Nv4ContextSurfaces2d Nv04ContextSurfaces2d +#define nv4ContextSurfaces2d Nv04ContextSurfaces2d +#define nv4ContextSurfaces2D Nv04ContextSurfaces2d +#define nv04ContextSurfaces2d Nv04ContextSurfaces2d + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0042_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl004a.h b/src/nouveau/nvidia-headers/classes/cl004a.h new file mode 100644 index 0000000..16a5211 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl004a.h @@ -0,0 +1,282 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl004a_h_ +#define _cl004a_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_GDI_RECTANGLE_TEXT (0x0000004A) +/* NvNotification[] elements */ +#define NV04A_NOTIFIERS_NOTIFY (0) +#define NV04A_NOTIFIERS_MAXCOUNT (1) +/* NvNotification[] fields and values */ +#define NV04A_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV04A_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV04A_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV04A_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000) +#define NV04A_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800) +#define NV04A_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) +/* memory data structures */ +typedef struct { /* start of data structure 0000- */ + NvV32 size; /* height_width U16_U16 in pixels 0- 3*/ + NvV32 monochrome[1]; /* 32 monochrome pixels per write 4- 7*/ +} Nv04aCharacter8[]; /* end of data structure -0007*/ +typedef struct { /* start of data structure 0000- */ + NvV32 size; /* height_width U16_U16 in pixels 0- 3*/ + NvV32 monochrome[3]; /* 32 monochrome pixels per write 4- f*/ +} Nv04aCharacter16[]; /* end of data structure -000f*/ +typedef struct { /* start of data structure 0000- */ + NvV32 size; /* height_width U16_U16 in pixels 00- 03*/ + NvV32 monochrome[7]; /* 32 monochrome pixels per write 04- 1f*/ +} Nv04aCharacter32[]; /* end of data structure -001f*/ +typedef struct { /* start of data structure 0000- */ + NvV32 size; /* height_width U16_U16 in pixels 00- 03*/ + NvV32 monochrome[15]; /* 32 monochrome pixels per write 04- 3f*/ +} Nv04aCharacter64[]; /* end of data structure -003f*/ +typedef struct { /* start of data structure 0000- */ + NvV32 size; /* height_width U16_U16 in pixels 00- 03*/ + NvV32 monochrome[31]; /* 32 monochrome pixels per write 04- 7f*/ +} Nv04aCharacter128[]; /* end of data structure -007f*/ +typedef struct { /* start of data structure 0000- */ + NvV32 size; /* height_width U16_U16 in pixels 00- 03*/ + NvV32 monochrome[63]; /* 32 monochrome pixels per write 04- ff*/ +} Nv04aCharacter256[]; /* end of data structure -00ff*/ +typedef struct { /* start of data structure 0000- */ + NvV32 size; /* height_width U16_U16 in pixels 000- 003*/ + NvV32 monochrome[127]; /* 32 monochrome pixels per write 004- 1ff*/ +} Nv04aCharacter512[]; /* end of data structure -01ff*/ +/* pio method data structure */ +typedef volatile struct _cl004a_tag0 { + NvV32 NoOperation; /* ignored 0100-0103*/ + NvV32 Notify; /* NV04A_NOTIFY_* 0104-0107*/ + NvV32 Reserved00[0x01e]; + NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/ + NvV32 SetContextDmaFonts; /* NV01_CONTEXT_DMA 0184-0187*/ + NvV32 SetContextPattern; /* NV04_CONTEXT_PATTERN 0188-018b*/ + NvV32 SetContextRop; /* NV03_CONTEXT_ROP 018c-018f*/ + NvV32 SetContextBeta1; /* NV01_CONTEXT_BETA 0190-0193*/ + NvV32 SetContextBeta4; /* NV04_CONTEXT_BETA 0194-0197*/ + NvV32 SetContextSurface; /* NV04_CONTEXT_SURFACES_2D 0198-019b*/ + NvV32 Reserved01[0x058]; + NvV32 SetOperation; /* NV04A_SET_OPERATION_* 02fc-02ff*/ + NvV32 SetColorFormat; /* NV04A_SET_COLOR_FORMAT_* 0300-0303*/ + NvV32 SetMonochromeFormat; /* NV04A_SET_MONOCHROME_FORMAT_* 0304-0307*/ + NvV32 Reserved02[0x03D]; + NvV32 Color1A; /* rectangle color 03fc-03ff*/ + struct { /* start aliased methods in array 0400- */ + NvV32 point; /* x_y S16_S16 in pixels 0- 3*/ + NvV32 size; /* width_height U16_U16 in pixels 4- 7*/ + } UnclippedRectangle[32]; /* end of aliased methods in array -04ff*/ + NvV32 Reserved03[0x03D]; + NvV32 ClipPoint0B; /* top_left S16_S16 in pixels 05f4-05f7*/ + NvV32 ClipPoint1B; /* bottom_right S16_S16 in pixels 05f8-05fb*/ + NvV32 Color1B; /* rectangle color 05fc-05ff*/ + struct { /* start aliased methods in array 0600- */ + NvV32 point0; /* top_left S16_S16 in pixels 0- 3*/ + NvV32 point1; /* bottom_right S16_S16 in pixels 4- 7*/ + } ClippedRectangle[32]; /* end of aliased methods in array -06ff*/ + NvV32 Reserved04[0x03B]; + NvV32 ClipPoint0C; /* top_left S16_S16 in pixels 07ec-07ef*/ + NvV32 ClipPoint1C; /* bottom_right S16_S16 in pixe 07f0-07f3*/ + NvV32 Color1C; /* color of 1 pixels 07f4-07f7*/ + NvV32 SizeC; /* height_width U16_U16 in pixels 07f8-07fb*/ + NvV32 PointC; /* y_x S16_S16 in pixels 07fc-07ff*/ + NvV32 MonochromeColor1C[128]; /* 32 monochrome pixels per write 0800-09ff*/ + NvV32 Reserved05[0x079]; + NvV32 ClipPoint0E; /* top_left S16_S16 in pixels 0be4-0be7*/ + NvV32 ClipPoint1E; /* bottom_right S16_S16 in pixels 0be8-0beb*/ + NvV32 Color0E; /* color of 0 pixels 0bec-0bef*/ + NvV32 Color1E; /* color of 1 pixels 0bf0-0bf3*/ + NvV32 SizeInE; /* height_width U16_U16 in pixels 0bf4-0bf7*/ + NvV32 SizeOutE; /* height_width U16_U16 in pixels 0bf8-0bfb*/ + NvV32 PointE; /* y_x S16_S16 in pixels 0bfc-0bff*/ + NvV32 MonochromeColor01E[128]; /* 32 monochrome pixels per write 0c00-0dff*/ + NvV32 Reserved06[0x07C]; + NvV32 FontF; /* pitch_offset V4_U28 0ff0-0ff3*/ + NvV32 ClipPoint0F; /* top_left S16_S16 in pixels 0ff4-0ff7*/ + NvV32 ClipPoint1F; /* bottom_right S16_S16 in pixels 0ff8-0ffb*/ + NvV32 Color1F; /* color of 1 pixels 0ffc-0fff*/ + NvV32 CharacterColor1F[256]; /* y_x_index S12_S12_U8 1000-13ff*/ + NvV32 Reserved07[0x0FC]; + NvV32 FontG; /* pitch_offset V4_U28 17f0-17f3*/ + NvV32 ClipPoint0G; /* top_left S16_S16 in pixels 17f4-17f7*/ + NvV32 ClipPoint1G; /* bottom_right S16_S16 in pixels 17f8-17fb*/ + NvV32 Color1G; /* color of 1 pixels 17fc-17ff*/ + struct { /* start aliased methods in array 1800- */ + NvV32 point; /* y_x S16_S16 in pixels 0- 3*/ + NvU32 index; /* 0<=index<=65525 4- 7*/ + } CharacterColor1G[256]; /* end of aliased methods in array -1fff*/ +} Nv04aTypedef, Nv04GdiRectangleText; +#define NV04A_TYPEDEF Nv04GdiRectangleText +/* dma method offsets, fields, and values */ +#define NV04A_SET_OBJECT (0x00000000) +#define NV04A_NO_OPERATION (0x00000100) +#define NV04A_NOTIFY (0x00000104) +#define NV04A_NOTIFY_WRITE_ONLY (0x00000000) +#define NV04A_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) +#define NV04A_SET_CONTEXT_DMA_NOTIFIES (0x00000180) +#define NV04A_SET_CONTEXT_DMA_FONTS (0x00000184) +#define NV04A_SET_CONTEXT_PATTERN (0x00000188) +#define NV04A_SET_CONTEXT_ROP (0x0000018C) +#define NV04A_SET_CONTEXT_BETA1 (0x00000190) +#define NV04A_SET_CONTEXT_BETA4 (0x00000194) +#define NV04A_SET_CONTEXT_SURFACE (0x00000198) +#define NV04A_SET_OPERATION (0x000002FC) +#define NV04A_SET_OPERATION_SRCCOPY_AND (0x00000000) +#define NV04A_SET_OPERATION_ROP_AND (0x00000001) +#define NV04A_SET_OPERATION_BLEND_AND (0x00000002) +#define NV04A_SET_OPERATION_SRCCOPY (0x00000003) +#define NV04A_SET_OPERATION_SRCCOPY_PREMULT (0x00000004) +#define NV04A_SET_OPERATION_BLEND_PREMULT (0x00000005) +#define NV04A_SET_COLOR_FORMAT (0x00000300) +#define NV04A_SET_COLOR_FORMAT_LE_X16R5G6B5 (0x00000001) +#define NV04A_SET_COLOR_FORMAT_LE_X17R5G5B5 (0x00000002) +#define NV04A_SET_COLOR_FORMAT_LE_X8R8G8B8 (0x00000003) +#define NV04A_SET_MONOCHROME_FORMAT (0x00000304) +#define NV04A_SET_MONOCHROME_FORMAT_CGA6_M1 (0x00000001) +#define NV04A_SET_MONOCHROME_FORMAT_LE_M1 (0x00000002) +#define NV04A_COLOR1_A (0x000003FC) +#define NV04A_UNCLIPPED_RECTANGLE(a) (0x00000400\ + +(a)*0x0008) +#define NV04A_UNCLIPPED_RECTANGLE_POINT(a) (0x00000400\ + +(a)*0x0008) +#define NV04A_UNCLIPPED_RECTANGLE_POINT_Y 15:0 +#define NV04A_UNCLIPPED_RECTANGLE_POINT_X 31:16 +#define NV04A_UNCLIPPED_RECTANGLE_SIZE(a) (0x00000404\ + +(a)*0x0008) +#define NV04A_UNCLIPPED_RECTANGLE_SIZE_HEIGHT 15:0 +#define NV04A_UNCLIPPED_RECTANGLE_SIZE_WIDTH 31:16 +#define NV04A_CLIP_POINT0_B (0x000005F4) +#define NV04A_CLIP_POINT0_B_LEFT 15:0 +#define NV04A_CLIP_POINT0_B_TOP 31:16 +#define NV04A_CLIP_POINT1_B (0x000005F8) +#define NV04A_CLIP_POINT1_B_RIGHT 15:0 +#define NV04A_CLIP_POINT1_B_BOTTOM 31:16 +#define NV04A_COLOR1_B (0x000005FC) +#define NV04A_CLIPPED_RECTANGLE(a) (0x00000600\ + +(a)*0x0008) +#define NV04A_CLIPPED_RECTANGLE_POINT_0(a) (0x00000600\ + +(a)*0x0008) +#define NV04A_CLIPPED_RECTANGLE_POINT_0_LEFT 15:0 +#define NV04A_CLIPPED_RECTANGLE_POINT_0_TOP 31:16 +#define NV04A_CLIPPED_RECTANGLE_POINT_1(a) (0x00000604\ + +(a)*0x0008) +#define NV04A_CLIPPED_RECTANGLE_POINT_1_RIGHT 15:0 +#define NV04A_CLIPPED_RECTANGLE_POINT_1_BOTTOM 31:16 +#define NV04A_CLIP_POINT0_C (0x000007EC) +#define NV04A_CLIP_POINT0_C_LEFT 15:0 +#define NV04A_CLIP_POINT0_C_TOP 31:16 +#define NV04A_CLIP_POINT1_C (0x000007F0) +#define NV04A_CLIP_POINT1_C_RIGHT 15:0 +#define NV04A_CLIP_POINT1_C_BOTTOM 31:16 +#define NV04A_COLOR1_C (0x000007F4) +#define NV04A_SIZE_C (0x000007F8) +#define NV04A_SIZE_C_WIDTH 15:0 +#define NV04A_SIZE_C_HEIGHT 31:16 +#define NV04A_POINT_C (0x000007FC) +#define NV04A_POINT_C_X 15:0 +#define NV04A_POINT_C_Y 31:16 +#define NV04A_MONOCHROME_COLOR1_C(a) (0x00000800\ + +(a)*0x0004) +#define NV04A_CLIP_POINT0_E (0x00000BE4) +#define NV04A_CLIP_POINT0_E_LEFT 15:0 +#define NV04A_CLIP_POINT0_E_TOP 31:16 +#define NV04A_CLIP_POINT1_E (0x00000BE8) +#define NV04A_CLIP_POINT1_E_RIGHT 15:0 +#define NV04A_CLIP_POINT1_E_BOTTOM 31:16 +#define NV04A_COLOR0_E (0x00000BEC) +#define NV04A_COLOR1_E (0x00000BF0) +#define NV04A_SIZE_IN_E (0x00000BF4) +#define NV04A_SIZE_IN_E_WIDTH 15:0 +#define NV04A_SIZE_IN_E_HEIGHT 31:16 +#define NV04A_SIZE_OUT_E (0x00000BF8) +#define NV04A_SIZE_OUT_E_WIDTH 15:0 +#define NV04A_SIZE_OUT_E_HEIGHT 31:16 +#define NV04A_POINT_E (0x00000BFC) +#define NV04A_POINT_E_X 15:0 +#define NV04A_POINT_E_Y 31:16 +#define NV04A_MONOCHROME_COLOR01_E(a) (0x00000C00\ + +(a)*0x0004) +#define NV04A_FONT_F (0x00000FF0) +#define NV04A_FONT_F_OFFSET 27:0 +#define NV04A_FONT_F_PITCH 31:28 +#define NV04A_FONT_F_PITCH_8 (0x00000003) +#define NV04A_FONT_F_PITCH_16 (0x00000004) +#define NV04A_FONT_F_PITCH_32 (0x00000005) +#define NV04A_FONT_F_PITCH_64 (0x00000006) +#define NV04A_FONT_F_PITCH_128 (0x00000007) +#define NV04A_FONT_F_PITCH_256 (0x00000008) +#define NV04A_FONT_F_PITCH_512 (0x00000009) +#define NV04A_CLIP_POINT0_F (0x00000FF4) +#define NV04A_CLIP_POINT0_F_LEFT 15:0 +#define NV04A_CLIP_POINT0_F_TOP 31:16 +#define NV04A_CLIP_POINT1_F (0x00000FF8) +#define NV04A_CLIP_POINT1_F_RIGHT 15:0 +#define NV04A_CLIP_POINT1_F_BOTTOM 31:16 +#define NV04A_COLOR1_F (0x00000FFC) +#define NV04A_CHARACTER_COLOR1_F(a) (0x00001000\ + +(a)*0x0004) +#define NV04A_CHARACTER_COLOR1_F_INDEX 7:0 +#define NV04A_CHARACTER_COLOR1_F_X 19:8 +#define NV04A_CHARACTER_COLOR1_F_Y 31:20 +#define NV04A_FONT_G (0x000017F0) +#define NV04A_FONT_G_OFFSET 27:0 +#define NV04A_FONT_G_PITCH 31:28 +#define NV04A_FONT_G_PITCH_8 (0x00000003) +#define NV04A_FONT_G_PITCH_16 (0x00000004) +#define NV04A_FONT_G_PITCH_32 (0x00000005) +#define NV04A_FONT_G_PITCH_64 (0x00000006) +#define NV04A_FONT_G_PITCH_128 (0x00000007) +#define NV04A_FONT_G_PITCH_256 (0x00000008) +#define NV04A_FONT_G_PITCH_512 (0x00000009) +#define NV04A_CLIP_POINT0_G (0x000017F4) +#define NV04A_CLIP_POINT0_G_LEFT 15:0 +#define NV04A_CLIP_POINT0_G_TOP 31:16 +#define NV04A_CLIP_POINT1_G (0x000017F8) +#define NV04A_CLIP_POINT1_G_RIGHT 15:0 +#define NV04A_CLIP_POINT1_G_BOTTOM 31:16 +#define NV04A_COLOR1_G (0x000017FC) +#define NV04A_CHARACTER_COLOR1_G(a) (0x00001800\ + +(a)*0x0008) +#define NV04A_CHARACTER_COLOR1_G_POINT(a) (0x00001800\ + +(a)*0x0008) +#define NV04A_CHARACTER_COLOR1_G_POINT_X 15:0 +#define NV04A_CHARACTER_COLOR1_G_POINT_Y 31:16 +#define NV04A_CHARACTER_COLOR1_G_INDEX(a) (0x00001804\ + +(a)*0x0008) +/* obsolete stuff */ +#define NV4_GDI_RECTANGLE_TEXT (0x0000004A) +#define Nv4GdiRectangleText Nv04GdiRectangleText +#define nv4GdiRectangleText Nv04GdiRectangleText +#define nv04GdiRectangleText Nv04GdiRectangleText + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl004a_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl0065.h b/src/nouveau/nvidia-headers/classes/cl0065.h new file mode 100644 index 0000000..cfb2446 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl0065.h @@ -0,0 +1,117 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl0065_h_ +#define _cl0065_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV05_IMAGE_FROM_CPU (0x00000065) +/* NvNotification[] elements */ +#define NV065_NOTIFIERS_NOTIFY (0) +#define NV065_NOTIFIERS_MAXCOUNT (1) + +/* NvNotification[] fields and values */ +#define NV065_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV065_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV065_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV065_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000) +#define NV065_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800) +#define NV065_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) +/* pio method data structure */ +typedef volatile struct _cl0065_tag0 { + NvV32 NoOperation; /* ignored 0100-0103*/ + NvV32 Notify; /* NV065_NOTIFY_* 0104-0107*/ + NvV32 Reserved00[0x01e]; + NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/ + NvV32 SetContextColorKey; /* NV04_CONTEXT_COLOR_KEY 0184-0187*/ + NvV32 SetContextClipRectangle; /* NV01_CONTEXT_CLIP_RECTANGLE 0188-018b*/ + NvV32 SetContextPattern; /* NV04_CONTEXT_PATTERN 018c-018f*/ + NvV32 SetContextRop; /* NV03_CONTEXT_ROP 0190-0193*/ + NvV32 SetContextBeta1; /* NV01_CONTEXT_BETA 0194-0197*/ + NvV32 SetContextBeta4; /* NV04_CONTEXT_BETA 0198-019b*/ + NvV32 SetContextSurface; /* NV04_CONTEXT_SURFACES_2D 019c-019f*/ + NvV32 Reserved01[0x056]; + NvV32 SetColorConversion; /* NV065_SET_COLOR_CONVERSION_* 02f8-02fb*/ + NvV32 SetOperation; /* NV065_SET_OPERATION_* 02fc-02ff*/ + NvV32 SetColorFormat; /* NV065_SET_COLOR_FORMAT_* 0300-0303*/ + NvV32 Point; /* y_x S16_S16 in pixels 0304-0307*/ + NvV32 SizeOut; /* height_width U16_U16, pixels 0308-030b*/ + NvV32 SizeIn; /* height_width U16_U16, pixels 030c-030f*/ + NvV32 Reserved02[0x03c]; + NvV32 Color[1792]; /* source colors (packed texels) 0400-1fff*/ +} Nv065Typedef, Nv05ImageFromCpu; +#define NV065_TYPEDEF Nv05ImageFromCpu +/* dma method offsets, fields, and values */ +#define NV065_SET_OBJECT (0x00000000) +#define NV065_NO_OPERATION (0x00000100) +#define NV065_NOTIFY (0x00000104) +#define NV065_NOTIFY_WRITE_ONLY (0x00000000) +#define NV065_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) +#define NV065_SET_CONTEXT_DMA_NOTIFIES (0x00000180) +#define NV065_SET_CONTEXT_COLOR_KEY (0x00000184) +#define NV065_SET_CONTEXT_CLIP_RECTANGLE (0x00000188) +#define NV065_SET_CONTEXT_PATTERN (0x0000018C) +#define NV065_SET_CONTEXT_ROP (0x00000190) +#define NV065_SET_CONTEXT_BETA1 (0x00000194) +#define NV065_SET_CONTEXT_BETA4 (0x00000198) +#define NV065_SET_CONTEXT_SURFACE (0x0000019C) +#define NV065_SET_COLOR_CONVERSION (0x000002F8) +#define NV065_SET_COLOR_CONVERSION_DITHER (0x00000000) +#define NV065_SET_COLOR_CONVERSION_TRUNCATE (0x00000001) +#define NV065_SET_COLOR_CONVERSION_SUBTRACT_TRUNCATE (0x00000002) +#define NV065_SET_OPERATION (0x000002FC) +#define NV065_SET_OPERATION_SRCCOPY_AND (0x00000000) +#define NV065_SET_OPERATION_ROP_AND (0x00000001) +#define NV065_SET_OPERATION_BLEND_AND (0x00000002) +#define NV065_SET_OPERATION_SRCCOPY (0x00000003) +#define NV065_SET_OPERATION_SRCCOPY_PREMULT (0x00000004) +#define NV065_SET_OPERATION_BLEND_PREMULT (0x00000005) +#define NV065_SET_COLOR_FORMAT (0x00000300) +#define NV065_SET_COLOR_FORMAT_LE_R5G6B5 (0x00000001) +#define NV065_SET_COLOR_FORMAT_LE_A1R5G5B5 (0x00000002) +#define NV065_SET_COLOR_FORMAT_LE_X1R5G5B5 (0x00000003) +#define NV065_SET_COLOR_FORMAT_LE_A8R8G8B8 (0x00000004) +#define NV065_SET_COLOR_FORMAT_LE_X8R8G8B8 (0x00000005) +#define NV065_POINT (0x00000304) +#define NV065_POINT_X 15:0 +#define NV065_POINT_Y 31:16 +#define NV065_SIZE_OUT (0x00000308) +#define NV065_SIZE_OUT_WIDTH 15:0 +#define NV065_SIZE_OUT_HEIGHT 31:16 +#define NV065_SIZE_IN (0x0000030C) +#define NV065_SIZE_IN_WIDTH 15:0 +#define NV065_SIZE_IN_HEIGHT 31:16 +#define NV065_COLOR(a) (0x00000400\ + +(a)*0x0004) +#define NV065_COLOR__SIZE_1 1792 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0065_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl0066.h b/src/nouveau/nvidia-headers/classes/cl0066.h new file mode 100644 index 0000000..542ac25 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl0066.h @@ -0,0 +1,130 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl0066_h_ +#define _cl0066_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV05_STRETCHED_IMAGE_FROM_CPU (0x00000066) +/* NvNotification[] elements */ +#define NV066_NOTIFIERS_NOTIFY (0) +#define NV066_NOTIFIERS_MAXCOUNT (1) +/* NvNotification[] fields and values */ +#define NV066_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV066_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV066_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV066_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000) +#define NV066_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800) +#define NV066_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) +/* pio method data structure */ +/* MSVC71 bug: cannot compile this typedef as C++ without a struct tag */ +/* fixed in MSVC8 and later */ +#define TAGHACK +#if defined(NV_WINDOWS) +#undef TAGHACK +#define TAGHACK tagHack +#endif +typedef volatile struct TAGHACK { +#undef TAGHACK + NvV32 NoOperation; /* ignored 0100-0103*/ + NvV32 Notify; /* NV066_NOTIFY_* 0104-0107*/ + NvV32 Reserved00[0x01e]; + NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/ + NvV32 SetContextColorKey; /* NV04_CONTEXT_COLOR_KEY 0184-0187*/ + NvV32 SetContextPattern; /* NV04_CONTEXT_PATTERN 0188-018b*/ + NvV32 SetContextRop; /* NV03_CONTEXT_ROP 018c-018f*/ + NvV32 SetContextBeta1; /* NV01_CONTEXT_BETA 0190-0193*/ + NvV32 SetContextBeta4; /* NV04_CONTEXT_BETA 0194-0197*/ + NvV32 SetContextSurface; /* NV04_CONTEXT_SURFACES_2D 0198-019b*/ + NvV32 Reserved01[0x057]; + NvV32 SetColorConversion; /* NV066_SET_COLOR_CONVERSION_* 02f8-02fb*/ + NvV32 SetOperation; /* NV066_SET_OPERATION_* 02fc-02ff*/ + NvV32 SetColorFormat; /* NV066_SET_COLOR_FORMAT_* 0300-0303*/ + NvV32 SizeIn; /* height_width U16_U16 in texels 0304-0307*/ + NvV32 DxDs; /* S12d20 dx/ds 0308-030b*/ + NvV32 DyDt; /* S12d20 dy/dt 030c-030f*/ + NvV32 ClipPoint; /* y_x S16_S16 0310-0313*/ + NvV32 ClipSize; /* height_width U16_U16 0314-0317*/ + NvV32 Point12d4; /* y_x S12d4_S12d4 in pixels 0318-031b*/ + NvV32 Reserved02[0x039]; + NvV32 Color[1792]; /* source colors (packed texels) 0400-1fff*/ +} Nv066Typedef, Nv05StretchedImageFromCpu; +#define NV066_TYPEDEF Nv05StretchedImageFromCpu +/* dma method offsets, fields, and values */ +#define NV066_SET_OBJECT (0x00000000) +#define NV066_NO_OPERATION (0x00000100) +#define NV066_NOTIFY (0x00000104) +#define NV066_NOTIFY_WRITE_ONLY (0x00000000) +#define NV066_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) +#define NV066_SET_CONTEXT_DMA_NOTIFIES (0x00000180) +#define NV066_SET_CONTEXT_COLOR_KEY (0x00000184) +#define NV066_SET_CONTEXT_PATTERN (0x00000188) +#define NV066_SET_CONTEXT_ROP (0x0000018C) +#define NV066_SET_CONTEXT_BETA1 (0x00000190) +#define NV066_SET_CONTEXT_BETA4 (0x00000194) +#define NV066_SET_CONTEXT_SURFACE (0x00000198) +#define NV066_SET_COLOR_CONVERSION (0x000002F8) +#define NV066_SET_COLOR_CONVERSION_DITHER (0x00000000) +#define NV066_SET_COLOR_CONVERSION_TRUNCATE (0x00000001) +#define NV066_SET_COLOR_CONVERSION_SUBTRACT_TRUNCATE (0x00000002) +#define NV066_SET_OPERATION (0x000002FC) +#define NV066_SET_OPERATION_SRCCOPY_AND (0x00000000) +#define NV066_SET_OPERATION_ROP_AND (0x00000001) +#define NV066_SET_OPERATION_BLEND_AND (0x00000002) +#define NV066_SET_OPERATION_SRCCOPY (0x00000003) +#define NV066_SET_OPERATION_SRCCOPY_PREMULT (0x00000004) +#define NV066_SET_OPERATION_BLEND_PREMULT (0x00000005) +#define NV066_SET_COLOR_FORMAT (0x00000300) +#define NV066_SET_COLOR_FORMAT_LE_R5G6B5 (0x00000001) +#define NV066_SET_COLOR_FORMAT_LE_A1R5G5B5 (0x00000002) +#define NV066_SET_COLOR_FORMAT_LE_X1R5G5B5 (0x00000003) +#define NV066_SET_COLOR_FORMAT_LE_A8R8G8B8 (0x00000004) +#define NV066_SET_COLOR_FORMAT_LE_X8R8G8B8 (0x00000005) +#define NV066_SIZE_IN (0x00000304) +#define NV066_SIZE_IN_WIDTH 15:0 +#define NV066_SIZE_IN_HEIGHT 31:16 +#define NV066_DX_DS (0x00000308) +#define NV066_DY_DT (0x0000030C) +#define NV066_CLIP_POINT (0x00000310) +#define NV066_CLIP_POINT_X 15:0 +#define NV066_CLIP_POINT_Y 31:16 +#define NV066_CLIP_SIZE (0x00000314) +#define NV066_CLIP_SIZE_WIDTH 15:0 +#define NV066_CLIP_SIZE_HEIGHT 31:16 +#define NV066_POINT_12D4 (0x00000318) +#define NV066_POINT_12D4_X 15:0 +#define NV066_POINT_12D4_Y 31:16 +#define NV066_COLOR(a) (0x00000400\ + +(a)*0x0004) +#define NV066_COLOR__SIZE_1 1792 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0066_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl0077.h b/src/nouveau/nvidia-headers/classes/cl0077.h new file mode 100644 index 0000000..c826d67 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl0077.h @@ -0,0 +1,140 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl0077_h_ +#define _cl0077_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV04_SCALED_IMAGE_FROM_MEMORY (0x00000077) +/* NvNotification[] elements */ +#define NV077_NOTIFIERS_NOTIFY (0) +#define NV077_NOTIFIERS_MAXCOUNT (1) +/* NvNotification[] fields and values */ +#define NV077_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV077_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV077_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV077_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000) +#define NV077_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800) +#define NV077_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) +/* pio method data structure */ +typedef volatile struct _cl0077_tag0 { + NvV32 NoOperation; /* ignored 0100-0103*/ + NvV32 Notify; /* NV077_NOTIFY_* 0104-0107*/ + NvV32 Reserved00[0x01e]; + NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/ + NvV32 SetContextDmaImage; /* NV01_CONTEXT_DMA 0184-0187*/ + NvV32 SetContextPattern; /* NV04_CONTEXT_PATTERN 0188-018b*/ + NvV32 SetContextRop; /* NV03_CONTEXT_ROP 018c-018f*/ + NvV32 SetContextBeta1; /* NV01_CONTEXT_BETA 0190-0193*/ + NvV32 SetContextBeta4; /* NV04_CONTEXT_BETA 0194-0197*/ + NvV32 SetContextSurface; /* NV04_CONTEXT_SURFACES_2D,SWIZZLE 0198-019b*/ + NvV32 Reserved01[0x059]; + NvV32 SetColorFormat; /* NV077_SET_COLOR_FORMAT_* 0300-0303*/ + NvV32 SetOperation; /* NV077_SET_OPERATION_* 0304-0307*/ + NvV32 ClipPoint; /* y_x S16_S16 0308-030b*/ + NvV32 ClipSize; /* height_width U16_U16 030c-030f*/ + NvV32 ImageOutPoint; /* y_x S16_S16 0310-0313*/ + NvV32 ImageOutSize; /* height_width U16_U16 0314-0317*/ + NvV32 DeltaDuDx; /* S12d20 ratio du/dx 0318-031b*/ + NvV32 DeltaDvDy; /* S12d20 ratio dv/dy 031c-031f*/ + NvV32 Reserved02[0x038]; + NvV32 ImageInSize; /* height_width U16_U16 0400-0403*/ + NvU32 ImageInFormat; /* interpolator_origin_pitch 0404-0407*/ + NvU32 ImageInOffset; /* bytes 0408-040b*/ + NvV32 ImageInPoint; /* v_u U12d4_U12d4 040c-040f*/ + NvV32 Reserved03[0x6fc]; +} Nv077Typedef, Nv04ScaledImageFromMemory; +#define NV077_TYPEDEF Nv04ScaledImageFromMemory +/* dma method offsets, fields, and values */ +#define NV077_SET_OBJECT (0x00000000) +#define NV077_NO_OPERATION (0x00000100) +#define NV077_NOTIFY (0x00000104) +#define NV077_NOTIFY_WRITE_ONLY (0x00000000) +#define NV077_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) +#define NV077_SET_CONTEXT_DMA_NOTIFIES (0x00000180) +#define NV077_SET_CONTEXT_DMA_IMAGE (0x00000184) +#define NV077_SET_CONTEXT_PATTERN (0x00000188) +#define NV077_SET_CONTEXT_ROP (0x0000018C) +#define NV077_SET_CONTEXT_BETA1 (0x00000190) +#define NV077_SET_CONTEXT_BETA4 (0x00000194) +#define NV077_SET_CONTEXT_SURFACE (0x00000198) +#define NV077_SET_COLOR_FORMAT (0x00000300) +#define NV077_SET_COLOR_FORMAT_LE_A1R5G5B5 (0x00000001) +#define NV077_SET_COLOR_FORMAT_LE_X1R5G5B5 (0x00000002) +#define NV077_SET_COLOR_FORMAT_LE_A8R8G8B8 (0x00000003) +#define NV077_SET_COLOR_FORMAT_LE_X8R8G8B8 (0x00000004) +#define NV077_SET_COLOR_FORMAT_LE_V8YB8U8YA8 (0x00000005) +#define NV077_SET_COLOR_FORMAT_LE_YB8V8YA8U8 (0x00000006) +#define NV077_SET_COLOR_FORMAT_LE_R5G6B5 (0x00000007) +#define NV077_SET_OPERATION (0x00000304) +#define NV077_SET_OPERATION_SRCCOPY_AND (0x00000000) +#define NV077_SET_OPERATION_ROP_AND (0x00000001) +#define NV077_SET_OPERATION_BLEND_AND (0x00000002) +#define NV077_SET_OPERATION_SRCCOPY (0x00000003) +#define NV077_SET_OPERATION_SRCCOPY_PREMULT (0x00000004) +#define NV077_SET_OPERATION_BLEND_PREMULT (0x00000005) +#define NV077_CLIP_POINT (0x00000308) +#define NV077_CLIP_POINT_X 15:0 +#define NV077_CLIP_POINT_Y 31:16 +#define NV077_CLIP_SIZE (0x0000030C) +#define NV077_CLIP_SIZE_WIDTH 15:0 +#define NV077_CLIP_SIZE_HEIGHT 31:16 +#define NV077_IMAGE_OUT_POINT (0x00000310) +#define NV077_IMAGE_OUT_POINT_X 15:0 +#define NV077_IMAGE_OUT_POINT_Y 31:16 +#define NV077_IMAGE_OUT_SIZE (0x00000314) +#define NV077_IMAGE_OUT_SIZE_WIDTH 15:0 +#define NV077_IMAGE_OUT_SIZE_HEIGHT 31:16 +#define NV077_DELTA_DU_DX (0x00000318) +#define NV077_DELTA_DV_DY (0x0000031C) +#define NV077_IMAGE_IN_SIZE (0x00000400) +#define NV077_IMAGE_IN_SIZE_WIDTH 15:0 +#define NV077_IMAGE_IN_SIZE_HEIGHT 31:16 +#define NV077_IMAGE_IN_FORMAT (0x00000404) +#define NV077_IMAGE_IN_FORMAT_PITCH 15:0 +#define NV077_IMAGE_IN_FORMAT_ORIGIN 23:16 +#define NV077_IMAGE_IN_FORMAT_ORIGIN_CENTER (0x00000001) +#define NV077_IMAGE_IN_FORMAT_ORIGIN_CORNER (0x00000002) +#define NV077_IMAGE_IN_FORMAT_INTERPOLATOR 31:24 +#define NV077_IMAGE_IN_FORMAT_INTERPOLATOR_ZOH (0x00000000) +#define NV077_IMAGE_IN_FORMAT_INTERPOLATOR_FOH (0x00000001) +#define NV077_IMAGE_IN_OFFSET (0x00000408) +#define NV077_IMAGE_IN (0x0000040C) +#define NV077_IMAGE_IN_POINT_U 15:0 +#define NV077_IMAGE_IN_POINT_V 31:16 +/* obsolete stuff */ +#define NV4_SCALED_IMAGE_FROM_MEMORY (0x00000077) +#define Nv4ScaledImageFromMemory Nv04ScaledImageFromMemory +#define nv4ScaledImageFromMemory Nv04ScaledImageFromMemory +#define nv04ScaledImageFromMemory Nv04ScaledImageFromMemory + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl0077_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl007b.h b/src/nouveau/nvidia-headers/classes/cl007b.h new file mode 100644 index 0000000..4ab37f5 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl007b.h @@ -0,0 +1,102 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl007b_h_ +#define _cl007b_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +#define NV10_TEXTURE_FROM_CPU (0x0000007B) +/* NvNotification[] elements */ +#define NV07B_NOTIFIERS_NOTIFY (0) +#define NV07B_NOTIFIERS_MAXCOUNT (1) +/* NvNotification[] fields and values */ +#define NV07B_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV07B_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +#define NV07B_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) +#define NV07B_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x1000) +#define NV07B_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x0800) +#define NV07B_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) +/* pio method data structure */ +typedef volatile struct _cl007b_tag0 { + NvV32 NoOperation; /* ignored 0100-0103*/ + NvV32 Notify; /* NV089_NOTIFY_* 0104-0107*/ + NvV32 Reserved00[0x01e]; + NvV32 SetContextDmaNotifies; /* NV01_CONTEXT_DMA 0180-0183*/ + NvV32 SetContextSurface; /* NV04_CONTEXT_SURFACES_2D 0184-0187*/ + NvV32 Reserved01[0x05e]; + NvV32 SetColorFormat; /* NV07B_SET_COLOR_FORMAT_* 0300-0303*/ + NvV32 Point; /* y_x S16_S16 in pixels 0304-0307*/ + NvV32 Size; /* height_width U16_U16, pixels 0308-030b*/ + NvV32 ClipHorizontal; /* width_x U16_U16 030c-030f*/ + NvV32 ClipVertical; /* height_y U16_U16 0310-0313*/ + NvV32 Reserved02[0x03b]; + struct { /* start aliased methods in array 0400- */ + NvV32 a; /* source colors (packed texels) 0- 3*/ + NvV32 b; /* source colors (packed texels) 4- 7*/ + } Color[896]; /* end of aliased methods in array -1fff*/ +} Nv07bTypedef, Nv10TextureFromCpu; +#define NV07B_TYPEDEF Nv10TextureFromCpu +/* dma method offsets, fields, and values */ +#define NV07B_SET_OBJECT (0x00000000) +#define NV07B_NO_OPERATION (0x00000100) +#define NV07B_NOTIFY (0x00000104) +#define NV07B_NOTIFY_WRITE_ONLY (0x00000000) +#define NV07B_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) +#define NV07B_SET_CONTEXT_DMA_NOTIFIES (0x00000180) +#define NV07B_SET_CONTEXT_SURFACE (0x00000184) +#define NV07B_SET_COLOR_FORMAT (0x00000300) +#define NV07B_SET_COLOR_FORMAT_LE_R5G6B5 (0x00000001) +#define NV07B_SET_COLOR_FORMAT_LE_A1R5G5B5 (0x00000002) +#define NV07B_SET_COLOR_FORMAT_LE_X1R5G5B5 (0x00000003) +#define NV07B_SET_COLOR_FORMAT_LE_A8R8G8B8 (0x00000004) +#define NV07B_SET_COLOR_FORMAT_LE_X8R8G8B8 (0x00000005) +#define NV07B_POINT (0x00000304) +#define NV07B_POINT_X 15:0 +#define NV07B_POINT_Y 31:16 +#define NV07B_SIZE (0x00000308) +#define NV07B_SIZE_WIDTH 15:0 +#define NV07B_SIZE_HEIGHT 31:16 +#define NV07B_CLIP_HORIZONTAL (0x0000030C) +#define NV07B_CLIP_HORIZONTAL_X 15:0 +#define NV07B_CLIP_HORIZONTAL_WIDTH 31:16 +#define NV07B_CLIP_VERTICAL (0x00000310) +#define NV07B_CLIP_VERTICAL_Y 15:0 +#define NV07B_CLIP_VERTICAL_HEIGHT 31:16 +#define NV07B_COLOR(a) (0x00000400\ + +(a)*0x0008) +#define NV07B_COLOR_A(a) (0x00000400\ + +(a)*0x0008) +#define NV07B_COLOR_B(a) (0x00000404\ + +(a)*0x0008) +#define NV07B_COLOR__SIZE_1 896 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl007b_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl502d.h b/src/nouveau/nvidia-headers/classes/cl502d.h new file mode 100644 index 0000000..0ac25cb --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl502d.h @@ -0,0 +1,712 @@ +/* + * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_nv50_twod_h_ +#define _cl_nv50_twod_h_ + +#define NV50_TWOD 0x502D + +typedef volatile struct _cl502d_tag0 { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 Notify; + NvU32 Reserved_0x108[0x2]; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0xB]; + NvU32 PmTrigger; + NvU32 Reserved_0x144[0xF]; + NvU32 SetContextDmaNotify; + NvU32 SetDstContextDma; + NvU32 SetSrcContextDma; + NvU32 SetSemaphoreContextDma; + NvU32 Reserved_0x190[0x1C]; + NvU32 SetDstFormat; + NvU32 SetDstMemoryLayout; + NvU32 SetDstBlockSize; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstPitch; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstOffsetUpper; + NvU32 SetDstOffsetLower; + NvU32 SetPixelsFromCpuIndexWrap; + NvU32 SetKind2dCheckEnable; + NvU32 SetSrcFormat; + NvU32 SetSrcMemoryLayout; + NvU32 SetSrcBlockSize; + NvU32 SetSrcDepth; + NvU32 SetSrcLayer; + NvU32 SetSrcPitch; + NvU32 SetSrcWidth; + NvU32 SetSrcHeight; + NvU32 SetSrcOffsetUpper; + NvU32 SetSrcOffsetLower; + NvU32 SetPixelsFromMemorySectorPromotion; + NvU32 Reserved_0x25C[0x1]; + NvU32 SetNumTpcs; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 Reserved_0x270[0x4]; + NvU32 SetClipX0; + NvU32 SetClipY0; + NvU32 SetClipWidth; + NvU32 SetClipHeight; + NvU32 SetClipEnable; + NvU32 SetColorKeyFormat; + NvU32 SetColorKey; + NvU32 SetColorKeyEnable; + NvU32 SetRop; + NvU32 SetBeta1; + NvU32 SetBeta4; + NvU32 SetOperation; + NvU32 SetPatternOffset; + NvU32 SetPatternSelect; + NvU32 Reserved_0x2B8[0xC]; + NvU32 SetMonochromePatternColorFormat; + NvU32 SetMonochromePatternFormat; + NvU32 SetMonochromePatternColor0; + NvU32 SetMonochromePatternColor1; + NvU32 SetMonochromePattern0; + NvU32 SetMonochromePattern1; + NvU32 ColorPatternX8R8G8B8[0x40]; + NvU32 ColorPatternR5G6B5[0x20]; + NvU32 ColorPatternX1R5G5B5[0x20]; + NvU32 ColorPatternY8[0x10]; + NvU32 Reserved_0x540[0x10]; + NvU32 RenderSolidPrimMode; + NvU32 SetRenderSolidPrimColorFormat; + NvU32 SetRenderSolidPrimColor; + NvU32 SetRenderSolidLineTieBreakBits; + NvU32 Reserved_0x590[0x14]; + NvU32 RenderSolidPrimPointXY; + NvU32 Reserved_0x5E4[0x7]; + struct { + NvU32 SetX; + NvU32 Y; + } RenderSolidPrimPoint[0x40]; + NvU32 SetPixelsFromCpuDataType; + NvU32 SetPixelsFromCpuColorFormat; + NvU32 SetPixelsFromCpuIndexFormat; + NvU32 SetPixelsFromCpuMonoFormat; + NvU32 SetPixelsFromCpuWrap; + NvU32 SetPixelsFromCpuColor0; + NvU32 SetPixelsFromCpuColor1; + NvU32 SetPixelsFromCpuMonoOpacity; + NvU32 Reserved_0x820[0x6]; + NvU32 SetPixelsFromCpuSrcWidth; + NvU32 SetPixelsFromCpuSrcHeight; + NvU32 SetPixelsFromCpuDxDuFrac; + NvU32 SetPixelsFromCpuDxDuInt; + NvU32 SetPixelsFromCpuDyDvFrac; + NvU32 SetPixelsFromCpuDyDvInt; + NvU32 SetPixelsFromCpuDstX0Frac; + NvU32 SetPixelsFromCpuDstX0Int; + NvU32 SetPixelsFromCpuDstY0Frac; + NvU32 SetPixelsFromCpuDstY0Int; + NvU32 PixelsFromCpuData; + NvU32 Reserved_0x864[0x3]; + NvU32 SetBigEndianControl; + NvU32 Reserved_0x874[0x3]; + NvU32 SetPixelsFromMemoryBlockShape; + NvU32 SetPixelsFromMemoryCorralSize; + NvU32 SetPixelsFromMemorySafeOverlap; + NvU32 SetPixelsFromMemorySampleMode; + NvU32 Reserved_0x890[0x8]; + NvU32 SetPixelsFromMemoryDstX0; + NvU32 SetPixelsFromMemoryDstY0; + NvU32 SetPixelsFromMemoryDstWidth; + NvU32 SetPixelsFromMemoryDstHeight; + NvU32 SetPixelsFromMemoryDuDxFrac; + NvU32 SetPixelsFromMemoryDuDxInt; + NvU32 SetPixelsFromMemoryDvDyFrac; + NvU32 SetPixelsFromMemoryDvDyInt; + NvU32 SetPixelsFromMemorySrcX0Frac; + NvU32 SetPixelsFromMemorySrcX0Int; + NvU32 SetPixelsFromMemorySrcY0Frac; + NvU32 PixelsFromMemorySrcY0Int; +} nv50_twod_t; + + +#define NV502D_SET_OBJECT 0x0000 +#define NV502D_SET_OBJECT_POINTER 15:0 + +#define NV502D_NO_OPERATION 0x0100 +#define NV502D_NO_OPERATION_V 31:0 + +#define NV502D_NOTIFY 0x0104 +#define NV502D_NOTIFY_TYPE 31:0 +#define NV502D_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV502D_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV502D_WAIT_FOR_IDLE 0x0110 +#define NV502D_WAIT_FOR_IDLE_V 31:0 + +#define NV502D_PM_TRIGGER 0x0140 +#define NV502D_PM_TRIGGER_V 31:0 + +#define NV502D_SET_CONTEXT_DMA_NOTIFY 0x0180 +#define NV502D_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 + +#define NV502D_SET_DST_CONTEXT_DMA 0x0184 +#define NV502D_SET_DST_CONTEXT_DMA_HANDLE 31:0 + +#define NV502D_SET_SRC_CONTEXT_DMA 0x0188 +#define NV502D_SET_SRC_CONTEXT_DMA_HANDLE 31:0 + +#define NV502D_SET_SEMAPHORE_CONTEXT_DMA 0x018c +#define NV502D_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0 + +#define NV502D_SET_DST_FORMAT 0x0200 +#define NV502D_SET_DST_FORMAT_V 7:0 +#define NV502D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF +#define NV502D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV502D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF +#define NV502D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV502D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV502D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV502D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV502D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV502D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV502D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV502D_SET_DST_FORMAT_V_R5G6B5 0x000000E8 +#define NV502D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV502D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV502D_SET_DST_FORMAT_V_Y8 0x000000F3 +#define NV502D_SET_DST_FORMAT_V_Y16 0x000000EE +#define NV502D_SET_DST_FORMAT_V_Y32 0x000000FF +#define NV502D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV502D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC +#define NV502D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV502D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE +#define NV502D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C +#define NV502D_SET_DST_FORMAT_V_RF16 0x000000F2 +#define NV502D_SET_DST_FORMAT_V_RF32 0x000000E5 +#define NV502D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB +#define NV502D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV502D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV502D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV502D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 + +#define NV502D_SET_DST_MEMORY_LAYOUT 0x0204 +#define NV502D_SET_DST_MEMORY_LAYOUT_V 0:0 +#define NV502D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV502D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV502D_SET_DST_BLOCK_SIZE 0x0208 +#define NV502D_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NV502D_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV502D_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NV502D_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV502D_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV502D_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV502D_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV502D_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV502D_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV502D_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NV502D_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV502D_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV502D_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV502D_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV502D_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV502D_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV502D_SET_DST_DEPTH 0x020c +#define NV502D_SET_DST_DEPTH_V 31:0 + +#define NV502D_SET_DST_LAYER 0x0210 +#define NV502D_SET_DST_LAYER_V 31:0 + +#define NV502D_SET_DST_PITCH 0x0214 +#define NV502D_SET_DST_PITCH_V 31:0 + +#define NV502D_SET_DST_WIDTH 0x0218 +#define NV502D_SET_DST_WIDTH_V 31:0 + +#define NV502D_SET_DST_HEIGHT 0x021c +#define NV502D_SET_DST_HEIGHT_V 31:0 + +#define NV502D_SET_DST_OFFSET_UPPER 0x0220 +#define NV502D_SET_DST_OFFSET_UPPER_V 7:0 + +#define NV502D_SET_DST_OFFSET_LOWER 0x0224 +#define NV502D_SET_DST_OFFSET_LOWER_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_WRAP 0x0228 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_WRAP_V 0:0 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_WRAP_V_WRAP 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_WRAP_V_NO_WRAP 0x00000001 + +#define NV502D_SET_KIND2D_CHECK_ENABLE 0x022c +#define NV502D_SET_KIND2D_CHECK_ENABLE_V 0:0 +#define NV502D_SET_KIND2D_CHECK_ENABLE_V_FALSE 0x00000000 +#define NV502D_SET_KIND2D_CHECK_ENABLE_V_TRUE 0x00000001 + +#define NV502D_SET_SRC_FORMAT 0x0230 +#define NV502D_SET_SRC_FORMAT_V 7:0 +#define NV502D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF +#define NV502D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV502D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF +#define NV502D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV502D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV502D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV502D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV502D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV502D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV502D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV502D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8 +#define NV502D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV502D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV502D_SET_SRC_FORMAT_V_Y8 0x000000F3 +#define NV502D_SET_SRC_FORMAT_V_AY8 0x0000001D +#define NV502D_SET_SRC_FORMAT_V_Y16 0x000000EE +#define NV502D_SET_SRC_FORMAT_V_Y32 0x000000FF +#define NV502D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV502D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC +#define NV502D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV502D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE +#define NV502D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C +#define NV502D_SET_SRC_FORMAT_V_RF16 0x000000F2 +#define NV502D_SET_SRC_FORMAT_V_RF32 0x000000E5 +#define NV502D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB +#define NV502D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV502D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV502D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV502D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 + +#define NV502D_SET_SRC_MEMORY_LAYOUT 0x0234 +#define NV502D_SET_SRC_MEMORY_LAYOUT_V 0:0 +#define NV502D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV502D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV502D_SET_SRC_BLOCK_SIZE 0x0238 +#define NV502D_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NV502D_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV502D_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NV502D_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV502D_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV502D_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV502D_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV502D_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV502D_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV502D_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NV502D_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV502D_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV502D_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV502D_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV502D_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV502D_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV502D_SET_SRC_DEPTH 0x023c +#define NV502D_SET_SRC_DEPTH_V 31:0 + +#define NV502D_SET_SRC_LAYER 0x0240 +#define NV502D_SET_SRC_LAYER_V 31:0 + +#define NV502D_SET_SRC_PITCH 0x0244 +#define NV502D_SET_SRC_PITCH_V 31:0 + +#define NV502D_SET_SRC_WIDTH 0x0248 +#define NV502D_SET_SRC_WIDTH_V 31:0 + +#define NV502D_SET_SRC_HEIGHT 0x024c +#define NV502D_SET_SRC_HEIGHT_V 31:0 + +#define NV502D_SET_SRC_OFFSET_UPPER 0x0250 +#define NV502D_SET_SRC_OFFSET_UPPER_V 7:0 + +#define NV502D_SET_SRC_OFFSET_LOWER 0x0254 +#define NV502D_SET_SRC_OFFSET_LOWER_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION 0x0258 +#define NV502D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V 1:0 +#define NV502D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_NO_PROMOTION 0x00000000 +#define NV502D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_2_V 0x00000001 +#define NV502D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_2_H 0x00000002 +#define NV502D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_4 0x00000003 + +#define NV502D_SET_NUM_TPCS 0x0260 +#define NV502D_SET_NUM_TPCS_V 0:0 +#define NV502D_SET_NUM_TPCS_V_ALL 0x00000000 +#define NV502D_SET_NUM_TPCS_V_ONE 0x00000001 + +#define NV502D_SET_RENDER_ENABLE_A 0x0264 +#define NV502D_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV502D_SET_RENDER_ENABLE_B 0x0268 +#define NV502D_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV502D_SET_RENDER_ENABLE_C 0x026c +#define NV502D_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV502D_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV502D_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV502D_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV502D_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV502D_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV502D_SET_CLIP_X0 0x0280 +#define NV502D_SET_CLIP_X0_V 31:0 + +#define NV502D_SET_CLIP_Y0 0x0284 +#define NV502D_SET_CLIP_Y0_V 31:0 + +#define NV502D_SET_CLIP_WIDTH 0x0288 +#define NV502D_SET_CLIP_WIDTH_V 31:0 + +#define NV502D_SET_CLIP_HEIGHT 0x028c +#define NV502D_SET_CLIP_HEIGHT_V 31:0 + +#define NV502D_SET_CLIP_ENABLE 0x0290 +#define NV502D_SET_CLIP_ENABLE_V 0:0 +#define NV502D_SET_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV502D_SET_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV502D_SET_COLOR_KEY_FORMAT 0x0294 +#define NV502D_SET_COLOR_KEY_FORMAT_V 2:0 +#define NV502D_SET_COLOR_KEY_FORMAT_V_A16R5G6B5 0x00000000 +#define NV502D_SET_COLOR_KEY_FORMAT_V_A1R5G5B5 0x00000001 +#define NV502D_SET_COLOR_KEY_FORMAT_V_A8R8G8B8 0x00000002 +#define NV502D_SET_COLOR_KEY_FORMAT_V_A2R10G10B10 0x00000003 +#define NV502D_SET_COLOR_KEY_FORMAT_V_Y8 0x00000004 +#define NV502D_SET_COLOR_KEY_FORMAT_V_Y16 0x00000005 +#define NV502D_SET_COLOR_KEY_FORMAT_V_Y32 0x00000006 + +#define NV502D_SET_COLOR_KEY 0x0298 +#define NV502D_SET_COLOR_KEY_V 31:0 + +#define NV502D_SET_COLOR_KEY_ENABLE 0x029c +#define NV502D_SET_COLOR_KEY_ENABLE_V 0:0 +#define NV502D_SET_COLOR_KEY_ENABLE_V_FALSE 0x00000000 +#define NV502D_SET_COLOR_KEY_ENABLE_V_TRUE 0x00000001 + +#define NV502D_SET_ROP 0x02a0 +#define NV502D_SET_ROP_V 7:0 + +#define NV502D_SET_BETA1 0x02a4 +#define NV502D_SET_BETA1_V 31:0 + +#define NV502D_SET_BETA4 0x02a8 +#define NV502D_SET_BETA4_B 7:0 +#define NV502D_SET_BETA4_G 15:8 +#define NV502D_SET_BETA4_R 23:16 +#define NV502D_SET_BETA4_A 31:24 + +#define NV502D_SET_OPERATION 0x02ac +#define NV502D_SET_OPERATION_V 2:0 +#define NV502D_SET_OPERATION_V_SRCCOPY_AND 0x00000000 +#define NV502D_SET_OPERATION_V_ROP_AND 0x00000001 +#define NV502D_SET_OPERATION_V_BLEND_AND 0x00000002 +#define NV502D_SET_OPERATION_V_SRCCOPY 0x00000003 +#define NV502D_SET_OPERATION_V_ROP 0x00000004 +#define NV502D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005 +#define NV502D_SET_OPERATION_V_BLEND_PREMULT 0x00000006 + +#define NV502D_SET_PATTERN_OFFSET 0x02b0 +#define NV502D_SET_PATTERN_OFFSET_X 5:0 +#define NV502D_SET_PATTERN_OFFSET_Y 13:8 + +#define NV502D_SET_PATTERN_SELECT 0x02b4 +#define NV502D_SET_PATTERN_SELECT_V 1:0 +#define NV502D_SET_PATTERN_SELECT_V_MONOCHROME_8x8 0x00000000 +#define NV502D_SET_PATTERN_SELECT_V_MONOCHROME_64x1 0x00000001 +#define NV502D_SET_PATTERN_SELECT_V_MONOCHROME_1x64 0x00000002 +#define NV502D_SET_PATTERN_SELECT_V_COLOR 0x00000003 + +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005 + +#define NV502D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec +#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0 +#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000 +#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001 + +#define NV502D_SET_MONOCHROME_PATTERN_COLOR0 0x02f0 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR0_V 31:0 + +#define NV502D_SET_MONOCHROME_PATTERN_COLOR1 0x02f4 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR1_V 31:0 + +#define NV502D_SET_MONOCHROME_PATTERN0 0x02f8 +#define NV502D_SET_MONOCHROME_PATTERN0_V 31:0 + +#define NV502D_SET_MONOCHROME_PATTERN1 0x02fc +#define NV502D_SET_MONOCHROME_PATTERN1_V 31:0 + +#define NV502D_COLOR_PATTERN_X8R8G8B8(i) (0x0300+(i)*4) +#define NV502D_COLOR_PATTERN_X8R8G8B8_B0 7:0 +#define NV502D_COLOR_PATTERN_X8R8G8B8_G0 15:8 +#define NV502D_COLOR_PATTERN_X8R8G8B8_R0 23:16 +#define NV502D_COLOR_PATTERN_X8R8G8B8_IGNORE0 31:24 + +#define NV502D_COLOR_PATTERN_R5G6B5(i) (0x0400+(i)*4) +#define NV502D_COLOR_PATTERN_R5G6B5_B0 4:0 +#define NV502D_COLOR_PATTERN_R5G6B5_G0 10:5 +#define NV502D_COLOR_PATTERN_R5G6B5_R0 15:11 +#define NV502D_COLOR_PATTERN_R5G6B5_B1 20:16 +#define NV502D_COLOR_PATTERN_R5G6B5_G1 26:21 +#define NV502D_COLOR_PATTERN_R5G6B5_R1 31:27 + +#define NV502D_COLOR_PATTERN_X1R5G5B5(i) (0x0480+(i)*4) +#define NV502D_COLOR_PATTERN_X1R5G5B5_B0 4:0 +#define NV502D_COLOR_PATTERN_X1R5G5B5_G0 9:5 +#define NV502D_COLOR_PATTERN_X1R5G5B5_R0 14:10 +#define NV502D_COLOR_PATTERN_X1R5G5B5_IGNORE0 15:15 +#define NV502D_COLOR_PATTERN_X1R5G5B5_B1 20:16 +#define NV502D_COLOR_PATTERN_X1R5G5B5_G1 25:21 +#define NV502D_COLOR_PATTERN_X1R5G5B5_R1 30:26 +#define NV502D_COLOR_PATTERN_X1R5G5B5_IGNORE1 31:31 + +#define NV502D_COLOR_PATTERN_Y8(i) (0x0500+(i)*4) +#define NV502D_COLOR_PATTERN_Y8_Y0 7:0 +#define NV502D_COLOR_PATTERN_Y8_Y1 15:8 +#define NV502D_COLOR_PATTERN_Y8_Y2 23:16 +#define NV502D_COLOR_PATTERN_Y8_Y3 31:24 + +#define NV502D_RENDER_SOLID_PRIM_MODE 0x0580 +#define NV502D_RENDER_SOLID_PRIM_MODE_V 2:0 +#define NV502D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000 +#define NV502D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001 +#define NV502D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002 +#define NV502D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003 +#define NV502D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004 + +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR 0x0588 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0 + +#define NV502D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS 0x058c +#define NV502D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_XMAJ__XINC__YINC 0:0 +#define NV502D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_XMAJ__XDEC__YINC 4:4 +#define NV502D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_YMAJ__XINC__YINC 8:8 +#define NV502D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_YMAJ__XDEC__YINC 12:12 + +#define NV502D_RENDER_SOLID_PRIM_POINT_X_Y 0x05e0 +#define NV502D_RENDER_SOLID_PRIM_POINT_X_Y_X 15:0 +#define NV502D_RENDER_SOLID_PRIM_POINT_X_Y_Y 31:16 + +#define NV502D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8) +#define NV502D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0 + +#define NV502D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8) +#define NV502D_RENDER_SOLID_PRIM_POINT_Y_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800 +#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0 +#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001 + +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002 + +#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c +#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0 +#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001 + +#define NV502D_SET_PIXELS_FROM_CPU_WRAP 0x0810 +#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V 1:0 +#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001 +#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002 + +#define NV502D_SET_PIXELS_FROM_CPU_COLOR0 0x0814 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_COLOR1 0x0818 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c +#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0 +#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001 + +#define NV502D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838 +#define NV502D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c +#define NV502D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840 +#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844 +#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848 +#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c +#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850 +#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854 +#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858 +#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c +#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0 + +#define NV502D_PIXELS_FROM_CPU_DATA 0x0860 +#define NV502D_PIXELS_FROM_CPU_DATA_V 31:0 + +#define NV502D_SET_BIG_ENDIAN_CONTROL 0x0870 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_1 0:0 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_4 1:1 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_8 2:2 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_16 3:3 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_1 4:4 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_4 5:5 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_8 6:6 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_16 7:7 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_1 8:8 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_4 9:9 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_8 10:10 +#define NV502D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_16 11:11 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_1 12:12 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_4 13:13 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_8 14:14 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_16 15:15 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_1 16:16 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_4 17:17 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_8 18:18 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_16 19:19 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_1 20:20 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_4 21:21 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_8 22:22 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_16 23:23 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_1 24:24 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_4 25:25 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_8 26:26 +#define NV502D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_16 27:27 +#define NV502D_SET_BIG_ENDIAN_CONTROL_OVERRIDE 28:28 + +#define NV502D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE 0x0880 +#define NV502D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V 2:0 +#define NV502D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_AUTO 0x00000000 +#define NV502D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_SHAPE_8X4 0x00000001 +#define NV502D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_SHAPE_16X2 0x00000002 + +#define NV502D_SET_PIXELS_FROM_MEMORY_CORRAL_SIZE 0x0884 +#define NV502D_SET_PIXELS_FROM_MEMORY_CORRAL_SIZE_V 5:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001 + +#define NV502D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE 0x088c +#define NV502D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN 0:0 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN_CENTER 0x00000000 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN_CORNER 0x00000001 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER 4:4 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER_POINT 0x00000000 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER_BILINEAR 0x00000001 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0 +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4 +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8 +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0 +#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4 +#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8 +#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc +#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0 +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4 +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8 +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0 + +#define NV502D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc +#define NV502D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0 + +#endif /* _cl_nv50_twod_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl5039.h b/src/nouveau/nvidia-headers/classes/cl5039.h new file mode 100644 index 0000000..1ca778a --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl5039.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_nv50_memory_to_memory_format_h_ +#define _cl_nv50_memory_to_memory_format_h_ + +/* This file is generated - do not edit. */ + +#include "nvtypes.h" + +#define NV50_MEMORY_TO_MEMORY_FORMAT 0x5039 + +#define NV5039_SET_OBJECT 0x0000 +#define NV5039_SET_OBJECT_POINTER 15:0 + +#define NV5039_NO_OPERATION 0x0100 +#define NV5039_NO_OPERATION_V 31:0 + +#define NV5039_NOTIFY 0x0104 +#define NV5039_NOTIFY_TYPE 31:0 +#define NV5039_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV5039_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV5039_WAIT_FOR_IDLE 0x0110 +#define NV5039_WAIT_FOR_IDLE_V 31:0 + +#define NV5039_PM_TRIGGER 0x0140 +#define NV5039_PM_TRIGGER_V 31:0 + +#define NV5039_SET_CONTEXT_DMA_NOTIFY 0x0180 +#define NV5039_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 + +#define NV5039_SET_CONTEXT_DMA_BUFFER_IN 0x0184 +#define NV5039_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0 + +#define NV5039_SET_CONTEXT_DMA_BUFFER_OUT 0x0188 +#define NV5039_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0 + +#define NV5039_SET_SRC_MEMORY_LAYOUT 0x0200 +#define NV5039_SET_SRC_MEMORY_LAYOUT_V 0:0 +#define NV5039_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV5039_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV5039_SET_SRC_BLOCK_SIZE 0x0204 +#define NV5039_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NV5039_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV5039_SET_SRC_WIDTH 0x0208 +#define NV5039_SET_SRC_WIDTH_V 31:0 + +#define NV5039_SET_SRC_HEIGHT 0x020c +#define NV5039_SET_SRC_HEIGHT_V 31:0 + +#define NV5039_SET_SRC_DEPTH 0x0210 +#define NV5039_SET_SRC_DEPTH_V 31:0 + +#define NV5039_SET_SRC_LAYER 0x0214 +#define NV5039_SET_SRC_LAYER_V 31:0 + +#define NV5039_SET_SRC_ORIGIN 0x0218 +#define NV5039_SET_SRC_ORIGIN_X 15:0 +#define NV5039_SET_SRC_ORIGIN_Y 31:16 + +#define NV5039_SET_DST_MEMORY_LAYOUT 0x021c +#define NV5039_SET_DST_MEMORY_LAYOUT_V 0:0 +#define NV5039_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV5039_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV5039_SET_DST_BLOCK_SIZE 0x0220 +#define NV5039_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NV5039_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV5039_SET_DST_WIDTH 0x0224 +#define NV5039_SET_DST_WIDTH_V 31:0 + +#define NV5039_SET_DST_HEIGHT 0x0228 +#define NV5039_SET_DST_HEIGHT_V 31:0 + +#define NV5039_SET_DST_DEPTH 0x022c +#define NV5039_SET_DST_DEPTH_V 31:0 + +#define NV5039_SET_DST_LAYER 0x0230 +#define NV5039_SET_DST_LAYER_V 31:0 + +#define NV5039_SET_DST_ORIGIN 0x0234 +#define NV5039_SET_DST_ORIGIN_X 15:0 +#define NV5039_SET_DST_ORIGIN_Y 31:16 + +#define NV5039_OFFSET_IN_UPPER 0x0238 +#define NV5039_OFFSET_IN_UPPER_VALUE 7:0 + +#define NV5039_OFFSET_OUT_UPPER 0x023c +#define NV5039_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NV5039_OFFSET_IN 0x030c +#define NV5039_OFFSET_IN_VALUE 31:0 + +#define NV5039_OFFSET_OUT 0x0310 +#define NV5039_OFFSET_OUT_VALUE 31:0 + +#define NV5039_PITCH_IN 0x0314 +#define NV5039_PITCH_IN_VALUE 31:0 + +#define NV5039_PITCH_OUT 0x0318 +#define NV5039_PITCH_OUT_VALUE 31:0 + +#define NV5039_LINE_LENGTH_IN 0x031c +#define NV5039_LINE_LENGTH_IN_VALUE 31:0 + +#define NV5039_LINE_COUNT 0x0320 +#define NV5039_LINE_COUNT_VALUE 31:0 + +#define NV5039_FORMAT 0x0324 +#define NV5039_FORMAT_IN 7:0 +#define NV5039_FORMAT_IN_ONE 0x00000001 +// removing options greater than _ONE due to hardware bug 294038. +// it is POSSIBLE to use them, but doing so will require some nasty workarounds, +// such as handling timeouts on notifiers that the HW will fail to write. +// as of july 2007, no driver needs them. hopefully they never will. +// #define NV5039_FORMAT_IN_TWO 0x00000002 +// #define NV5039_FORMAT_IN_FOUR 0x00000004 +// #define NV5039_FORMAT_IN_EIGHT 0x00000008 +// #define NV5039_FORMAT_IN_SIXTEEN 0x00000010 +#define NV5039_FORMAT_OUT 15:8 +#define NV5039_FORMAT_OUT_ONE 0x00000001 +// #define NV5039_FORMAT_OUT_TWO 0x00000002 +// #define NV5039_FORMAT_OUT_FOUR 0x00000004 +// #define NV5039_FORMAT_OUT_EIGHT 0x00000008 +// #define NV5039_FORMAT_OUT_SIXTEEN 0x00000010 + +#define NV5039_BUFFER_NOTIFY 0x0328 +#define NV5039_BUFFER_NOTIFY_TYPE 31:0 +#define NV5039_BUFFER_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV5039_BUFFER_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#endif /* _cl_nv50_memory_to_memory_format_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl50c0.h b/src/nouveau/nvidia-headers/classes/cl50c0.h new file mode 100644 index 0000000..ba7e2cf --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl50c0.h @@ -0,0 +1,598 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_nv50_compute_h_ +#define _cl_nv50_compute_h_ + +/* This file is generated - do not edit. */ + +#include "nvtypes.h" + +#define NV50_COMPUTE 0x50C0 + +#define NV50C0_SET_OBJECT 0x0000 +#define NV50C0_SET_OBJECT_POINTER 15:0 + +#define NV50C0_NO_OPERATION 0x0100 +#define NV50C0_NO_OPERATION_V 31:0 + +#define NV50C0_NOTIFY 0x0104 +#define NV50C0_NOTIFY_TYPE 31:0 +#define NV50C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV50C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV50C0_WAIT_FOR_IDLE 0x0110 +#define NV50C0_WAIT_FOR_IDLE_V 31:0 + +#define NV50C0_PM_TRIGGER 0x0140 +#define NV50C0_PM_TRIGGER_V 31:0 + +#define NV50C0_SET_CONTEXT_DMA_NOTIFY 0x0180 +#define NV50C0_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_GLOBAL_MEM 0x01a0 +#define NV50C0_SET_CTX_DMA_GLOBAL_MEM_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_SEMAPHORE 0x01a4 +#define NV50C0_SET_CTX_DMA_SEMAPHORE_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_SHADER_THREAD_MEMORY 0x01b8 +#define NV50C0_SET_CTX_DMA_SHADER_THREAD_MEMORY_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_SHADER_THREAD_STACK 0x01bc +#define NV50C0_SET_CTX_DMA_SHADER_THREAD_STACK_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_SHADER_PROGRAM 0x01c0 +#define NV50C0_SET_CTX_DMA_SHADER_PROGRAM_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_TEXTURE_SAMPLER 0x01c4 +#define NV50C0_SET_CTX_DMA_TEXTURE_SAMPLER_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_TEXTURE_HEADERS 0x01c8 +#define NV50C0_SET_CTX_DMA_TEXTURE_HEADERS_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_TEXTURE 0x01cc +#define NV50C0_SET_CTX_DMA_TEXTURE_HANDLE 31:0 + +#define NV50C0_DECRYPTION_CONTROL(j) (0x0200+(j)*16) +#define NV50C0_DECRYPTION_CONTROL_ALGORITHM 15:0 +#define NV50C0_DECRYPTION_CONTROL_ALGORITHM_NV17_COMPATIBLE 0x00000000 +#define NV50C0_DECRYPTION_CONTROL_KEY_COUNT 23:16 + +#define NV50C0_DECRYPTION_QUERY_SESSION_KEY(j) (0x0204+(j)*16) +#define NV50C0_DECRYPTION_QUERY_SESSION_KEY_V 31:0 + +#define NV50C0_DECRYPTION_GET_SESSION_KEY(j) (0x0208+(j)*16) +#define NV50C0_DECRYPTION_GET_SESSION_KEY_V 31:0 + +#define NV50C0_DECRYPTION_SET_ENCRYPTION(j) (0x020c+(j)*16) +#define NV50C0_DECRYPTION_SET_ENCRYPTION_V 31:0 + +#define NV50C0_SET_CTA_PROGRAM_A 0x0210 +#define NV50C0_SET_CTA_PROGRAM_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_CTA_PROGRAM_B 0x0214 +#define NV50C0_SET_CTA_PROGRAM_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_SHADER_THREAD_STACK_A 0x0218 +#define NV50C0_SET_SHADER_THREAD_STACK_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_SHADER_THREAD_STACK_B 0x021c +#define NV50C0_SET_SHADER_THREAD_STACK_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_SHADER_THREAD_STACK_C 0x0220 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE 3:0 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__0 0x00000000 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__1 0x00000001 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__2 0x00000002 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__4 0x00000003 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__8 0x00000004 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__16 0x00000005 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__32 0x00000006 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__64 0x00000007 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__128 0x00000008 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__256 0x00000009 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__512 0x0000000A +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__1024 0x0000000B +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__2048 0x0000000C +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__4096 0x0000000D + +#define NV50C0_SET_API_CALL_LIMIT 0x0224 +#define NV50C0_SET_API_CALL_LIMIT_CTA 3:0 +#define NV50C0_SET_API_CALL_LIMIT_CTA__0 0x00000000 +#define NV50C0_SET_API_CALL_LIMIT_CTA__1 0x00000001 +#define NV50C0_SET_API_CALL_LIMIT_CTA__2 0x00000002 +#define NV50C0_SET_API_CALL_LIMIT_CTA__4 0x00000003 +#define NV50C0_SET_API_CALL_LIMIT_CTA__8 0x00000004 +#define NV50C0_SET_API_CALL_LIMIT_CTA__16 0x00000005 +#define NV50C0_SET_API_CALL_LIMIT_CTA__32 0x00000006 +#define NV50C0_SET_API_CALL_LIMIT_CTA__64 0x00000007 +#define NV50C0_SET_API_CALL_LIMIT_CTA__128 0x00000008 +#define NV50C0_SET_API_CALL_LIMIT_CTA_NO_CHECK 0x0000000F + +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL 0x0228 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PIXEL_ASSOCIATIVITY 7:4 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_NONPIXEL_ASSOCIATIVITY 11:8 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_PIXEL_ASSOCIATIVITY 15:12 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_NONPIXEL_ASSOCIATIVITY 19:16 + +#define NV50C0_SET_TEX_SAMPLER_POOL_A 0x022c +#define NV50C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_TEX_SAMPLER_POOL_B 0x0230 +#define NV50C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_TEX_SAMPLER_POOL_C 0x0234 +#define NV50C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV50C0_LOAD_CONSTANT_SELECTOR 0x0238 +#define NV50C0_LOAD_CONSTANT_SELECTOR_TABLE_INDEX 7:0 +#define NV50C0_LOAD_CONSTANT_SELECTOR_CONSTANT_INDEX 23:8 + +#define NV50C0_LOAD_CONSTANT(i) (0x023c+(i)*4) +#define NV50C0_LOAD_CONSTANT_V 31:0 + +#define NV50C0_INVALIDATE_SAMPLER_CACHE 0x027c +#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV50C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x0280 +#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV50C0_SET_SM_TIMEOUT_INTERVAL 0x0288 +#define NV50C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV50C0_TEST_FOR_COMPUTE 0x028c +#define NV50C0_TEST_FOR_COMPUTE_V 31:0 + +#define NV50C0_SET_SHADER_SCHEDULING 0x0290 +#define NV50C0_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV50C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV50C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV50C0_SET_SHADER_THREAD_MEMORY_A 0x0294 +#define NV50C0_SET_SHADER_THREAD_MEMORY_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_SHADER_THREAD_MEMORY_B 0x0298 +#define NV50C0_SET_SHADER_THREAD_MEMORY_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_SHADER_THREAD_MEMORY_C 0x029c +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE 3:0 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__0 0x00000000 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1 0x00000001 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2 0x00000002 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4 0x00000003 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__8 0x00000004 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__16 0x00000005 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__32 0x00000006 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__64 0x00000007 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__128 0x00000008 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__256 0x00000009 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__512 0x0000000A +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1024 0x0000000B +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2048 0x0000000C +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4096 0x0000000D + +#define NV50C0_SET_WORK_DISTRIBUTION 0x02a0 +#define NV50C0_SET_WORK_DISTRIBUTION_V 3:0 +#define NV50C0_SET_WORK_DISTRIBUTION_V_HARDWARE_POLICY 0x00000000 +#define NV50C0_SET_WORK_DISTRIBUTION_V_WIDE_DYNAMIC 0x00000001 +#define NV50C0_SET_WORK_DISTRIBUTION_V_DEEP_DYNAMIC 0x00000002 +#define NV50C0_SET_WORK_DISTRIBUTION_V_WIDE_FIXED 0x00000003 +#define NV50C0_SET_WORK_DISTRIBUTION_V_DEEP_FIXED 0x00000004 +#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_DYNAMIC 0x00000005 +#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_DYNAMIC 0x00000006 +#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_FIXED 0x00000007 +#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_FIXED 0x00000008 + +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_A 0x02a4 +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_A_OFFSET_UPPER 7:0 + +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_B 0x02a8 +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_B_OFFSET_LOWER 31:0 + +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C 0x02ac +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C_SIZE 15:0 +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C_ENTRY 23:16 + +#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL 0x02b0 +#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK 0:0 +#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_FALSE 0x00000000 +#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_TRUE 0x00000001 +#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_SUBSET_MASK 31:1 + +#define NV50C0_SET_CTA_RESOURCE_ALLOCATION 0x02b4 +#define NV50C0_SET_CTA_RESOURCE_ALLOCATION_THREAD_COUNT 15:0 +#define NV50C0_SET_CTA_RESOURCE_ALLOCATION_BARRIER_COUNT 23:16 + +#define NV50C0_SET_CTA_THREAD_CONTROL 0x02b8 +#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH 0:0 +#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_FALSE 0x00000000 +#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_TRUE 0x00000001 + +#define NV50C0_SET_PHASE_ID_CONTROL 0x02bc +#define NV50C0_SET_PHASE_ID_CONTROL_WINDOW_SIZE 2:0 +#define NV50C0_SET_PHASE_ID_CONTROL_LOCK_PHASE 6:4 + +#define NV50C0_SET_CTA_REGISTER_COUNT 0x02c0 +#define NV50C0_SET_CTA_REGISTER_COUNT_V 7:0 + +#define NV50C0_SET_TEX_HEADER_POOL_A 0x02c4 +#define NV50C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_TEX_HEADER_POOL_B 0x02c8 +#define NV50C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_TEX_HEADER_POOL_C 0x02cc +#define NV50C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x02d0+(i)*4) +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL(i) (0x02e0+(i)*4) +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EDGE 0:0 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK 6:4 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_ACE 0x00000000 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DIS 0x00000001 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DSM 0x00000002 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_PIC 0x00000003 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_STP 0x00000004 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_XIU 0x00000005 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_FUNC 23:8 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EVENT 31:24 + +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x02f0 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 3:0 + +#define NV50C0_RESET_CTA_TRACKING_RAM 0x02f4 +#define NV50C0_RESET_CTA_TRACKING_RAM_V 31:0 + +#define NV50C0_INITIALIZE 0x02f8 +#define NV50C0_INITIALIZE_INIT_CTA_SHAPE 0:0 +#define NV50C0_INITIALIZE_INIT_CTA_SHAPE_FALSE 0x00000000 +#define NV50C0_INITIALIZE_INIT_CTA_SHAPE_TRUE 0x00000001 + +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE 0x02fc +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM 2:0 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 + +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL 0x0300 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V 2:0 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 + +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE 0x0304 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM 2:0 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 + +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL 0x0308 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V 2:0 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 + +#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS 0x030c +#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA 0:0 +#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_FALSE 0x00000000 +#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_TRUE 0x00000001 + +#define NV50C0_SET_REPORT_SEMAPHORE_A 0x0310 +#define NV50C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_REPORT_SEMAPHORE_B 0x0314 +#define NV50C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_REPORT_SEMAPHORE_C 0x0318 +#define NV50C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV50C0_SET_REPORT_SEMAPHORE_D 0x031c +#define NV50C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV50C0_SET_REPORT_SEMAPHORE_D_OPERATION_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_RELEASE 2:2 +#define NV50C0_SET_REPORT_SEMAPHORE_D_RELEASE_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_ACQUIRE 3:3 +#define NV50C0_SET_REPORT_SEMAPHORE_D_ACQUIRE_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 7:4 +#define NV50C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_COMPARISON 8:8 +#define NV50C0_SET_REPORT_SEMAPHORE_D_COMPARISON_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 9:9 +#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV50C0_SET_REPORT_SEMAPHORE_D_REPORT 14:10 +#define NV50C0_SET_REPORT_SEMAPHORE_D_REPORT_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 15:15 +#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 + +#define NV50C0_SET_LAUNCH_ENABLE_A 0x0320 +#define NV50C0_SET_LAUNCH_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_LAUNCH_ENABLE_B 0x0324 +#define NV50C0_SET_LAUNCH_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_LAUNCH_ENABLE_C 0x0328 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE 2:0 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_FALSE 0x00000000 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_TRUE 0x00000001 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE 0x032c +#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE 31:0 +#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NV50C0_PIPE_NOP 0x0330 +#define NV50C0_PIPE_NOP_V 31:0 + +#define NV50C0_SET_SPARE00 0x0340 +#define NV50C0_SET_SPARE00_V 31:0 + +#define NV50C0_SET_SPARE01 0x0344 +#define NV50C0_SET_SPARE01_V 31:0 + +#define NV50C0_SET_SPARE02 0x0348 +#define NV50C0_SET_SPARE02_V 31:0 + +#define NV50C0_SET_SPARE03 0x034c +#define NV50C0_SET_SPARE03_V 31:0 + +#define NV50C0_SET_GLOBAL_COLOR_KEY 0x0358 +#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE 31:0 +#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV50C0_RESET_REF_COUNT 0x035c +#define NV50C0_RESET_REF_COUNT_REF_CNT 3:0 + +#define NV50C0_WAIT_REF_COUNT 0x0360 +#define NV50C0_WAIT_REF_COUNT_COMPARE 7:4 +#define NV50C0_WAIT_REF_COUNT_COMPARE_COUNT_QUIESENT 0x00000000 +#define NV50C0_WAIT_REF_COUNT_COMPARE_VALUE_EQUAL 0x00000001 +#define NV50C0_WAIT_REF_COUNT_COMPARE_VALUE_CLOCKHAND 0x00000002 +#define NV50C0_WAIT_REF_COUNT_REF_CNT 11:8 + +#define NV50C0_SET_REF_COUNT_VALUE 0x0364 +#define NV50C0_SET_REF_COUNT_VALUE_V 31:0 + +#define NV50C0_LAUNCH 0x0368 +#define NV50C0_LAUNCH_V 31:0 + +#define NV50C0_SET_LAUNCH_ID 0x036c +#define NV50C0_SET_LAUNCH_ID_REF_CNT 3:0 + +#define NV50C0_SET_LAUNCH_CONTROL 0x0370 +#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH 7:0 +#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH_MANUAL_LAUNCH 0x00000000 +#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH_AUTO_LAUNCH 0x00000001 + +#define NV50C0_SET_PARAMETER_SIZE 0x0374 +#define NV50C0_SET_PARAMETER_SIZE_AUTO_LAUNCH_INDEX 7:0 +#define NV50C0_SET_PARAMETER_SIZE_COUNT 15:8 + +#define NV50C0_SET_SAMPLER_BINDING 0x0378 +#define NV50C0_SET_SAMPLER_BINDING_V 0:0 +#define NV50C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV50C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV50C0_SET_SHADER_CONTROL 0x037c +#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV50C0_INVALIDATE_SHADER_CACHE 0x0380 +#define NV50C0_INVALIDATE_SHADER_CACHE_V 1:0 +#define NV50C0_INVALIDATE_SHADER_CACHE_V_ALL 0x00000000 +#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1 0x00000001 +#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1_DATA 0x00000002 +#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1_INSTRUCTION 0x00000003 + +#define NV50C0_SET_RASTER_CONTROL 0x0384 +#define NV50C0_SET_RASTER_CONTROL_PROGRAM 7:0 +#define NV50C0_SET_RASTER_CONTROL_PROGRAM_DISABLE 0x00000000 +#define NV50C0_SET_RASTER_CONTROL_FIXED 15:8 +#define NV50C0_SET_RASTER_CONTROL_FIXED_DISABLE 0x00000000 +#define NV50C0_SET_RASTER_CONTROL_FIXED_SIMPLE 0x00000001 +#define NV50C0_SET_RASTER_CONTROL_FIXED_DXVA_RUN_CODED 0x00000002 +#define NV50C0_SET_RASTER_CONTROL_DECRYPTION 23:16 +#define NV50C0_SET_RASTER_CONTROL_DECRYPTION_DISABLE 0x00000000 +#define NV50C0_SET_RASTER_CONTROL_DECRYPTION_ENABLE 0x00000001 + +#define NV50C0_SET_CTA_FLAGS 0x0388 +#define NV50C0_SET_CTA_FLAGS_V 15:0 + +#define NV50C0_SET_CTA_RASTER_SIZE 0x03a4 +#define NV50C0_SET_CTA_RASTER_SIZE_WIDTH 15:0 +#define NV50C0_SET_CTA_RASTER_SIZE_HEIGHT 31:16 + +#define NV50C0_SET_CTA_GRF_SIZE 0x03a8 +#define NV50C0_SET_CTA_GRF_SIZE_V 31:0 + +#define NV50C0_SET_CTA_THREAD_DIMENSION_A 0x03ac +#define NV50C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 +#define NV50C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 + +#define NV50C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 +#define NV50C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 + +#define NV50C0_SET_CTA_PROGRAM_START 0x03b4 +#define NV50C0_SET_CTA_PROGRAM_START_OFFSET 23:0 + +#define NV50C0_SET_CTA_REGISTER_ALLOCATION 0x03b8 +#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V 31:0 +#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V_THICK 0x00000001 +#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V_THIN 0x00000002 + +#define NV50C0_SET_CTA_TEXTURE 0x03bc +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER 0x03c0 +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID 0:0 +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV50C0_BIND_CTA_TEXTURE_HEADER 0x03c4 +#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID 0:0 +#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV50C0_BIND_CTA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV50C0_BIND_CTA_TEXTURE_HEADER_INDEX 30:9 + +#define NV50C0_BIND_CONSTANT_BUFFER 0x03c8 +#define NV50C0_BIND_CONSTANT_BUFFER_VALID 3:0 +#define NV50C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV50C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_TYPE 7:4 +#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_TYPE_CTA 0x00000000 +#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 11:8 +#define NV50C0_BIND_CONSTANT_BUFFER_TABLE_ENTRY 19:12 + +#define NV50C0_PREFETCH_TEXTURE_SAMPLER 0x03cc +#define NV50C0_PREFETCH_TEXTURE_SAMPLER_INDEX 21:0 + +#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE 0x03d0 +#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 5:4 +#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 +#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L2_ONLY 0x00000001 +#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_AND_L2 0x00000002 + +#define NV50C0_SET_SHADER_EXCEPTIONS 0x03ec +#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV50C0_SET_GLOBAL_MEM_A(j) (0x0400+(j)*32) +#define NV50C0_SET_GLOBAL_MEM_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_GLOBAL_MEM_B(j) (0x0404+(j)*32) +#define NV50C0_SET_GLOBAL_MEM_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_GLOBAL_MEM_SIZE(j) (0x0408+(j)*32) +#define NV50C0_SET_GLOBAL_MEM_SIZE_BLOCK_PITCH 31:0 + +#define NV50C0_SET_GLOBAL_MEM_LIMIT(j) (0x040c+(j)*32) +#define NV50C0_SET_GLOBAL_MEM_LIMIT_MAX 31:0 + +#define NV50C0_SET_GLOBAL_MEM_FORMAT(j) (0x0410+(j)*32) +#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT 0:0 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_PITCH 0x00000001 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH 7:4 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH_ONE_GOB 0x00000000 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT 11:8 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_ONE_GOB 0x00000000 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_TWO_GOBS 0x00000001 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_FOUR_GOBS 0x00000002 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV50C0_PARAMETER(i) (0x0600+(i)*4) +#define NV50C0_PARAMETER_V 31:0 + +#define NV50C0_SET_SPARE_NOOP00 0x0700 +#define NV50C0_SET_SPARE_NOOP00_V 31:0 + +#define NV50C0_SET_SPARE_NOOP01 0x0704 +#define NV50C0_SET_SPARE_NOOP01_V 31:0 + +#define NV50C0_SET_SPARE_NOOP02 0x0708 +#define NV50C0_SET_SPARE_NOOP02_V 31:0 + +#define NV50C0_SET_SPARE_NOOP03 0x070c +#define NV50C0_SET_SPARE_NOOP03_V 31:0 + +#define NV50C0_SET_SPARE_NOOP04 0x0710 +#define NV50C0_SET_SPARE_NOOP04_V 31:0 + +#define NV50C0_SET_SPARE_NOOP05 0x0714 +#define NV50C0_SET_SPARE_NOOP05_V 31:0 + +#define NV50C0_SET_SPARE_NOOP06 0x0718 +#define NV50C0_SET_SPARE_NOOP06_V 31:0 + +#define NV50C0_SET_SPARE_NOOP07 0x071c +#define NV50C0_SET_SPARE_NOOP07_V 31:0 + +#define NV50C0_SET_SPARE_NOOP08 0x0720 +#define NV50C0_SET_SPARE_NOOP08_V 31:0 + +#define NV50C0_SET_SPARE_NOOP09 0x0724 +#define NV50C0_SET_SPARE_NOOP09_V 31:0 + +#define NV50C0_SET_SPARE_NOOP10 0x0728 +#define NV50C0_SET_SPARE_NOOP10_V 31:0 + +#define NV50C0_SET_SPARE_NOOP11 0x072c +#define NV50C0_SET_SPARE_NOOP11_V 31:0 + +#define NV50C0_SET_SPARE_NOOP12 0x0730 +#define NV50C0_SET_SPARE_NOOP12_V 31:0 + +#define NV50C0_SET_SPARE_NOOP13 0x0734 +#define NV50C0_SET_SPARE_NOOP13_V 31:0 + +#define NV50C0_SET_SPARE_NOOP14 0x0738 +#define NV50C0_SET_SPARE_NOOP14_V 31:0 + +#define NV50C0_SET_SPARE_NOOP15 0x073c +#define NV50C0_SET_SPARE_NOOP15_V 31:0 + +#endif /* _cl_nv50_compute_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl85b5.h b/src/nouveau/nvidia-headers/classes/cl85b5.h new file mode 100644 index 0000000..76baefd --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl85b5.h @@ -0,0 +1,222 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _cl85b5_h_ +#define _cl85b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define GT212_DMA_COPY (0x000085B5) + +#define NV85B5_NOP (0x00000100) +#define NV85B5_NOP_PARAMETER 31:0 +#define NV85B5_PM_TRIGGER (0x00000140) +#define NV85B5_PM_TRIGGER_V 31:0 +#define NV85B5_SET_CTX_DMA(b) (0x00000180 + (b)*0x00000004) +#define NV85B5_SET_CTX_DMA_HANDLE 31:0 +#define NV85B5_SET_APPLICATION_ID (0x00000200) +#define NV85B5_SET_APPLICATION_ID_ID 31:0 +#define NV85B5_SET_APPLICATION_ID_ID_NORMAL (0x00000001) +#define NV85B5_SET_WATCHDOG_TIMER (0x00000204) +#define NV85B5_SET_WATCHDOG_TIMER_TIMER 31:0 +#define NV85B5_SET_SEMAPHORE_A (0x00000240) +#define NV85B5_SET_SEMAPHORE_A_UPPER 7:0 +#define NV85B5_SET_SEMAPHORE_A_CTX_DMA 31:28 +#define NV85B5_SET_SEMAPHORE_B (0x00000244) +#define NV85B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NV85B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NV85B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NV85B5_LAUNCH_DMA (0x00000300) +#define NV85B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NV85B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NV85B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NV85B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NV85B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NV85B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NV85B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NV85B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NV85B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NV85B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NV85B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NV85B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NV85B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NV85B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NV85B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NV85B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NV85B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV85B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV85B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NV85B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV85B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV85B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NV85B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NV85B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NV85B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NV85B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NV85B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NV85B5_OFFSET_IN_UPPER (0x00000400) +#define NV85B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NV85B5_OFFSET_IN_UPPER_CTX_DMA 31:28 +#define NV85B5_OFFSET_IN_LOWER (0x00000404) +#define NV85B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NV85B5_OFFSET_OUT_UPPER (0x00000408) +#define NV85B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NV85B5_OFFSET_OUT_UPPER_CTX_DMA 31:28 +#define NV85B5_OFFSET_OUT_LOWER (0x0000040C) +#define NV85B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NV85B5_PITCH_IN (0x00000410) +#define NV85B5_PITCH_IN_VALUE 31:0 +#define NV85B5_PITCH_OUT (0x00000414) +#define NV85B5_PITCH_OUT_VALUE 31:0 +#define NV85B5_LINE_LENGTH_IN (0x00000418) +#define NV85B5_LINE_LENGTH_IN_VALUE 31:0 +#define NV85B5_LINE_COUNT (0x0000041C) +#define NV85B5_LINE_COUNT_VALUE 31:0 +#define NV85B5_SET_REMAP_CONST_A (0x00000700) +#define NV85B5_SET_REMAP_CONST_A_V 31:0 +#define NV85B5_SET_REMAP_CONST_B (0x00000704) +#define NV85B5_SET_REMAP_CONST_B_V 31:0 +#define NV85B5_SET_REMAP_COMPONENTS (0x00000708) +#define NV85B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NV85B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NV85B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NV85B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NV85B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NV85B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NV85B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NV85B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NV85B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NV85B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NV85B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NV85B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NV85B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NV85B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NV85B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NV85B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NV85B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NV85B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NV85B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NV85B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NV85B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NV85B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NV85B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NV85B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NV85B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NV85B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NV85B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NV85B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NV85B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NV85B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NV85B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NV85B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NV85B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NV85B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NV85B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NV85B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NV85B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NV85B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV85B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NV85B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NV85B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NV85B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NV85B5_SET_DST_WIDTH (0x00000710) +#define NV85B5_SET_DST_WIDTH_V 31:0 +#define NV85B5_SET_DST_HEIGHT (0x00000714) +#define NV85B5_SET_DST_HEIGHT_V 31:0 +#define NV85B5_SET_DST_DEPTH (0x00000718) +#define NV85B5_SET_DST_DEPTH_V 31:0 +#define NV85B5_SET_DST_LAYER (0x0000071C) +#define NV85B5_SET_DST_LAYER_V 31:0 +#define NV85B5_SET_DST_ORIGIN (0x00000720) +#define NV85B5_SET_DST_ORIGIN_X 15:0 +#define NV85B5_SET_DST_ORIGIN_Y 31:16 +#define NV85B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NV85B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NV85B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NV85B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NV85B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NV85B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NV85B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NV85B5_SET_SRC_WIDTH (0x0000072C) +#define NV85B5_SET_SRC_WIDTH_V 31:0 +#define NV85B5_SET_SRC_HEIGHT (0x00000730) +#define NV85B5_SET_SRC_HEIGHT_V 31:0 +#define NV85B5_SET_SRC_DEPTH (0x00000734) +#define NV85B5_SET_SRC_DEPTH_V 31:0 +#define NV85B5_SET_SRC_LAYER (0x00000738) +#define NV85B5_SET_SRC_LAYER_V 31:0 +#define NV85B5_SET_SRC_ORIGIN (0x0000073C) +#define NV85B5_SET_SRC_ORIGIN_X 15:0 +#define NV85B5_SET_SRC_ORIGIN_Y 31:16 +#define NV85B5_PM_TRIGGER_END (0x00001114) +#define NV85B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl85b5_h + diff --git a/src/nouveau/nvidia-headers/classes/cl85c0.h b/src/nouveau/nvidia-headers/classes/cl85c0.h new file mode 100644 index 0000000..ba9ac56 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl85c0.h @@ -0,0 +1,607 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_gt214_compute_h_ +#define _cl_gt214_compute_h_ + +/* This file is generated - do not edit. */ + +#include "nvtypes.h" + +#define GT214_COMPUTE 0x85C0 + +#define NV85C0_SET_OBJECT 0x0000 +#define NV85C0_SET_OBJECT_POINTER 15:0 + +#define NV85C0_NO_OPERATION 0x0100 +#define NV85C0_NO_OPERATION_V 31:0 + +#define NV85C0_NOTIFY 0x0104 +#define NV85C0_NOTIFY_TYPE 31:0 +#define NV85C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV85C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV85C0_WAIT_FOR_IDLE 0x0110 +#define NV85C0_WAIT_FOR_IDLE_V 31:0 + +#define NV85C0_PM_TRIGGER 0x0140 +#define NV85C0_PM_TRIGGER_V 31:0 + +#define NV85C0_SET_CONTEXT_DMA_NOTIFY 0x0180 +#define NV85C0_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_GLOBAL_MEM 0x01a0 +#define NV85C0_SET_CTX_DMA_GLOBAL_MEM_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_SEMAPHORE 0x01a4 +#define NV85C0_SET_CTX_DMA_SEMAPHORE_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_SHADER_THREAD_MEMORY 0x01b8 +#define NV85C0_SET_CTX_DMA_SHADER_THREAD_MEMORY_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_SHADER_THREAD_STACK 0x01bc +#define NV85C0_SET_CTX_DMA_SHADER_THREAD_STACK_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_SHADER_PROGRAM 0x01c0 +#define NV85C0_SET_CTX_DMA_SHADER_PROGRAM_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_TEXTURE_SAMPLER 0x01c4 +#define NV85C0_SET_CTX_DMA_TEXTURE_SAMPLER_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_TEXTURE_HEADERS 0x01c8 +#define NV85C0_SET_CTX_DMA_TEXTURE_HEADERS_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_TEXTURE 0x01cc +#define NV85C0_SET_CTX_DMA_TEXTURE_HANDLE 31:0 + +#define NV85C0_DECRYPTION_CONTROL(j) (0x0200+(j)*16) +#define NV85C0_DECRYPTION_CONTROL_ALGORITHM 15:0 +#define NV85C0_DECRYPTION_CONTROL_ALGORITHM_NV17_COMPATIBLE 0x00000000 +#define NV85C0_DECRYPTION_CONTROL_KEY_COUNT 23:16 + +#define NV85C0_DECRYPTION_QUERY_SESSION_KEY(j) (0x0204+(j)*16) +#define NV85C0_DECRYPTION_QUERY_SESSION_KEY_V 31:0 + +#define NV85C0_DECRYPTION_GET_SESSION_KEY(j) (0x0208+(j)*16) +#define NV85C0_DECRYPTION_GET_SESSION_KEY_V 31:0 + +#define NV85C0_DECRYPTION_SET_ENCRYPTION(j) (0x020c+(j)*16) +#define NV85C0_DECRYPTION_SET_ENCRYPTION_V 31:0 + +#define NV85C0_SET_CTA_PROGRAM_A 0x0210 +#define NV85C0_SET_CTA_PROGRAM_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_CTA_PROGRAM_B 0x0214 +#define NV85C0_SET_CTA_PROGRAM_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_SHADER_THREAD_STACK_A 0x0218 +#define NV85C0_SET_SHADER_THREAD_STACK_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_SHADER_THREAD_STACK_B 0x021c +#define NV85C0_SET_SHADER_THREAD_STACK_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_SHADER_THREAD_STACK_C 0x0220 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE 3:0 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__0 0x00000000 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__1 0x00000001 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__2 0x00000002 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__4 0x00000003 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__8 0x00000004 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__16 0x00000005 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__32 0x00000006 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__64 0x00000007 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__128 0x00000008 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__256 0x00000009 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__512 0x0000000A +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__1024 0x0000000B +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__2048 0x0000000C +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__4096 0x0000000D + +#define NV85C0_SET_API_CALL_LIMIT 0x0224 +#define NV85C0_SET_API_CALL_LIMIT_CTA 3:0 +#define NV85C0_SET_API_CALL_LIMIT_CTA__0 0x00000000 +#define NV85C0_SET_API_CALL_LIMIT_CTA__1 0x00000001 +#define NV85C0_SET_API_CALL_LIMIT_CTA__2 0x00000002 +#define NV85C0_SET_API_CALL_LIMIT_CTA__4 0x00000003 +#define NV85C0_SET_API_CALL_LIMIT_CTA__8 0x00000004 +#define NV85C0_SET_API_CALL_LIMIT_CTA__16 0x00000005 +#define NV85C0_SET_API_CALL_LIMIT_CTA__32 0x00000006 +#define NV85C0_SET_API_CALL_LIMIT_CTA__64 0x00000007 +#define NV85C0_SET_API_CALL_LIMIT_CTA__128 0x00000008 +#define NV85C0_SET_API_CALL_LIMIT_CTA_NO_CHECK 0x0000000F + +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL 0x0228 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PIXEL_ASSOCIATIVITY 7:4 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_NONPIXEL_ASSOCIATIVITY 11:8 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_PIXEL_ASSOCIATIVITY 15:12 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_NONPIXEL_ASSOCIATIVITY 19:16 + +#define NV85C0_SET_TEX_SAMPLER_POOL_A 0x022c +#define NV85C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_TEX_SAMPLER_POOL_B 0x0230 +#define NV85C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_TEX_SAMPLER_POOL_C 0x0234 +#define NV85C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV85C0_LOAD_CONSTANT_SELECTOR 0x0238 +#define NV85C0_LOAD_CONSTANT_SELECTOR_TABLE_INDEX 7:0 +#define NV85C0_LOAD_CONSTANT_SELECTOR_CONSTANT_INDEX 23:8 + +#define NV85C0_LOAD_CONSTANT(i) (0x023c+(i)*4) +#define NV85C0_LOAD_CONSTANT_V 31:0 + +#define NV85C0_INVALIDATE_SAMPLER_CACHE 0x027c +#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV85C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x0280 +#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV85C0_SET_SM_TIMEOUT_INTERVAL 0x0288 +#define NV85C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV85C0_TEST_FOR_COMPUTE 0x028c +#define NV85C0_TEST_FOR_COMPUTE_V 31:0 + +#define NV85C0_SET_SHADER_SCHEDULING 0x0290 +#define NV85C0_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV85C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV85C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV85C0_SET_SHADER_THREAD_MEMORY_A 0x0294 +#define NV85C0_SET_SHADER_THREAD_MEMORY_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_SHADER_THREAD_MEMORY_B 0x0298 +#define NV85C0_SET_SHADER_THREAD_MEMORY_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_SHADER_THREAD_MEMORY_C 0x029c +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE 3:0 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__0 0x00000000 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1 0x00000001 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2 0x00000002 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4 0x00000003 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__8 0x00000004 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__16 0x00000005 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__32 0x00000006 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__64 0x00000007 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__128 0x00000008 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__256 0x00000009 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__512 0x0000000A +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1024 0x0000000B +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2048 0x0000000C +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4096 0x0000000D + +#define NV85C0_SET_WORK_DISTRIBUTION 0x02a0 +#define NV85C0_SET_WORK_DISTRIBUTION_V 3:0 +#define NV85C0_SET_WORK_DISTRIBUTION_V_HARDWARE_POLICY 0x00000000 +#define NV85C0_SET_WORK_DISTRIBUTION_V_WIDE_DYNAMIC 0x00000001 +#define NV85C0_SET_WORK_DISTRIBUTION_V_DEEP_DYNAMIC 0x00000002 +#define NV85C0_SET_WORK_DISTRIBUTION_V_WIDE_FIXED 0x00000003 +#define NV85C0_SET_WORK_DISTRIBUTION_V_DEEP_FIXED 0x00000004 +#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_DYNAMIC 0x00000005 +#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_DYNAMIC 0x00000006 +#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_FIXED 0x00000007 +#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_FIXED 0x00000008 + +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_A 0x02a4 +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_A_OFFSET_UPPER 7:0 + +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_B 0x02a8 +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_B_OFFSET_LOWER 31:0 + +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C 0x02ac +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C_SIZE 15:0 +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C_ENTRY 23:16 + +#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL 0x02b0 +#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK 0:0 +#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_FALSE 0x00000000 +#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_TRUE 0x00000001 +#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_SUBSET_MASK 31:1 + +#define NV85C0_SET_CTA_RESOURCE_ALLOCATION 0x02b4 +#define NV85C0_SET_CTA_RESOURCE_ALLOCATION_THREAD_COUNT 15:0 +#define NV85C0_SET_CTA_RESOURCE_ALLOCATION_BARRIER_COUNT 23:16 + +#define NV85C0_SET_CTA_THREAD_CONTROL 0x02b8 +#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH 0:0 +#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_FALSE 0x00000000 +#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_TRUE 0x00000001 + +#define NV85C0_SET_PHASE_ID_CONTROL 0x02bc +#define NV85C0_SET_PHASE_ID_CONTROL_WINDOW_SIZE 2:0 +#define NV85C0_SET_PHASE_ID_CONTROL_LOCK_PHASE 6:4 + +#define NV85C0_SET_CTA_REGISTER_COUNT 0x02c0 +#define NV85C0_SET_CTA_REGISTER_COUNT_V 7:0 + +#define NV85C0_SET_TEX_HEADER_POOL_A 0x02c4 +#define NV85C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_TEX_HEADER_POOL_B 0x02c8 +#define NV85C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_TEX_HEADER_POOL_C 0x02cc +#define NV85C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x02d0+(i)*4) +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL(i) (0x02e0+(i)*4) +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EDGE 0:0 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK 6:4 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_ACE 0x00000000 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DIS 0x00000001 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DSM 0x00000002 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_PIC 0x00000003 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_STP 0x00000004 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_XIU 0x00000005 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_FUNC 23:8 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EVENT 31:24 + +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x02f0 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 3:0 + +#define NV85C0_RESET_CTA_TRACKING_RAM 0x02f4 +#define NV85C0_RESET_CTA_TRACKING_RAM_V 31:0 + +#define NV85C0_INITIALIZE 0x02f8 +#define NV85C0_INITIALIZE_INIT_CTA_SHAPE 0:0 +#define NV85C0_INITIALIZE_INIT_CTA_SHAPE_FALSE 0x00000000 +#define NV85C0_INITIALIZE_INIT_CTA_SHAPE_TRUE 0x00000001 + +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE 0x02fc +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM 2:0 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__24 0x00000005 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 + +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL 0x0300 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V 2:0 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 + +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE 0x0304 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM 2:0 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__24 0x00000005 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 + +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL 0x0308 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V 2:0 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 + +#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS 0x030c +#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA 0:0 +#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_FALSE 0x00000000 +#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_TRUE 0x00000001 + +#define NV85C0_SET_REPORT_SEMAPHORE_A 0x0310 +#define NV85C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_REPORT_SEMAPHORE_B 0x0314 +#define NV85C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_REPORT_SEMAPHORE_C 0x0318 +#define NV85C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV85C0_SET_REPORT_SEMAPHORE_D 0x031c +#define NV85C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV85C0_SET_REPORT_SEMAPHORE_D_OPERATION_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_RELEASE 2:2 +#define NV85C0_SET_REPORT_SEMAPHORE_D_RELEASE_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_ACQUIRE 3:3 +#define NV85C0_SET_REPORT_SEMAPHORE_D_ACQUIRE_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 7:4 +#define NV85C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_COMPARISON 8:8 +#define NV85C0_SET_REPORT_SEMAPHORE_D_COMPARISON_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 9:9 +#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV85C0_SET_REPORT_SEMAPHORE_D_REPORT 14:10 +#define NV85C0_SET_REPORT_SEMAPHORE_D_REPORT_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 15:15 +#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 + +#define NV85C0_SET_LAUNCH_ENABLE_A 0x0320 +#define NV85C0_SET_LAUNCH_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_LAUNCH_ENABLE_B 0x0324 +#define NV85C0_SET_LAUNCH_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_LAUNCH_ENABLE_C 0x0328 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE 2:0 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_FALSE 0x00000000 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_TRUE 0x00000001 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE 0x032c +#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE 31:0 +#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NV85C0_PIPE_NOP 0x0330 +#define NV85C0_PIPE_NOP_V 31:0 + +#define NV85C0_SET_SPARE_NOOP13 0x0334 +#define NV85C0_SET_SPARE_NOOP13_V 31:0 + +#define NV85C0_SET_SPARE_NOOP09 0x0338 +#define NV85C0_SET_SPARE_NOOP09_V 31:0 + +#define NV85C0_SET_SPARE_NOOP14 0x033c +#define NV85C0_SET_SPARE_NOOP14_V 31:0 + +#define NV85C0_SET_SPARE_NOOP00 0x0340 +#define NV85C0_SET_SPARE_NOOP00_V 31:0 + +#define NV85C0_SET_SPARE_NOOP01 0x0344 +#define NV85C0_SET_SPARE_NOOP01_V 31:0 + +#define NV85C0_SET_SPARE00 0x0348 +#define NV85C0_SET_SPARE00_V 31:0 + +#define NV85C0_SET_SPARE01 0x034c +#define NV85C0_SET_SPARE01_V 31:0 + +#define NV85C0_SET_SPARE_NOOP05 0x0350 +#define NV85C0_SET_SPARE_NOOP05_V 31:0 + +#define NV85C0_SET_SPARE_NOOP10 0x0354 +#define NV85C0_SET_SPARE_NOOP10_V 31:0 + +#define NV85C0_SET_GLOBAL_COLOR_KEY 0x0358 +#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE 31:0 +#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV85C0_RESET_REF_COUNT 0x035c +#define NV85C0_RESET_REF_COUNT_REF_CNT 3:0 + +#define NV85C0_WAIT_REF_COUNT 0x0360 +#define NV85C0_WAIT_REF_COUNT_COMPARE 7:4 +#define NV85C0_WAIT_REF_COUNT_COMPARE_COUNT_QUIESENT 0x00000000 +#define NV85C0_WAIT_REF_COUNT_COMPARE_VALUE_EQUAL 0x00000001 +#define NV85C0_WAIT_REF_COUNT_COMPARE_VALUE_CLOCKHAND 0x00000002 +#define NV85C0_WAIT_REF_COUNT_REF_CNT 11:8 + +#define NV85C0_SET_REF_COUNT_VALUE 0x0364 +#define NV85C0_SET_REF_COUNT_VALUE_V 31:0 + +#define NV85C0_LAUNCH 0x0368 +#define NV85C0_LAUNCH_V 31:0 + +#define NV85C0_SET_LAUNCH_ID 0x036c +#define NV85C0_SET_LAUNCH_ID_REF_CNT 3:0 + +#define NV85C0_SET_LAUNCH_CONTROL 0x0370 +#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH 7:0 +#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH_MANUAL_LAUNCH 0x00000000 +#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH_AUTO_LAUNCH 0x00000001 + +#define NV85C0_SET_PARAMETER_SIZE 0x0374 +#define NV85C0_SET_PARAMETER_SIZE_AUTO_LAUNCH_INDEX 7:0 +#define NV85C0_SET_PARAMETER_SIZE_COUNT 15:8 + +#define NV85C0_SET_SAMPLER_BINDING 0x0378 +#define NV85C0_SET_SAMPLER_BINDING_V 0:0 +#define NV85C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV85C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV85C0_SET_SHADER_CONTROL 0x037c +#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV85C0_INVALIDATE_SHADER_CACHE 0x0380 +#define NV85C0_INVALIDATE_SHADER_CACHE_V 1:0 +#define NV85C0_INVALIDATE_SHADER_CACHE_V_ALL 0x00000000 +#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1 0x00000001 +#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1_DATA 0x00000002 +#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1_INSTRUCTION 0x00000003 + +#define NV85C0_SET_RASTER_CONTROL 0x0384 +#define NV85C0_SET_RASTER_CONTROL_PROGRAM 7:0 +#define NV85C0_SET_RASTER_CONTROL_PROGRAM_DISABLE 0x00000000 +#define NV85C0_SET_RASTER_CONTROL_FIXED 15:8 +#define NV85C0_SET_RASTER_CONTROL_FIXED_DISABLE 0x00000000 +#define NV85C0_SET_RASTER_CONTROL_FIXED_SIMPLE 0x00000001 +#define NV85C0_SET_RASTER_CONTROL_FIXED_DXVA_RUN_CODED 0x00000002 +#define NV85C0_SET_RASTER_CONTROL_DECRYPTION 23:16 +#define NV85C0_SET_RASTER_CONTROL_DECRYPTION_DISABLE 0x00000000 +#define NV85C0_SET_RASTER_CONTROL_DECRYPTION_ENABLE 0x00000001 + +#define NV85C0_SET_CTA_FLAGS 0x0388 +#define NV85C0_SET_CTA_FLAGS_V 15:0 + +#define NV85C0_SET_SPARE_NOOP06 0x038c +#define NV85C0_SET_SPARE_NOOP06_V 31:0 + +#define NV85C0_SET_SPARE_NOOP15 0x0390 +#define NV85C0_SET_SPARE_NOOP15_V 31:0 + +#define NV85C0_SET_SPARE_NOOP11 0x0394 +#define NV85C0_SET_SPARE_NOOP11_V 31:0 + +#define NV85C0_SET_SPARE02 0x0398 +#define NV85C0_SET_SPARE02_V 31:0 + +#define NV85C0_SET_SPARE_NOOP02 0x039c +#define NV85C0_SET_SPARE_NOOP02_V 31:0 + +#define NV85C0_SET_SPARE03 0x03a0 +#define NV85C0_SET_SPARE03_V 31:0 + +#define NV85C0_SET_CTA_RASTER_SIZE 0x03a4 +#define NV85C0_SET_CTA_RASTER_SIZE_WIDTH 15:0 +#define NV85C0_SET_CTA_RASTER_SIZE_HEIGHT 31:16 + +#define NV85C0_SET_CTA_GRF_SIZE 0x03a8 +#define NV85C0_SET_CTA_GRF_SIZE_V 31:0 + +#define NV85C0_SET_CTA_THREAD_DIMENSION_A 0x03ac +#define NV85C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 +#define NV85C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 + +#define NV85C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 +#define NV85C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 + +#define NV85C0_SET_CTA_PROGRAM_START 0x03b4 +#define NV85C0_SET_CTA_PROGRAM_START_OFFSET 23:0 + +#define NV85C0_SET_CTA_REGISTER_ALLOCATION 0x03b8 +#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V 31:0 +#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V_THICK 0x00000001 +#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V_THIN 0x00000002 + +#define NV85C0_SET_CTA_TEXTURE 0x03bc +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER 0x03c0 +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID 0:0 +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV85C0_BIND_CTA_TEXTURE_HEADER 0x03c4 +#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID 0:0 +#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV85C0_BIND_CTA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV85C0_BIND_CTA_TEXTURE_HEADER_INDEX 30:9 + +#define NV85C0_BIND_CONSTANT_BUFFER 0x03c8 +#define NV85C0_BIND_CONSTANT_BUFFER_VALID 3:0 +#define NV85C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV85C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_TYPE 7:4 +#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_TYPE_CTA 0x00000000 +#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 11:8 +#define NV85C0_BIND_CONSTANT_BUFFER_TABLE_ENTRY 19:12 + +#define NV85C0_PREFETCH_TEXTURE_SAMPLER 0x03cc +#define NV85C0_PREFETCH_TEXTURE_SAMPLER_INDEX 21:0 + +#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE 0x03d0 +#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 5:4 +#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 +#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L2_ONLY 0x00000001 +#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_AND_L2 0x00000002 + +#define NV85C0_SET_SPARE_NOOP03 0x03d4 +#define NV85C0_SET_SPARE_NOOP03_V 31:0 + +#define NV85C0_SET_SPARE_NOOP07 0x03d8 +#define NV85C0_SET_SPARE_NOOP07_V 31:0 + +#define NV85C0_SET_SPARE_NOOP04 0x03dc +#define NV85C0_SET_SPARE_NOOP04_V 31:0 + +#define NV85C0_SET_SPARE_NOOP08 0x03e0 +#define NV85C0_SET_SPARE_NOOP08_V 31:0 + +#define NV85C0_SET_SPARE_NOOP12 0x03e4 +#define NV85C0_SET_SPARE_NOOP12_V 31:0 + +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING 0x03e8 +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 1:0 +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 + +#define NV85C0_SET_SHADER_EXCEPTIONS 0x03ec +#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV85C0_SET_GLOBAL_MEM_A(j) (0x0400+(j)*32) +#define NV85C0_SET_GLOBAL_MEM_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_GLOBAL_MEM_B(j) (0x0404+(j)*32) +#define NV85C0_SET_GLOBAL_MEM_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_GLOBAL_MEM_SIZE(j) (0x0408+(j)*32) +#define NV85C0_SET_GLOBAL_MEM_SIZE_BLOCK_PITCH 31:0 + +#define NV85C0_SET_GLOBAL_MEM_LIMIT(j) (0x040c+(j)*32) +#define NV85C0_SET_GLOBAL_MEM_LIMIT_MAX 31:0 + +#define NV85C0_SET_GLOBAL_MEM_FORMAT(j) (0x0410+(j)*32) +#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT 0:0 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_PITCH 0x00000001 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH 7:4 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH_ONE_GOB 0x00000000 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT 11:8 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_ONE_GOB 0x00000000 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_TWO_GOBS 0x00000001 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_FOUR_GOBS 0x00000002 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV85C0_PARAMETER(i) (0x0600+(i)*4) +#define NV85C0_PARAMETER_V 31:0 + +#endif /* _cl_gt214_compute_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl902d.h b/src/nouveau/nvidia-headers/classes/cl902d.h new file mode 100644 index 0000000..b675ee3 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl902d.h @@ -0,0 +1,1091 @@ +/* + * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_twod_a_h_ +#define _cl_fermi_twod_a_h_ + +#define FERMI_TWOD_A 0x902D + +typedef volatile struct fermi_twod_a_struct { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 LoadMmeInstructionRamPointer; + NvU32 LoadMmeInstructionRam; + NvU32 LoadMmeStartAddressRamPointer; + NvU32 LoadMmeStartAddressRam; + NvU32 SetMmeShadowRamControl; + NvU32 Reserved_0x128[0x2]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 Reserved_0x144[0x3]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0x25]; + NvU32 SetMmeSwitchState; + NvU32 Reserved_0x1F0[0x4]; + NvU32 SetDstFormat; + NvU32 SetDstMemoryLayout; + NvU32 SetDstBlockSize; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstPitch; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstOffsetUpper; + NvU32 SetDstOffsetLower; + NvU32 FlushAndInvalidateRopMiniCache; + NvU32 SetSpareNoop06; + NvU32 SetSrcFormat; + NvU32 SetSrcMemoryLayout; + NvU32 SetSrcBlockSize; + NvU32 SetSrcDepth; + NvU32 TwodInvalidateTextureDataCache; + NvU32 SetSrcPitch; + NvU32 SetSrcWidth; + NvU32 SetSrcHeight; + NvU32 SetSrcOffsetUpper; + NvU32 SetSrcOffsetLower; + NvU32 SetPixelsFromMemorySectorPromotion; + NvU32 SetSpareNoop12; + NvU32 SetNumProcessingClusters; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop11; + NvU32 SetSpareNoop07; + NvU32 SetClipX0; + NvU32 SetClipY0; + NvU32 SetClipWidth; + NvU32 SetClipHeight; + NvU32 SetClipEnable; + NvU32 SetColorKeyFormat; + NvU32 SetColorKey; + NvU32 SetColorKeyEnable; + NvU32 SetRop; + NvU32 SetBeta1; + NvU32 SetBeta4; + NvU32 SetOperation; + NvU32 SetPatternOffset; + NvU32 SetPatternSelect; + NvU32 SetDstColorRenderToZetaSurface; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop15; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop02; + NvU32 SetCompression; + NvU32 SetSpareNoop09; + NvU32 SetRenderEnableOverride; + NvU32 SetPixelsFromMemoryDirection; + NvU32 SetSpareNoop10; + NvU32 SetMonochromePatternColorFormat; + NvU32 SetMonochromePatternFormat; + NvU32 SetMonochromePatternColor0; + NvU32 SetMonochromePatternColor1; + NvU32 SetMonochromePattern0; + NvU32 SetMonochromePattern1; + NvU32 ColorPatternX8R8G8B8[0x40]; + NvU32 ColorPatternR5G6B5[0x20]; + NvU32 ColorPatternX1R5G5B5[0x20]; + NvU32 ColorPatternY8[0x10]; + NvU32 SetRenderSolidPrimColor0; + NvU32 SetRenderSolidPrimColor1; + NvU32 SetRenderSolidPrimColor2; + NvU32 SetRenderSolidPrimColor3; + NvU32 SetMmeMemAddressA; + NvU32 SetMmeMemAddressB; + NvU32 SetMmeDataRamAddress; + NvU32 MmeDmaRead; + NvU32 MmeDmaReadFifoed; + NvU32 MmeDmaWrite; + NvU32 MmeDmaReduction; + NvU32 MmeDmaSysmembar; + NvU32 MmeDmaSync; + NvU32 SetMmeDataFifoConfig; + NvU32 Reserved_0x578[0x2]; + NvU32 RenderSolidPrimMode; + NvU32 SetRenderSolidPrimColorFormat; + NvU32 SetRenderSolidPrimColor; + NvU32 SetRenderSolidLineTieBreakBits; + NvU32 Reserved_0x590[0x14]; + NvU32 RenderSolidPrimPointXY; + NvU32 Reserved_0x5E4[0x7]; + struct { + NvU32 SetX; + NvU32 Y; + } RenderSolidPrimPoint[0x40]; + NvU32 SetPixelsFromCpuDataType; + NvU32 SetPixelsFromCpuColorFormat; + NvU32 SetPixelsFromCpuIndexFormat; + NvU32 SetPixelsFromCpuMonoFormat; + NvU32 SetPixelsFromCpuWrap; + NvU32 SetPixelsFromCpuColor0; + NvU32 SetPixelsFromCpuColor1; + NvU32 SetPixelsFromCpuMonoOpacity; + NvU32 Reserved_0x820[0x6]; + NvU32 SetPixelsFromCpuSrcWidth; + NvU32 SetPixelsFromCpuSrcHeight; + NvU32 SetPixelsFromCpuDxDuFrac; + NvU32 SetPixelsFromCpuDxDuInt; + NvU32 SetPixelsFromCpuDyDvFrac; + NvU32 SetPixelsFromCpuDyDvInt; + NvU32 SetPixelsFromCpuDstX0Frac; + NvU32 SetPixelsFromCpuDstX0Int; + NvU32 SetPixelsFromCpuDstY0Frac; + NvU32 SetPixelsFromCpuDstY0Int; + NvU32 PixelsFromCpuData; + NvU32 Reserved_0x864[0x3]; + NvU32 SetBigEndianControl; + NvU32 Reserved_0x874[0x3]; + NvU32 SetPixelsFromMemoryBlockShape; + NvU32 SetPixelsFromMemoryCorralSize; + NvU32 SetPixelsFromMemorySafeOverlap; + NvU32 SetPixelsFromMemorySampleMode; + NvU32 Reserved_0x890[0x8]; + NvU32 SetPixelsFromMemoryDstX0; + NvU32 SetPixelsFromMemoryDstY0; + NvU32 SetPixelsFromMemoryDstWidth; + NvU32 SetPixelsFromMemoryDstHeight; + NvU32 SetPixelsFromMemoryDuDxFrac; + NvU32 SetPixelsFromMemoryDuDxInt; + NvU32 SetPixelsFromMemoryDvDyFrac; + NvU32 SetPixelsFromMemoryDvDyInt; + NvU32 SetPixelsFromMemorySrcX0Frac; + NvU32 SetPixelsFromMemorySrcX0Int; + NvU32 SetPixelsFromMemorySrcY0Frac; + NvU32 PixelsFromMemorySrcY0Int; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x960[0x123]; + NvU32 MmeDmaWriteMethodBarrier; + NvU32 Reserved_0xDF0[0x984]; + NvU32 SetMmeShadowScratch[0x100]; + struct { + NvU32 Macro; + NvU32 Data; + } CallMme[0xE0]; +} fermi_twod_a_t; + + +#define NV902D_SET_OBJECT 0x0000 +#define NV902D_SET_OBJECT_CLASS_ID 15:0 +#define NV902D_SET_OBJECT_ENGINE_ID 20:16 + +#define NV902D_NO_OPERATION 0x0100 +#define NV902D_NO_OPERATION_V 31:0 + +#define NV902D_SET_NOTIFY_A 0x0104 +#define NV902D_SET_NOTIFY_A_ADDRESS_UPPER 24:0 + +#define NV902D_SET_NOTIFY_B 0x0108 +#define NV902D_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV902D_NOTIFY 0x010c +#define NV902D_NOTIFY_TYPE 31:0 +#define NV902D_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV902D_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV902D_WAIT_FOR_IDLE 0x0110 +#define NV902D_WAIT_FOR_IDLE_V 31:0 + +#define NV902D_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV902D_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV902D_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV902D_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV902D_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV902D_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV902D_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV902D_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV902D_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV902D_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV902D_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV902D_SEND_GO_IDLE 0x013c +#define NV902D_SEND_GO_IDLE_V 31:0 + +#define NV902D_PM_TRIGGER 0x0140 +#define NV902D_PM_TRIGGER_V 31:0 + +#define NV902D_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV902D_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV902D_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV902D_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV902D_SET_MME_SWITCH_STATE 0x01ec +#define NV902D_SET_MME_SWITCH_STATE_VALID 0:0 +#define NV902D_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NV902D_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NV902D_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NV902D_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NV902D_SET_DST_FORMAT 0x0200 +#define NV902D_SET_DST_FORMAT_V 7:0 +#define NV902D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV902D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV902D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV902D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV902D_SET_DST_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_DST_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_DST_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_DST_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE +#define NV902D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C +#define NV902D_SET_DST_FORMAT_V_RF16 0x000000F2 +#define NV902D_SET_DST_FORMAT_V_RF32 0x000000E5 +#define NV902D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV902D_SET_DST_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV902D_SET_DST_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV902D_SET_DST_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV902D_SET_DST_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV902D_SET_DST_FORMAT_V_RF16_GF16 0x000000DE +#define NV902D_SET_DST_FORMAT_V_R16_G16 0x000000DA +#define NV902D_SET_DST_FORMAT_V_RN16_GN16 0x000000DB +#define NV902D_SET_DST_FORMAT_V_G8R8 0x000000EA +#define NV902D_SET_DST_FORMAT_V_GN8RN8 0x000000EB +#define NV902D_SET_DST_FORMAT_V_RN16 0x000000EF +#define NV902D_SET_DST_FORMAT_V_RN8 0x000000F4 +#define NV902D_SET_DST_FORMAT_V_A8 0x000000F7 + +#define NV902D_SET_DST_MEMORY_LAYOUT 0x0204 +#define NV902D_SET_DST_MEMORY_LAYOUT_V 0:0 +#define NV902D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV902D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV902D_SET_DST_BLOCK_SIZE 0x0208 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT 6:4 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH 10:8 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV902D_SET_DST_DEPTH 0x020c +#define NV902D_SET_DST_DEPTH_V 31:0 + +#define NV902D_SET_DST_LAYER 0x0210 +#define NV902D_SET_DST_LAYER_V 31:0 + +#define NV902D_SET_DST_PITCH 0x0214 +#define NV902D_SET_DST_PITCH_V 31:0 + +#define NV902D_SET_DST_WIDTH 0x0218 +#define NV902D_SET_DST_WIDTH_V 31:0 + +#define NV902D_SET_DST_HEIGHT 0x021c +#define NV902D_SET_DST_HEIGHT_V 31:0 + +#define NV902D_SET_DST_OFFSET_UPPER 0x0220 +#define NV902D_SET_DST_OFFSET_UPPER_V 7:0 + +#define NV902D_SET_DST_OFFSET_LOWER 0x0224 +#define NV902D_SET_DST_OFFSET_LOWER_V 31:0 + +#define NV902D_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x0228 +#define NV902D_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NV902D_SET_SPARE_NOOP06 0x022c +#define NV902D_SET_SPARE_NOOP06_V 31:0 + +#define NV902D_SET_SRC_FORMAT 0x0230 +#define NV902D_SET_SRC_FORMAT_V 7:0 +#define NV902D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV902D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV902D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV902D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV902D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_SRC_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_SRC_FORMAT_V_AY8 0x0000001D +#define NV902D_SET_SRC_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_SRC_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE +#define NV902D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C +#define NV902D_SET_SRC_FORMAT_V_RF16 0x000000F2 +#define NV902D_SET_SRC_FORMAT_V_RF32 0x000000E5 +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV902D_SET_SRC_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV902D_SET_SRC_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV902D_SET_SRC_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV902D_SET_SRC_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16 0x000000DE +#define NV902D_SET_SRC_FORMAT_V_R16_G16 0x000000DA +#define NV902D_SET_SRC_FORMAT_V_RN16_GN16 0x000000DB +#define NV902D_SET_SRC_FORMAT_V_G8R8 0x000000EA +#define NV902D_SET_SRC_FORMAT_V_GN8RN8 0x000000EB +#define NV902D_SET_SRC_FORMAT_V_RN16 0x000000EF +#define NV902D_SET_SRC_FORMAT_V_RN8 0x000000F4 +#define NV902D_SET_SRC_FORMAT_V_A8 0x000000F7 + +#define NV902D_SET_SRC_MEMORY_LAYOUT 0x0234 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V 0:0 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV902D_SET_SRC_BLOCK_SIZE 0x0238 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT 6:4 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH 10:8 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV902D_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV902D_SET_SRC_DEPTH 0x023c +#define NV902D_SET_SRC_DEPTH_V 31:0 + +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE 0x0240 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V 1:0 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L1_ONLY 0x00000000 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L2_ONLY 0x00000001 +#define NV902D_TWOD_INVALIDATE_TEXTURE_DATA_CACHE_V_L1_AND_L2 0x00000002 + +#define NV902D_SET_SRC_PITCH 0x0244 +#define NV902D_SET_SRC_PITCH_V 31:0 + +#define NV902D_SET_SRC_WIDTH 0x0248 +#define NV902D_SET_SRC_WIDTH_V 31:0 + +#define NV902D_SET_SRC_HEIGHT 0x024c +#define NV902D_SET_SRC_HEIGHT_V 31:0 + +#define NV902D_SET_SRC_OFFSET_UPPER 0x0250 +#define NV902D_SET_SRC_OFFSET_UPPER_V 7:0 + +#define NV902D_SET_SRC_OFFSET_LOWER 0x0254 +#define NV902D_SET_SRC_OFFSET_LOWER_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION 0x0258 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V 1:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_NO_PROMOTION 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_2_V 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_2_H 0x00000002 +#define NV902D_SET_PIXELS_FROM_MEMORY_SECTOR_PROMOTION_V_PROMOTE_TO_4 0x00000003 + +#define NV902D_SET_SPARE_NOOP12 0x025c +#define NV902D_SET_SPARE_NOOP12_V 31:0 + +#define NV902D_SET_NUM_PROCESSING_CLUSTERS 0x0260 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V 0:0 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V_ALL 0x00000000 +#define NV902D_SET_NUM_PROCESSING_CLUSTERS_V_ONE 0x00000001 + +#define NV902D_SET_RENDER_ENABLE_A 0x0264 +#define NV902D_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV902D_SET_RENDER_ENABLE_B 0x0268 +#define NV902D_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV902D_SET_RENDER_ENABLE_C 0x026c +#define NV902D_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV902D_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV902D_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV902D_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV902D_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV902D_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV902D_SET_SPARE_NOOP08 0x0270 +#define NV902D_SET_SPARE_NOOP08_V 31:0 + +#define NV902D_SET_SPARE_NOOP01 0x0274 +#define NV902D_SET_SPARE_NOOP01_V 31:0 + +#define NV902D_SET_SPARE_NOOP11 0x0278 +#define NV902D_SET_SPARE_NOOP11_V 31:0 + +#define NV902D_SET_SPARE_NOOP07 0x027c +#define NV902D_SET_SPARE_NOOP07_V 31:0 + +#define NV902D_SET_CLIP_X0 0x0280 +#define NV902D_SET_CLIP_X0_V 31:0 + +#define NV902D_SET_CLIP_Y0 0x0284 +#define NV902D_SET_CLIP_Y0_V 31:0 + +#define NV902D_SET_CLIP_WIDTH 0x0288 +#define NV902D_SET_CLIP_WIDTH_V 31:0 + +#define NV902D_SET_CLIP_HEIGHT 0x028c +#define NV902D_SET_CLIP_HEIGHT_V 31:0 + +#define NV902D_SET_CLIP_ENABLE 0x0290 +#define NV902D_SET_CLIP_ENABLE_V 0:0 +#define NV902D_SET_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV902D_SET_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV902D_SET_COLOR_KEY_FORMAT 0x0294 +#define NV902D_SET_COLOR_KEY_FORMAT_V 2:0 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A16R5G6B5 0x00000000 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A1R5G5B5 0x00000001 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A8R8G8B8 0x00000002 +#define NV902D_SET_COLOR_KEY_FORMAT_V_A2R10G10B10 0x00000003 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y8 0x00000004 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y16 0x00000005 +#define NV902D_SET_COLOR_KEY_FORMAT_V_Y32 0x00000006 + +#define NV902D_SET_COLOR_KEY 0x0298 +#define NV902D_SET_COLOR_KEY_V 31:0 + +#define NV902D_SET_COLOR_KEY_ENABLE 0x029c +#define NV902D_SET_COLOR_KEY_ENABLE_V 0:0 +#define NV902D_SET_COLOR_KEY_ENABLE_V_FALSE 0x00000000 +#define NV902D_SET_COLOR_KEY_ENABLE_V_TRUE 0x00000001 + +#define NV902D_SET_ROP 0x02a0 +#define NV902D_SET_ROP_V 7:0 + +#define NV902D_SET_BETA1 0x02a4 +#define NV902D_SET_BETA1_V 31:0 + +#define NV902D_SET_BETA4 0x02a8 +#define NV902D_SET_BETA4_B 7:0 +#define NV902D_SET_BETA4_G 15:8 +#define NV902D_SET_BETA4_R 23:16 +#define NV902D_SET_BETA4_A 31:24 + +#define NV902D_SET_OPERATION 0x02ac +#define NV902D_SET_OPERATION_V 2:0 +#define NV902D_SET_OPERATION_V_SRCCOPY_AND 0x00000000 +#define NV902D_SET_OPERATION_V_ROP_AND 0x00000001 +#define NV902D_SET_OPERATION_V_BLEND_AND 0x00000002 +#define NV902D_SET_OPERATION_V_SRCCOPY 0x00000003 +#define NV902D_SET_OPERATION_V_ROP 0x00000004 +#define NV902D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005 +#define NV902D_SET_OPERATION_V_BLEND_PREMULT 0x00000006 + +#define NV902D_SET_PATTERN_OFFSET 0x02b0 +#define NV902D_SET_PATTERN_OFFSET_X 5:0 +#define NV902D_SET_PATTERN_OFFSET_Y 13:8 + +#define NV902D_SET_PATTERN_SELECT 0x02b4 +#define NV902D_SET_PATTERN_SELECT_V 1:0 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_8x8 0x00000000 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_64x1 0x00000001 +#define NV902D_SET_PATTERN_SELECT_V_MONOCHROME_1x64 0x00000002 +#define NV902D_SET_PATTERN_SELECT_V_COLOR 0x00000003 + +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NV902D_SET_DST_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NV902D_SET_SPARE_NOOP04 0x02bc +#define NV902D_SET_SPARE_NOOP04_V 31:0 + +#define NV902D_SET_SPARE_NOOP15 0x02c0 +#define NV902D_SET_SPARE_NOOP15_V 31:0 + +#define NV902D_SET_SPARE_NOOP13 0x02c4 +#define NV902D_SET_SPARE_NOOP13_V 31:0 + +#define NV902D_SET_SPARE_NOOP03 0x02c8 +#define NV902D_SET_SPARE_NOOP03_V 31:0 + +#define NV902D_SET_SPARE_NOOP14 0x02cc +#define NV902D_SET_SPARE_NOOP14_V 31:0 + +#define NV902D_SET_SPARE_NOOP02 0x02d0 +#define NV902D_SET_SPARE_NOOP02_V 31:0 + +#define NV902D_SET_COMPRESSION 0x02d4 +#define NV902D_SET_COMPRESSION_ENABLE 0:0 +#define NV902D_SET_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV902D_SET_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV902D_SET_SPARE_NOOP09 0x02d8 +#define NV902D_SET_SPARE_NOOP09_V 31:0 + +#define NV902D_SET_RENDER_ENABLE_OVERRIDE 0x02dc +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV902D_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION 0x02e0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL 1:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_HW_DECIDES 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_LEFT_TO_RIGHT 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_HORIZONTAL_RIGHT_TO_LEFT 0x00000002 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL 5:4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_HW_DECIDES 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_TOP_TO_BOTTOM 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_DIRECTION_VERTICAL_BOTTOM_TO_TOP 0x00000002 + +#define NV902D_SET_SPARE_NOOP10 0x02e4 +#define NV902D_SET_SPARE_NOOP10_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_BYTE_EXPAND 0x00000006 + +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0 +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000 +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR0 0x02f0 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR0_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR1 0x02f4 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR1_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN0 0x02f8 +#define NV902D_SET_MONOCHROME_PATTERN0_V 31:0 + +#define NV902D_SET_MONOCHROME_PATTERN1 0x02fc +#define NV902D_SET_MONOCHROME_PATTERN1_V 31:0 + +#define NV902D_COLOR_PATTERN_X8R8G8B8(i) (0x0300+(i)*4) +#define NV902D_COLOR_PATTERN_X8R8G8B8_B0 7:0 +#define NV902D_COLOR_PATTERN_X8R8G8B8_G0 15:8 +#define NV902D_COLOR_PATTERN_X8R8G8B8_R0 23:16 +#define NV902D_COLOR_PATTERN_X8R8G8B8_IGNORE0 31:24 + +#define NV902D_COLOR_PATTERN_R5G6B5(i) (0x0400+(i)*4) +#define NV902D_COLOR_PATTERN_R5G6B5_B0 4:0 +#define NV902D_COLOR_PATTERN_R5G6B5_G0 10:5 +#define NV902D_COLOR_PATTERN_R5G6B5_R0 15:11 +#define NV902D_COLOR_PATTERN_R5G6B5_B1 20:16 +#define NV902D_COLOR_PATTERN_R5G6B5_G1 26:21 +#define NV902D_COLOR_PATTERN_R5G6B5_R1 31:27 + +#define NV902D_COLOR_PATTERN_X1R5G5B5(i) (0x0480+(i)*4) +#define NV902D_COLOR_PATTERN_X1R5G5B5_B0 4:0 +#define NV902D_COLOR_PATTERN_X1R5G5B5_G0 9:5 +#define NV902D_COLOR_PATTERN_X1R5G5B5_R0 14:10 +#define NV902D_COLOR_PATTERN_X1R5G5B5_IGNORE0 15:15 +#define NV902D_COLOR_PATTERN_X1R5G5B5_B1 20:16 +#define NV902D_COLOR_PATTERN_X1R5G5B5_G1 25:21 +#define NV902D_COLOR_PATTERN_X1R5G5B5_R1 30:26 +#define NV902D_COLOR_PATTERN_X1R5G5B5_IGNORE1 31:31 + +#define NV902D_COLOR_PATTERN_Y8(i) (0x0500+(i)*4) +#define NV902D_COLOR_PATTERN_Y8_Y0 7:0 +#define NV902D_COLOR_PATTERN_Y8_Y1 15:8 +#define NV902D_COLOR_PATTERN_Y8_Y2 23:16 +#define NV902D_COLOR_PATTERN_Y8_Y3 31:24 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR0 0x0540 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR0_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR1 0x0544 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR1_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR2 0x0548 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR2_V 31:0 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR3 0x054c +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR3_V 31:0 + +#define NV902D_SET_MME_MEM_ADDRESS_A 0x0550 +#define NV902D_SET_MME_MEM_ADDRESS_A_UPPER 24:0 + +#define NV902D_SET_MME_MEM_ADDRESS_B 0x0554 +#define NV902D_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NV902D_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NV902D_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NV902D_MME_DMA_READ 0x055c +#define NV902D_MME_DMA_READ_LENGTH 31:0 + +#define NV902D_MME_DMA_READ_FIFOED 0x0560 +#define NV902D_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NV902D_MME_DMA_WRITE 0x0564 +#define NV902D_MME_DMA_WRITE_LENGTH 31:0 + +#define NV902D_MME_DMA_REDUCTION 0x0568 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NV902D_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NV902D_MME_DMA_SYSMEMBAR 0x056c +#define NV902D_MME_DMA_SYSMEMBAR_V 0:0 + +#define NV902D_MME_DMA_SYNC 0x0570 +#define NV902D_MME_DMA_SYNC_VALUE 31:0 + +#define NV902D_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NV902D_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NV902D_RENDER_SOLID_PRIM_MODE 0x0580 +#define NV902D_RENDER_SOLID_PRIM_MODE_V 2:0 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR 0x0588 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0 + +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS 0x058c +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_XMAJ__XINC__YINC 0:0 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_XMAJ__XDEC__YINC 4:4 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_YMAJ__XINC__YINC 8:8 +#define NV902D_SET_RENDER_SOLID_LINE_TIE_BREAK_BITS_YMAJ__XDEC__YINC 12:12 + +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y 0x05e0 +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y_X 15:0 +#define NV902D_RENDER_SOLID_PRIM_POINT_X_Y_Y 31:16 + +#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8) +#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0 + +#define NV902D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8) +#define NV902D_RENDER_SOLID_PRIM_POINT_Y_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002 + +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_WRAP 0x0810 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V 1:0 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR0 0x0814 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR1 0x0818 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838 +#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c +#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840 +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844 +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848 +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850 +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854 +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858 +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0 + +#define NV902D_PIXELS_FROM_CPU_DATA 0x0860 +#define NV902D_PIXELS_FROM_CPU_DATA_V 31:0 + +#define NV902D_SET_BIG_ENDIAN_CONTROL 0x0870 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_1 0:0 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_4 1:1 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_8 2:2 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X32_SWAP_16 3:3 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_1 4:4 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_4 5:5 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_8 6:6 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X16_SWAP_16 7:7 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_1 8:8 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_4 9:9 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_8 10:10 +#define NV902D_SET_BIG_ENDIAN_CONTROL_X8_SWAP_16 11:11 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_1 12:12 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_4 13:13 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_8 14:14 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_CGA6_SWAP_16 15:15 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_1 16:16 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_4 17:17 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_8 18:18 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I1_X8_LE_SWAP_16 19:19 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_1 20:20 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_4 21:21 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_8 22:22 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I4_SWAP_16 23:23 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_1 24:24 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_4 25:25 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_8 26:26 +#define NV902D_SET_BIG_ENDIAN_CONTROL_I8_SWAP_16 27:27 +#define NV902D_SET_BIG_ENDIAN_CONTROL_OVERRIDE 28:28 + +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE 0x0880 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V 2:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_AUTO 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_SHAPE_8X8 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_BLOCK_SHAPE_V_SHAPE_16X4 0x00000002 + +#define NV902D_SET_PIXELS_FROM_MEMORY_CORRAL_SIZE 0x0884 +#define NV902D_SET_PIXELS_FROM_MEMORY_CORRAL_SIZE_V 9:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE 0x088c +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN 0:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN_CENTER 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_ORIGIN_CORNER 0x00000001 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER 4:4 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER_POINT 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAMPLE_MODE_FILTER_BILINEAR 0x00000001 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8 +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0 + +#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc +#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0 + +#define NV902D_SET_FALCON00 0x08e0 +#define NV902D_SET_FALCON00_V 31:0 + +#define NV902D_SET_FALCON01 0x08e4 +#define NV902D_SET_FALCON01_V 31:0 + +#define NV902D_SET_FALCON02 0x08e8 +#define NV902D_SET_FALCON02_V 31:0 + +#define NV902D_SET_FALCON03 0x08ec +#define NV902D_SET_FALCON03_V 31:0 + +#define NV902D_SET_FALCON04 0x08f0 +#define NV902D_SET_FALCON04_V 31:0 + +#define NV902D_SET_FALCON05 0x08f4 +#define NV902D_SET_FALCON05_V 31:0 + +#define NV902D_SET_FALCON06 0x08f8 +#define NV902D_SET_FALCON06_V 31:0 + +#define NV902D_SET_FALCON07 0x08fc +#define NV902D_SET_FALCON07_V 31:0 + +#define NV902D_SET_FALCON08 0x0900 +#define NV902D_SET_FALCON08_V 31:0 + +#define NV902D_SET_FALCON09 0x0904 +#define NV902D_SET_FALCON09_V 31:0 + +#define NV902D_SET_FALCON10 0x0908 +#define NV902D_SET_FALCON10_V 31:0 + +#define NV902D_SET_FALCON11 0x090c +#define NV902D_SET_FALCON11_V 31:0 + +#define NV902D_SET_FALCON12 0x0910 +#define NV902D_SET_FALCON12_V 31:0 + +#define NV902D_SET_FALCON13 0x0914 +#define NV902D_SET_FALCON13_V 31:0 + +#define NV902D_SET_FALCON14 0x0918 +#define NV902D_SET_FALCON14_V 31:0 + +#define NV902D_SET_FALCON15 0x091c +#define NV902D_SET_FALCON15_V 31:0 + +#define NV902D_SET_FALCON16 0x0920 +#define NV902D_SET_FALCON16_V 31:0 + +#define NV902D_SET_FALCON17 0x0924 +#define NV902D_SET_FALCON17_V 31:0 + +#define NV902D_SET_FALCON18 0x0928 +#define NV902D_SET_FALCON18_V 31:0 + +#define NV902D_SET_FALCON19 0x092c +#define NV902D_SET_FALCON19_V 31:0 + +#define NV902D_SET_FALCON20 0x0930 +#define NV902D_SET_FALCON20_V 31:0 + +#define NV902D_SET_FALCON21 0x0934 +#define NV902D_SET_FALCON21_V 31:0 + +#define NV902D_SET_FALCON22 0x0938 +#define NV902D_SET_FALCON22_V 31:0 + +#define NV902D_SET_FALCON23 0x093c +#define NV902D_SET_FALCON23_V 31:0 + +#define NV902D_SET_FALCON24 0x0940 +#define NV902D_SET_FALCON24_V 31:0 + +#define NV902D_SET_FALCON25 0x0944 +#define NV902D_SET_FALCON25_V 31:0 + +#define NV902D_SET_FALCON26 0x0948 +#define NV902D_SET_FALCON26_V 31:0 + +#define NV902D_SET_FALCON27 0x094c +#define NV902D_SET_FALCON27_V 31:0 + +#define NV902D_SET_FALCON28 0x0950 +#define NV902D_SET_FALCON28_V 31:0 + +#define NV902D_SET_FALCON29 0x0954 +#define NV902D_SET_FALCON29_V 31:0 + +#define NV902D_SET_FALCON30 0x0958 +#define NV902D_SET_FALCON30_V 31:0 + +#define NV902D_SET_FALCON31 0x095c +#define NV902D_SET_FALCON31_V 31:0 + +#define NV902D_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NV902D_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NV902D_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV902D_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV902D_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV902D_CALL_MME_MACRO_V 31:0 + +#define NV902D_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV902D_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_twod_a_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl9039.h b/src/nouveau/nvidia-headers/classes/cl9039.h new file mode 100644 index 0000000..282825d --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl9039.h @@ -0,0 +1,401 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_memory_to_memory_format_a_h_ +#define _cl_fermi_memory_to_memory_format_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl fermi_memory_to_memory_format_a */ + +#include "nvtypes.h" + +#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x9039 + +#define NV9039_SET_OBJECT 0x0000 +#define NV9039_SET_OBJECT_CLASS_ID 15:0 +#define NV9039_SET_OBJECT_ENGINE_ID 20:16 + +#define NV9039_NO_OPERATION 0x0100 +#define NV9039_NO_OPERATION_V 31:0 + +#define NV9039_SET_NOTIFY_A 0x0104 +#define NV9039_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NV9039_SET_NOTIFY_B 0x0108 +#define NV9039_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV9039_NOTIFY 0x010c +#define NV9039_NOTIFY_TYPE 31:0 +#define NV9039_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV9039_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV9039_WAIT_FOR_IDLE 0x0110 +#define NV9039_WAIT_FOR_IDLE_V 31:0 + +#define NV9039_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV9039_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV9039_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV9039_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV9039_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV9039_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV9039_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV9039_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV9039_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV9039_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV9039_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV9039_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV9039_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV9039_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV9039_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV9039_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV9039_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV9039_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV9039_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV9039_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV9039_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV9039_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV9039_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV9039_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV9039_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV9039_SEND_GO_IDLE 0x013c +#define NV9039_SEND_GO_IDLE_V 31:0 + +#define NV9039_PM_TRIGGER 0x0140 +#define NV9039_PM_TRIGGER_V 31:0 + +#define NV9039_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV9039_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV9039_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV9039_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV9039_SET_SRC_BLOCK_SIZE 0x0204 +#define NV9039_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NV9039_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9039_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NV9039_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9039_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9039_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9039_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9039_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9039_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9039_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NV9039_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV9039_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV9039_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV9039_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV9039_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV9039_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV9039_SET_SRC_WIDTH 0x0208 +#define NV9039_SET_SRC_WIDTH_V 31:0 + +#define NV9039_SET_SRC_HEIGHT 0x020c +#define NV9039_SET_SRC_HEIGHT_V 31:0 + +#define NV9039_SET_SRC_DEPTH 0x0210 +#define NV9039_SET_SRC_DEPTH_V 31:0 + +#define NV9039_SET_SRC_LAYER 0x0214 +#define NV9039_SET_SRC_LAYER_V 31:0 + +#define NV9039_SET_DST_BLOCK_SIZE 0x0220 +#define NV9039_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NV9039_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9039_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NV9039_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9039_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9039_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9039_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9039_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9039_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9039_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NV9039_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV9039_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV9039_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV9039_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV9039_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV9039_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV9039_SET_DST_WIDTH 0x0224 +#define NV9039_SET_DST_WIDTH_V 31:0 + +#define NV9039_SET_DST_HEIGHT 0x0228 +#define NV9039_SET_DST_HEIGHT_V 31:0 + +#define NV9039_SET_DST_DEPTH 0x022c +#define NV9039_SET_DST_DEPTH_V 31:0 + +#define NV9039_SET_DST_LAYER 0x0230 +#define NV9039_SET_DST_LAYER_V 31:0 + +#define NV9039_OFFSET_OUT_UPPER 0x0238 +#define NV9039_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NV9039_OFFSET_OUT 0x023c +#define NV9039_OFFSET_OUT_VALUE 31:0 + +#define NV9039_SET_SPARE_NOOP06 0x0240 +#define NV9039_SET_SPARE_NOOP06_V 31:0 + +#define NV9039_SET_SPARE_NOOP03 0x0244 +#define NV9039_SET_SPARE_NOOP03_V 31:0 + +#define NV9039_SET_SPARE_NOOP07 0x0248 +#define NV9039_SET_SPARE_NOOP07_V 31:0 + +#define NV9039_SET_SPARE_NOOP05 0x024c +#define NV9039_SET_SPARE_NOOP05_V 31:0 + +#define NV9039_SET_SPARE_NOOP14 0x0250 +#define NV9039_SET_SPARE_NOOP14_V 31:0 + +#define NV9039_SET_SPARE_NOOP04 0x0254 +#define NV9039_SET_SPARE_NOOP04_V 31:0 + +#define NV9039_SET_SPARE_NOOP10 0x0258 +#define NV9039_SET_SPARE_NOOP10_V 31:0 + +#define NV9039_SET_SPARE_NOOP02 0x025c +#define NV9039_SET_SPARE_NOOP02_V 31:0 + +#define NV9039_SET_SPARE_NOOP12 0x0260 +#define NV9039_SET_SPARE_NOOP12_V 31:0 + +#define NV9039_SET_SPARE_NOOP00 0x0264 +#define NV9039_SET_SPARE_NOOP00_V 31:0 + +#define NV9039_SET_SPARE_NOOP08 0x0268 +#define NV9039_SET_SPARE_NOOP08_V 31:0 + +#define NV9039_SET_SPARE_NOOP13 0x026c +#define NV9039_SET_SPARE_NOOP13_V 31:0 + +#define NV9039_SET_SPARE_NOOP09 0x0270 +#define NV9039_SET_SPARE_NOOP09_V 31:0 + +#define NV9039_SET_SPARE_NOOP15 0x0274 +#define NV9039_SET_SPARE_NOOP15_V 31:0 + +#define NV9039_SET_SPARE_NOOP01 0x0278 +#define NV9039_SET_SPARE_NOOP01_V 31:0 + +#define NV9039_SET_FALCON00 0x027c +#define NV9039_SET_FALCON00_V 31:0 + +#define NV9039_SET_FALCON01 0x0280 +#define NV9039_SET_FALCON01_V 31:0 + +#define NV9039_SET_FALCON02 0x0284 +#define NV9039_SET_FALCON02_V 31:0 + +#define NV9039_SET_FALCON03 0x0288 +#define NV9039_SET_FALCON03_V 31:0 + +#define NV9039_SET_FALCON04 0x028c +#define NV9039_SET_FALCON04_V 31:0 + +#define NV9039_SET_FALCON05 0x0290 +#define NV9039_SET_FALCON05_V 31:0 + +#define NV9039_SET_FALCON06 0x0294 +#define NV9039_SET_FALCON06_V 31:0 + +#define NV9039_SET_FALCON07 0x0298 +#define NV9039_SET_FALCON07_V 31:0 + +#define NV9039_SET_FALCON08 0x029c +#define NV9039_SET_FALCON08_V 31:0 + +#define NV9039_SET_FALCON09 0x02a0 +#define NV9039_SET_FALCON09_V 31:0 + +#define NV9039_SET_FALCON10 0x02a4 +#define NV9039_SET_FALCON10_V 31:0 + +#define NV9039_SET_FALCON11 0x02a8 +#define NV9039_SET_FALCON11_V 31:0 + +#define NV9039_SET_FALCON12 0x02ac +#define NV9039_SET_FALCON12_V 31:0 + +#define NV9039_SET_FALCON13 0x02b0 +#define NV9039_SET_FALCON13_V 31:0 + +#define NV9039_SET_FALCON14 0x02b4 +#define NV9039_SET_FALCON14_V 31:0 + +#define NV9039_SET_FALCON15 0x02b8 +#define NV9039_SET_FALCON15_V 31:0 + +#define NV9039_SET_FALCON16 0x02bc +#define NV9039_SET_FALCON16_V 31:0 + +#define NV9039_SET_FALCON17 0x02c0 +#define NV9039_SET_FALCON17_V 31:0 + +#define NV9039_SET_FALCON18 0x02c4 +#define NV9039_SET_FALCON18_V 31:0 + +#define NV9039_SET_FALCON19 0x02c8 +#define NV9039_SET_FALCON19_V 31:0 + +#define NV9039_SET_FALCON20 0x02cc +#define NV9039_SET_FALCON20_V 31:0 + +#define NV9039_SET_FALCON21 0x02d0 +#define NV9039_SET_FALCON21_V 31:0 + +#define NV9039_SET_FALCON22 0x02d4 +#define NV9039_SET_FALCON22_V 31:0 + +#define NV9039_SET_FALCON23 0x02d8 +#define NV9039_SET_FALCON23_V 31:0 + +#define NV9039_SET_FALCON24 0x02dc +#define NV9039_SET_FALCON24_V 31:0 + +#define NV9039_SET_FALCON25 0x02e0 +#define NV9039_SET_FALCON25_V 31:0 + +#define NV9039_SET_FALCON26 0x02e4 +#define NV9039_SET_FALCON26_V 31:0 + +#define NV9039_SET_FALCON27 0x02e8 +#define NV9039_SET_FALCON27_V 31:0 + +#define NV9039_SET_FALCON28 0x02ec +#define NV9039_SET_FALCON28_V 31:0 + +#define NV9039_SET_FALCON29 0x02f0 +#define NV9039_SET_FALCON29_V 31:0 + +#define NV9039_SET_FALCON30 0x02f4 +#define NV9039_SET_FALCON30_V 31:0 + +#define NV9039_SET_FALCON31 0x02f8 +#define NV9039_SET_FALCON31_V 31:0 + +#define NV9039_SET_SPARE_NOOP11 0x02fc +#define NV9039_SET_SPARE_NOOP11_V 31:0 + +#define NV9039_LAUNCH_DMA 0x0300 +#define NV9039_LAUNCH_DMA_SRC_INLINE 0:0 +#define NV9039_LAUNCH_DMA_SRC_INLINE_FALSE 0x00000000 +#define NV9039_LAUNCH_DMA_SRC_INLINE_TRUE 0x00000001 +#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT 4:4 +#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH 0x00000001 +#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE 13:12 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE 17:16 +#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 20:20 +#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 + +#define NV9039_LOAD_INLINE_DATA 0x0304 +#define NV9039_LOAD_INLINE_DATA_V 31:0 + +#define NV9039_SET_RENDER_ENABLE_OVERRIDE 0x0308 +#define NV9039_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV9039_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV9039_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV9039_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV9039_OFFSET_IN_UPPER 0x030c +#define NV9039_OFFSET_IN_UPPER_VALUE 7:0 + +#define NV9039_OFFSET_IN 0x0310 +#define NV9039_OFFSET_IN_VALUE 31:0 + +#define NV9039_PITCH_IN 0x0314 +#define NV9039_PITCH_IN_VALUE 31:0 + +#define NV9039_PITCH_OUT 0x0318 +#define NV9039_PITCH_OUT_VALUE 31:0 + +#define NV9039_LINE_LENGTH_IN 0x031c +#define NV9039_LINE_LENGTH_IN_VALUE 31:0 + +#define NV9039_LINE_COUNT 0x0320 +#define NV9039_LINE_COUNT_VALUE 31:0 + +#define NV9039_SET_SEMAPHORE_A 0x032c +#define NV9039_SET_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV9039_SET_SEMAPHORE_B 0x0330 +#define NV9039_SET_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV9039_SET_SEMAPHORE_C 0x0334 +#define NV9039_SET_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV9039_SET_RENDER_ENABLE_A 0x0338 +#define NV9039_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV9039_SET_RENDER_ENABLE_B 0x033c +#define NV9039_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV9039_SET_RENDER_ENABLE_C 0x0340 +#define NV9039_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV9039_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV9039_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV9039_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV9039_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV9039_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV9039_SET_SRC_ORIGIN_BYTES_X 0x0344 +#define NV9039_SET_SRC_ORIGIN_BYTES_X_V 19:0 + +#define NV9039_SET_SRC_ORIGIN_SAMPLES_Y 0x0348 +#define NV9039_SET_SRC_ORIGIN_SAMPLES_Y_V 15:0 + +#define NV9039_SET_DST_ORIGIN_BYTES_X 0x034c +#define NV9039_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NV9039_SET_DST_ORIGIN_SAMPLES_Y 0x0350 +#define NV9039_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NV9039_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV9039_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV9039_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV9039_CALL_MME_MACRO_V 31:0 + +#define NV9039_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV9039_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_memory_to_memory_format_a_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl90b5.h b/src/nouveau/nvidia-headers/classes/cl90b5.h new file mode 100644 index 0000000..2947b09 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl90b5.h @@ -0,0 +1,262 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _cl90b5_h_ +#define _cl90b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define GF100_DMA_COPY (0x000090B5) + +#define NV90B5_LL_CMD1 (0x00000000) +#define NV90B5_LL_CMD1_SRC_MAX_GOBLINE_PAD_POLICY 1:0 +#define NV90B5_LL_CMD1_DST_MAX_GOBLINE_PAD_POLICY 3:2 +#define NV90B5_LL_CMD1_SRC_NONCROSSING_BOUNDARY 7:4 +#define NV90B5_LL_CMD1_DST_NONCROSSING_BOUNDARY 11:8 +#define NV90B5_LL_CMD1_P2_P_1_LINE_TRAVERSAL 12:12 +#define NV90B5_LL_CMD1_NO_WRITE_B14 17:17 +#define NV90B5_LL_CMD1_SELECT_OUT_B15 22:18 +#define NV90B5_LL_CMD1_NO_WRITE_B15 23:23 +#define NV90B5_LL_CMD1_COPY_TYPE_SWIZ 9:9 +#define NV90B5_LL_CMD1_COPY_TYPE_BIGMEM 10:10 +#define NV90B5_LL_CMD1_BURSTSIZE_SRC 13:11 +#define NV90B5_LL_CMD1_BURSTSIZE_DST 16:14 +#define NV90B5_LL_CMD1_GOBWIDTH_SRC 17:17 +#define NV90B5_LL_CMD1_GOBWIDTH_DST 18:18 +#define NV90B5_LL_CMD1_PIPELINED_READS 19:19 +#define NV90B5_LL_CMD1_SRC_CTXDMA 22:20 +#define NV90B5_LL_CMD1_DST_CTXDMA 25:23 +#define NV90B5_NOP (0x00000100) +#define NV90B5_NOP_PARAMETER 31:0 +#define NV90B5_PM_TRIGGER (0x00000140) +#define NV90B5_PM_TRIGGER_V 31:0 +#define NV90B5_SET_APPLICATION_ID (0x00000200) +#define NV90B5_SET_APPLICATION_ID_ID 31:0 +#define NV90B5_SET_APPLICATION_ID_ID_NORMAL (0x00000001) +#define NV90B5_SET_APPLICATION_ID_ID_LOW_LEVEL_CLASS (0x00000003) +#define NV90B5_SET_WATCHDOG_TIMER (0x00000204) +#define NV90B5_SET_WATCHDOG_TIMER_TIMER 31:0 +#define NV90B5_SET_SEMAPHORE_A (0x00000240) +#define NV90B5_SET_SEMAPHORE_A_UPPER 7:0 +#define NV90B5_SET_SEMAPHORE_B (0x00000244) +#define NV90B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NV90B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NV90B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NV90B5_ADDRESSING_MODE (0x00000250) +#define NV90B5_ADDRESSING_MODE_SRC_TYPE 0:0 +#define NV90B5_ADDRESSING_MODE_SRC_TYPE_VIRTUAL (0x00000000) +#define NV90B5_ADDRESSING_MODE_SRC_TYPE_PHYSICAL (0x00000001) +#define NV90B5_ADDRESSING_MODE_SRC_TARGET 5:4 +#define NV90B5_ADDRESSING_MODE_SRC_TARGET_LOCAL_FB (0x00000000) +#define NV90B5_ADDRESSING_MODE_SRC_TARGET_COHERENT_SYSMEM (0x00000001) +#define NV90B5_ADDRESSING_MODE_SRC_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NV90B5_ADDRESSING_MODE_DST_TYPE 8:8 +#define NV90B5_ADDRESSING_MODE_DST_TYPE_VIRTUAL (0x00000000) +#define NV90B5_ADDRESSING_MODE_DST_TYPE_PHYSICAL (0x00000001) +#define NV90B5_ADDRESSING_MODE_DST_TARGET 13:12 +#define NV90B5_ADDRESSING_MODE_DST_TARGET_LOCAL_FB (0x00000000) +#define NV90B5_ADDRESSING_MODE_DST_TARGET_COHERENT_SYSMEM (0x00000001) +#define NV90B5_ADDRESSING_MODE_DST_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NV90B5_SET_RENDER_ENABLE_A (0x00000254) +#define NV90B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NV90B5_SET_RENDER_ENABLE_B (0x00000258) +#define NV90B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NV90B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NV90B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV90B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NV90B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NV90B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NV90B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NV90B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NV90B5_LAUNCH_DMA (0x00000300) +#define NV90B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NV90B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NV90B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NV90B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NV90B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NV90B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NV90B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NV90B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NV90B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NV90B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NV90B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NV90B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NV90B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NV90B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NV90B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NV90B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NV90B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV90B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV90B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NV90B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV90B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV90B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NV90B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NV90B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NV90B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NV90B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NV90B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NV90B5_OFFSET_IN_UPPER (0x00000400) +#define NV90B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NV90B5_OFFSET_IN_LOWER (0x00000404) +#define NV90B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NV90B5_OFFSET_OUT_UPPER (0x00000408) +#define NV90B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NV90B5_OFFSET_OUT_LOWER (0x0000040C) +#define NV90B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NV90B5_PITCH_IN (0x00000410) +#define NV90B5_PITCH_IN_VALUE 31:0 +#define NV90B5_PITCH_OUT (0x00000414) +#define NV90B5_PITCH_OUT_VALUE 31:0 +#define NV90B5_LINE_LENGTH_IN (0x00000418) +#define NV90B5_LINE_LENGTH_IN_VALUE 31:0 +#define NV90B5_LINE_COUNT (0x0000041C) +#define NV90B5_LINE_COUNT_VALUE 31:0 +#define NV90B5_SET_REMAP_CONST_A (0x00000700) +#define NV90B5_SET_REMAP_CONST_A_V 31:0 +#define NV90B5_SET_REMAP_CONST_B (0x00000704) +#define NV90B5_SET_REMAP_CONST_B_V 31:0 +#define NV90B5_SET_REMAP_COMPONENTS (0x00000708) +#define NV90B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NV90B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NV90B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NV90B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NV90B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NV90B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NV90B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NV90B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NV90B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NV90B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NV90B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NV90B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NV90B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NV90B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NV90B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NV90B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NV90B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NV90B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NV90B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NV90B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NV90B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NV90B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NV90B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NV90B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NV90B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NV90B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NV90B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NV90B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NV90B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NV90B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NV90B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NV90B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NV90B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NV90B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NV90B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NV90B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NV90B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NV90B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV90B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV90B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV90B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NV90B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NV90B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NV90B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NV90B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NV90B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NV90B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NV90B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NV90B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NV90B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NV90B5_SET_DST_WIDTH (0x00000710) +#define NV90B5_SET_DST_WIDTH_V 31:0 +#define NV90B5_SET_DST_HEIGHT (0x00000714) +#define NV90B5_SET_DST_HEIGHT_V 31:0 +#define NV90B5_SET_DST_DEPTH (0x00000718) +#define NV90B5_SET_DST_DEPTH_V 31:0 +#define NV90B5_SET_DST_LAYER (0x0000071C) +#define NV90B5_SET_DST_LAYER_V 31:0 +#define NV90B5_SET_DST_ORIGIN (0x00000720) +#define NV90B5_SET_DST_ORIGIN_X 15:0 +#define NV90B5_SET_DST_ORIGIN_Y 31:16 +#define NV90B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NV90B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NV90B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NV90B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NV90B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NV90B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NV90B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NV90B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NV90B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV90B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV90B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV90B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NV90B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NV90B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NV90B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NV90B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NV90B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NV90B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NV90B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NV90B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NV90B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NV90B5_SET_SRC_WIDTH (0x0000072C) +#define NV90B5_SET_SRC_WIDTH_V 31:0 +#define NV90B5_SET_SRC_HEIGHT (0x00000730) +#define NV90B5_SET_SRC_HEIGHT_V 31:0 +#define NV90B5_SET_SRC_DEPTH (0x00000734) +#define NV90B5_SET_SRC_DEPTH_V 31:0 +#define NV90B5_SET_SRC_LAYER (0x00000738) +#define NV90B5_SET_SRC_LAYER_V 31:0 +#define NV90B5_SET_SRC_ORIGIN (0x0000073C) +#define NV90B5_SET_SRC_ORIGIN_X 15:0 +#define NV90B5_SET_SRC_ORIGIN_Y 31:16 +#define NV90B5_PM_TRIGGER_END (0x00001114) +#define NV90B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl90b5_h + diff --git a/src/nouveau/nvidia-headers/classes/cl90c0.h b/src/nouveau/nvidia-headers/classes/cl90c0.h new file mode 100644 index 0000000..3996a5c --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl90c0.h @@ -0,0 +1,808 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_compute_a_h_ +#define _cl_fermi_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl fermi_compute_a */ + +#include "nvtypes.h" + +#define FERMI_COMPUTE_A 0x90C0 + +#define NV90C0_SET_OBJECT 0x0000 +#define NV90C0_SET_OBJECT_CLASS_ID 15:0 +#define NV90C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NV90C0_NO_OPERATION 0x0100 +#define NV90C0_NO_OPERATION_V 31:0 + +#define NV90C0_SET_NOTIFY_A 0x0104 +#define NV90C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NV90C0_SET_NOTIFY_B 0x0108 +#define NV90C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV90C0_NOTIFY 0x010c +#define NV90C0_NOTIFY_TYPE 31:0 +#define NV90C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV90C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV90C0_WAIT_FOR_IDLE 0x0110 +#define NV90C0_WAIT_FOR_IDLE_V 31:0 + +#define NV90C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV90C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV90C0_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV90C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV90C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV90C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV90C0_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV90C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV90C0_SEND_GO_IDLE 0x013c +#define NV90C0_SEND_GO_IDLE_V 31:0 + +#define NV90C0_PM_TRIGGER 0x0140 +#define NV90C0_PM_TRIGGER_V 31:0 + +#define NV90C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV90C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV90C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV90C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE 0x0204 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V 23:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE 0x0208 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V 23:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE 0x020c +#define NV90C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V 20:0 + +#define NV90C0_SET_BINDING_CONTROL_TEXTURE 0x0210 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV90C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NV90C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV90C0_INVALIDATE_SHADER_CACHES 0x021c +#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NV90C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 +#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NV90C0_BIND_TEXTURE_SAMPLER 0x0228 +#define NV90C0_BIND_TEXTURE_SAMPLER_VALID 0:0 +#define NV90C0_BIND_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV90C0_BIND_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV90C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV90C0_BIND_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV90C0_BIND_TEXTURE_HEADER 0x022c +#define NV90C0_BIND_TEXTURE_HEADER_VALID 0:0 +#define NV90C0_BIND_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV90C0_BIND_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV90C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV90C0_BIND_TEXTURE_HEADER_INDEX 30:9 + +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER 0x0230 +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID 0:0 +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER 0x0234 +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID 0:0 +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_INDEX 30:9 + +#define NV90C0_SET_CTA_RASTER_SIZE_A 0x0238 +#define NV90C0_SET_CTA_RASTER_SIZE_A_WIDTH 15:0 +#define NV90C0_SET_CTA_RASTER_SIZE_A_HEIGHT 31:16 + +#define NV90C0_SET_CTA_RASTER_SIZE_B 0x023c +#define NV90C0_SET_CTA_RASTER_SIZE_B_DEPTH 15:0 + +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NV90C0_SET_SHADER_SHARED_MEMORY_SIZE 0x024c +#define NV90C0_SET_SHADER_SHARED_MEMORY_SIZE_V 17:0 + +#define NV90C0_SET_CTA_THREAD_COUNT 0x0250 +#define NV90C0_SET_CTA_THREAD_COUNT_V 15:0 + +#define NV90C0_SET_CTA_BARRIER_COUNT 0x0254 +#define NV90C0_SET_CTA_BARRIER_COUNT_V 7:0 + +#define NV90C0_TEST_FOR_COMPUTE 0x028c +#define NV90C0_TEST_FOR_COMPUTE_V 31:0 + +#define NV90C0_BEGIN_GRID 0x029c +#define NV90C0_BEGIN_GRID_V 0:0 + +#define NV90C0_SET_WORK_DISTRIBUTION 0x02a0 +#define NV90C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE 16:13 +#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE 4:4 +#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE 0x00000000 +#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE 0x00000001 +#define NV90C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS 12:5 + +#define NV90C0_SET_CTA_REGISTER_COUNT 0x02c0 +#define NV90C0_SET_CTA_REGISTER_COUNT_V 7:0 + +#define NV90C0_SET_GA_TO_VA_MAPPING_MODE 0x02c4 +#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V 0:0 +#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 +#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 + +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 + +#define NV90C0_SET_L1_CONFIGURATION 0x0308 +#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NV90C0_SET_RENDER_ENABLE_CONTROL 0x030c +#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NV90C0_WAIT_REF_COUNT 0x0360 +#define NV90C0_WAIT_REF_COUNT_REF_CNT 9:8 +#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM 0:0 +#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE 0x00000000 +#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE 0x00000001 + +#define NV90C0_LAUNCH 0x0368 +#define NV90C0_LAUNCHCTA_PARAM 31:0 + +#define NV90C0_SET_LAUNCH_ID 0x036c +#define NV90C0_SET_LAUNCH_ID_REF_CNT 1:0 + +#define NV90C0_SET_CTA_THREAD_DIMENSION_A 0x03ac +#define NV90C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 +#define NV90C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 + +#define NV90C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 +#define NV90C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 + +#define NV90C0_SET_CTA_PROGRAM_START 0x03b4 +#define NV90C0_SET_CTA_PROGRAM_START_OFFSET 31:0 + +#define NV90C0_SET_FALCON00 0x0500 +#define NV90C0_SET_FALCON00_V 31:0 + +#define NV90C0_SET_FALCON01 0x0504 +#define NV90C0_SET_FALCON01_V 31:0 + +#define NV90C0_SET_FALCON02 0x0508 +#define NV90C0_SET_FALCON02_V 31:0 + +#define NV90C0_SET_FALCON03 0x050c +#define NV90C0_SET_FALCON03_V 31:0 + +#define NV90C0_SET_FALCON04 0x0510 +#define NV90C0_SET_FALCON04_V 31:0 + +#define NV90C0_SET_FALCON05 0x0514 +#define NV90C0_SET_FALCON05_V 31:0 + +#define NV90C0_SET_FALCON06 0x0518 +#define NV90C0_SET_FALCON06_V 31:0 + +#define NV90C0_SET_FALCON07 0x051c +#define NV90C0_SET_FALCON07_V 31:0 + +#define NV90C0_SET_FALCON08 0x0520 +#define NV90C0_SET_FALCON08_V 31:0 + +#define NV90C0_SET_FALCON09 0x0524 +#define NV90C0_SET_FALCON09_V 31:0 + +#define NV90C0_SET_FALCON10 0x0528 +#define NV90C0_SET_FALCON10_V 31:0 + +#define NV90C0_SET_FALCON11 0x052c +#define NV90C0_SET_FALCON11_V 31:0 + +#define NV90C0_SET_FALCON12 0x0530 +#define NV90C0_SET_FALCON12_V 31:0 + +#define NV90C0_SET_FALCON13 0x0534 +#define NV90C0_SET_FALCON13_V 31:0 + +#define NV90C0_SET_FALCON14 0x0538 +#define NV90C0_SET_FALCON14_V 31:0 + +#define NV90C0_SET_FALCON15 0x053c +#define NV90C0_SET_FALCON15_V 31:0 + +#define NV90C0_SET_FALCON16 0x0540 +#define NV90C0_SET_FALCON16_V 31:0 + +#define NV90C0_SET_FALCON17 0x0544 +#define NV90C0_SET_FALCON17_V 31:0 + +#define NV90C0_SET_FALCON18 0x0548 +#define NV90C0_SET_FALCON18_V 31:0 + +#define NV90C0_SET_FALCON19 0x054c +#define NV90C0_SET_FALCON19_V 31:0 + +#define NV90C0_SET_FALCON20 0x0550 +#define NV90C0_SET_FALCON20_V 31:0 + +#define NV90C0_SET_FALCON21 0x0554 +#define NV90C0_SET_FALCON21_V 31:0 + +#define NV90C0_SET_FALCON22 0x0558 +#define NV90C0_SET_FALCON22_V 31:0 + +#define NV90C0_SET_FALCON23 0x055c +#define NV90C0_SET_FALCON23_V 31:0 + +#define NV90C0_SET_FALCON24 0x0560 +#define NV90C0_SET_FALCON24_V 31:0 + +#define NV90C0_SET_FALCON25 0x0564 +#define NV90C0_SET_FALCON25_V 31:0 + +#define NV90C0_SET_FALCON26 0x0568 +#define NV90C0_SET_FALCON26_V 31:0 + +#define NV90C0_SET_FALCON27 0x056c +#define NV90C0_SET_FALCON27_V 31:0 + +#define NV90C0_SET_FALCON28 0x0570 +#define NV90C0_SET_FALCON28_V 31:0 + +#define NV90C0_SET_FALCON29 0x0574 +#define NV90C0_SET_FALCON29_V 31:0 + +#define NV90C0_SET_FALCON30 0x0578 +#define NV90C0_SET_FALCON30_V 31:0 + +#define NV90C0_SET_FALCON31 0x057c +#define NV90C0_SET_FALCON31_V 31:0 + +#define NV90C0_SET_MAX_SM_COUNT 0x0758 +#define NV90C0_SET_MAX_SM_COUNT_V 8:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NV90C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV90C0_SET_GRID_PARAM 0x0780 +#define NV90C0_SET_GRID_PARAM_V 31:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NV90C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NV90C0_END_GRID 0x0a04 +#define NV90C0_END_GRID_V 0:0 + +#define NV90C0_SET_LAUNCH_SIZE 0x0a08 +#define NV90C0_SET_LAUNCH_SIZE_V 31:0 + +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA 3:0 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0 0x00000000 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1 0x00000001 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2 0x00000002 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4 0x00000003 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8 0x00000004 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16 0x00000005 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32 0x00000006 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64 0x00000007 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128 0x00000008 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK 0x0000000F + +#define NV90C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NV90C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NV90C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV90C0_SET_SPARE_NOOP12 0x0f44 +#define NV90C0_SET_SPARE_NOOP12_V 31:0 + +#define NV90C0_SET_SPARE_NOOP13 0x0f48 +#define NV90C0_SET_SPARE_NOOP13_V 31:0 + +#define NV90C0_SET_SPARE_NOOP14 0x0f4c +#define NV90C0_SET_SPARE_NOOP14_V 31:0 + +#define NV90C0_SET_SPARE_NOOP15 0x0f50 +#define NV90C0_SET_SPARE_NOOP15_V 31:0 + +#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 +#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 +#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 +#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 + +#define NV90C0_SET_SPARE_NOOP00 0x1040 +#define NV90C0_SET_SPARE_NOOP00_V 31:0 + +#define NV90C0_SET_SPARE_NOOP01 0x1044 +#define NV90C0_SET_SPARE_NOOP01_V 31:0 + +#define NV90C0_SET_SPARE_NOOP02 0x1048 +#define NV90C0_SET_SPARE_NOOP02_V 31:0 + +#define NV90C0_SET_SPARE_NOOP03 0x104c +#define NV90C0_SET_SPARE_NOOP03_V 31:0 + +#define NV90C0_SET_SPARE_NOOP04 0x1050 +#define NV90C0_SET_SPARE_NOOP04_V 31:0 + +#define NV90C0_SET_SPARE_NOOP05 0x1054 +#define NV90C0_SET_SPARE_NOOP05_V 31:0 + +#define NV90C0_SET_SPARE_NOOP06 0x1058 +#define NV90C0_SET_SPARE_NOOP06_V 31:0 + +#define NV90C0_SET_SPARE_NOOP07 0x105c +#define NV90C0_SET_SPARE_NOOP07_V 31:0 + +#define NV90C0_SET_SPARE_NOOP08 0x1060 +#define NV90C0_SET_SPARE_NOOP08_V 31:0 + +#define NV90C0_SET_SPARE_NOOP09 0x1064 +#define NV90C0_SET_SPARE_NOOP09_V 31:0 + +#define NV90C0_SET_SPARE_NOOP10 0x1068 +#define NV90C0_SET_SPARE_NOOP10_V 31:0 + +#define NV90C0_SET_SPARE_NOOP11 0x106c +#define NV90C0_SET_SPARE_NOOP11_V 31:0 + +#define NV90C0_UNBIND_ALL 0x10f4 +#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS 0:0 +#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 +#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 +#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 +#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 +#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 +#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NV90C0_SET_SAMPLER_BINDING 0x1234 +#define NV90C0_SET_SAMPLER_BINDING_V 0:0 +#define NV90C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV90C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NV90C0_SET_SHADER_SCHEDULING 0x12ac +#define NV90C0_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV90C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV90C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV90C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 + +#define NV90C0_SET_GLOBAL_COLOR_KEY 0x1354 +#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NV90C0_PERFMON_TRANSFER 0x1524 +#define NV90C0_PERFMON_TRANSFER_V 31:0 + +#define NV90C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV90C0_SET_RENDER_ENABLE_A 0x1550 +#define NV90C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_RENDER_ENABLE_B 0x1554 +#define NV90C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_RENDER_ENABLE_C 0x1558 +#define NV90C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV90C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV90C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV90C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV90C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV90C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV90C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NV90C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NV90C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NV90C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV90C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NV90C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NV90C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_TEX_HEADER_POOL_C 0x157c +#define NV90C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV90C0_SET_PROGRAM_REGION_A 0x1608 +#define NV90C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NV90C0_SET_PROGRAM_REGION_B 0x160c +#define NV90C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 1:0 +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 + +#define NV90C0_SET_SHADER_CONTROL 0x1690 +#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV90C0_BIND_CONSTANT_BUFFER 0x1694 +#define NV90C0_BIND_CONSTANT_BUFFER_VALID 0:0 +#define NV90C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV90C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV90C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 12:8 + +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM 8:8 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NV90C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV90C0_PIPE_NOP 0x1a2c +#define NV90C0_PIPE_NOP_V 31:0 + +#define NV90C0_SET_SPARE00 0x1a30 +#define NV90C0_SET_SPARE00_V 31:0 + +#define NV90C0_SET_SPARE01 0x1a34 +#define NV90C0_SET_SPARE01_V 31:0 + +#define NV90C0_SET_SPARE02 0x1a38 +#define NV90C0_SET_SPARE02_V 31:0 + +#define NV90C0_SET_SPARE03 0x1a3c +#define NV90C0_SET_SPARE03_V 31:0 + +#define NV90C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NV90C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NV90C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NV90C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV90C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 + +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NV90C0_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NV90C0_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NV90C0_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NV90C0_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NV90C0_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 + +#define NV90C0_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 +#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 +#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 +#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 + +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT 25:17 + +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 + +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NV90C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV90C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV90C0_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV90C0_CALL_MME_MACRO_V 31:0 + +#define NV90C0_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV90C0_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_compute_a_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cl91c0.h b/src/nouveau/nvidia-headers/classes/cl91c0.h new file mode 100644 index 0000000..c5d393d --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cl91c0.h @@ -0,0 +1,822 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_compute_b_h_ +#define _cl_fermi_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl fermi_compute_b */ + +#include "nvtypes.h" + +#define FERMI_COMPUTE_B 0x91C0 + +#define NV91C0_SET_OBJECT 0x0000 +#define NV91C0_SET_OBJECT_CLASS_ID 15:0 +#define NV91C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NV91C0_NO_OPERATION 0x0100 +#define NV91C0_NO_OPERATION_V 31:0 + +#define NV91C0_SET_NOTIFY_A 0x0104 +#define NV91C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NV91C0_SET_NOTIFY_B 0x0108 +#define NV91C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV91C0_NOTIFY 0x010c +#define NV91C0_NOTIFY_TYPE 31:0 +#define NV91C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV91C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV91C0_WAIT_FOR_IDLE 0x0110 +#define NV91C0_WAIT_FOR_IDLE_V 31:0 + +#define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV91C0_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV91C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV91C0_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV91C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV91C0_SEND_GO_IDLE 0x013c +#define NV91C0_SEND_GO_IDLE_V 31:0 + +#define NV91C0_PM_TRIGGER 0x0140 +#define NV91C0_PM_TRIGGER_V 31:0 + +#define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV91C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV91C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE 0x0204 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V 23:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE 0x0208 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V 23:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE 0x020c +#define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V 20:0 + +#define NV91C0_SET_BINDING_CONTROL_TEXTURE 0x0210 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV91C0_INVALIDATE_SHADER_CACHES 0x021c +#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NV91C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 +#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NV91C0_BIND_TEXTURE_SAMPLER 0x0228 +#define NV91C0_BIND_TEXTURE_SAMPLER_VALID 0:0 +#define NV91C0_BIND_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV91C0_BIND_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV91C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV91C0_BIND_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV91C0_BIND_TEXTURE_HEADER 0x022c +#define NV91C0_BIND_TEXTURE_HEADER_VALID 0:0 +#define NV91C0_BIND_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV91C0_BIND_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV91C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV91C0_BIND_TEXTURE_HEADER_INDEX 30:9 + +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER 0x0230 +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID 0:0 +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER 0x0234 +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID 0:0 +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_INDEX 30:9 + +#define NV91C0_SET_CTA_RASTER_SIZE_A 0x0238 +#define NV91C0_SET_CTA_RASTER_SIZE_A_WIDTH 15:0 +#define NV91C0_SET_CTA_RASTER_SIZE_A_HEIGHT 31:16 + +#define NV91C0_SET_CTA_RASTER_SIZE_B 0x023c +#define NV91C0_SET_CTA_RASTER_SIZE_B_DEPTH 15:0 +#define NV91C0_SET_CTA_RASTER_SIZE_B_WIDTH_UPPER 31:16 + +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE 0x024c +#define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE_V 17:0 + +#define NV91C0_SET_CTA_THREAD_COUNT 0x0250 +#define NV91C0_SET_CTA_THREAD_COUNT_V 15:0 + +#define NV91C0_SET_CTA_BARRIER_COUNT 0x0254 +#define NV91C0_SET_CTA_BARRIER_COUNT_V 7:0 + +#define NV91C0_TEST_FOR_COMPUTE 0x028c +#define NV91C0_TEST_FOR_COMPUTE_V 31:0 + +#define NV91C0_BEGIN_GRID 0x029c +#define NV91C0_BEGIN_GRID_V 0:0 + +#define NV91C0_SET_WORK_DISTRIBUTION 0x02a0 +#define NV91C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE 16:13 +#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE 4:4 +#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE 0x00000000 +#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE 0x00000001 +#define NV91C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS 12:5 + +#define NV91C0_SET_CTA_REGISTER_COUNT 0x02c0 +#define NV91C0_SET_CTA_REGISTER_COUNT_V 7:0 + +#define NV91C0_SET_GA_TO_VA_MAPPING_MODE 0x02c4 +#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V 0:0 +#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 +#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 + +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 + +#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS 0x02e0 +#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE 0:0 +#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_TRUE 0x00000001 + +#define NV91C0_SET_L1_CONFIGURATION 0x0308 +#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NV91C0_SET_RENDER_ENABLE_CONTROL 0x030c +#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NV91C0_WAIT_REF_COUNT 0x0360 +#define NV91C0_WAIT_REF_COUNT_REF_CNT 11:8 +#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM 0:0 +#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE 0x00000000 +#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE 0x00000001 + +#define NV91C0_LAUNCH 0x0368 +#define NV91C0_LAUNCHCTA_PARAM 31:0 + +#define NV91C0_SET_LAUNCH_ID 0x036c +#define NV91C0_SET_LAUNCH_ID_REF_CNT 3:0 + +#define NV91C0_SET_CTA_THREAD_DIMENSION_A 0x03ac +#define NV91C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 +#define NV91C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 + +#define NV91C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 +#define NV91C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 + +#define NV91C0_SET_CTA_PROGRAM_START 0x03b4 +#define NV91C0_SET_CTA_PROGRAM_START_OFFSET 31:0 + +#define NV91C0_SET_FALCON00 0x0500 +#define NV91C0_SET_FALCON00_V 31:0 + +#define NV91C0_SET_FALCON01 0x0504 +#define NV91C0_SET_FALCON01_V 31:0 + +#define NV91C0_SET_FALCON02 0x0508 +#define NV91C0_SET_FALCON02_V 31:0 + +#define NV91C0_SET_FALCON03 0x050c +#define NV91C0_SET_FALCON03_V 31:0 + +#define NV91C0_SET_FALCON04 0x0510 +#define NV91C0_SET_FALCON04_V 31:0 + +#define NV91C0_SET_FALCON05 0x0514 +#define NV91C0_SET_FALCON05_V 31:0 + +#define NV91C0_SET_FALCON06 0x0518 +#define NV91C0_SET_FALCON06_V 31:0 + +#define NV91C0_SET_FALCON07 0x051c +#define NV91C0_SET_FALCON07_V 31:0 + +#define NV91C0_SET_FALCON08 0x0520 +#define NV91C0_SET_FALCON08_V 31:0 + +#define NV91C0_SET_FALCON09 0x0524 +#define NV91C0_SET_FALCON09_V 31:0 + +#define NV91C0_SET_FALCON10 0x0528 +#define NV91C0_SET_FALCON10_V 31:0 + +#define NV91C0_SET_FALCON11 0x052c +#define NV91C0_SET_FALCON11_V 31:0 + +#define NV91C0_SET_FALCON12 0x0530 +#define NV91C0_SET_FALCON12_V 31:0 + +#define NV91C0_SET_FALCON13 0x0534 +#define NV91C0_SET_FALCON13_V 31:0 + +#define NV91C0_SET_FALCON14 0x0538 +#define NV91C0_SET_FALCON14_V 31:0 + +#define NV91C0_SET_FALCON15 0x053c +#define NV91C0_SET_FALCON15_V 31:0 + +#define NV91C0_SET_FALCON16 0x0540 +#define NV91C0_SET_FALCON16_V 31:0 + +#define NV91C0_SET_FALCON17 0x0544 +#define NV91C0_SET_FALCON17_V 31:0 + +#define NV91C0_SET_FALCON18 0x0548 +#define NV91C0_SET_FALCON18_V 31:0 + +#define NV91C0_SET_FALCON19 0x054c +#define NV91C0_SET_FALCON19_V 31:0 + +#define NV91C0_SET_FALCON20 0x0550 +#define NV91C0_SET_FALCON20_V 31:0 + +#define NV91C0_SET_FALCON21 0x0554 +#define NV91C0_SET_FALCON21_V 31:0 + +#define NV91C0_SET_FALCON22 0x0558 +#define NV91C0_SET_FALCON22_V 31:0 + +#define NV91C0_SET_FALCON23 0x055c +#define NV91C0_SET_FALCON23_V 31:0 + +#define NV91C0_SET_FALCON24 0x0560 +#define NV91C0_SET_FALCON24_V 31:0 + +#define NV91C0_SET_FALCON25 0x0564 +#define NV91C0_SET_FALCON25_V 31:0 + +#define NV91C0_SET_FALCON26 0x0568 +#define NV91C0_SET_FALCON26_V 31:0 + +#define NV91C0_SET_FALCON27 0x056c +#define NV91C0_SET_FALCON27_V 31:0 + +#define NV91C0_SET_FALCON28 0x0570 +#define NV91C0_SET_FALCON28_V 31:0 + +#define NV91C0_SET_FALCON29 0x0574 +#define NV91C0_SET_FALCON29_V 31:0 + +#define NV91C0_SET_FALCON30 0x0578 +#define NV91C0_SET_FALCON30_V 31:0 + +#define NV91C0_SET_FALCON31 0x057c +#define NV91C0_SET_FALCON31_V 31:0 + +#define NV91C0_SET_MAX_SM_COUNT 0x0758 +#define NV91C0_SET_MAX_SM_COUNT_V 8:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV91C0_SET_GRID_PARAM 0x0780 +#define NV91C0_SET_GRID_PARAM_V 31:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NV91C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NV91C0_END_GRID 0x0a04 +#define NV91C0_END_GRID_V 0:0 + +#define NV91C0_SET_LAUNCH_SIZE 0x0a08 +#define NV91C0_SET_LAUNCH_SIZE_V 31:0 + +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA 3:0 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0 0x00000000 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1 0x00000001 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2 0x00000002 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4 0x00000003 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8 0x00000004 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16 0x00000005 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32 0x00000006 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64 0x00000007 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128 0x00000008 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK 0x0000000F + +#define NV91C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NV91C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NV91C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV91C0_SET_SPARE_NOOP12 0x0f44 +#define NV91C0_SET_SPARE_NOOP12_V 31:0 + +#define NV91C0_SET_SPARE_NOOP13 0x0f48 +#define NV91C0_SET_SPARE_NOOP13_V 31:0 + +#define NV91C0_SET_SPARE_NOOP14 0x0f4c +#define NV91C0_SET_SPARE_NOOP14_V 31:0 + +#define NV91C0_SET_SPARE_NOOP15 0x0f50 +#define NV91C0_SET_SPARE_NOOP15_V 31:0 + +#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 +#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 +#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 + +#define NV91C0_SET_SPARE_NOOP00 0x1040 +#define NV91C0_SET_SPARE_NOOP00_V 31:0 + +#define NV91C0_SET_SPARE_NOOP01 0x1044 +#define NV91C0_SET_SPARE_NOOP01_V 31:0 + +#define NV91C0_SET_SPARE_NOOP02 0x1048 +#define NV91C0_SET_SPARE_NOOP02_V 31:0 + +#define NV91C0_SET_SPARE_NOOP03 0x104c +#define NV91C0_SET_SPARE_NOOP03_V 31:0 + +#define NV91C0_SET_SPARE_NOOP04 0x1050 +#define NV91C0_SET_SPARE_NOOP04_V 31:0 + +#define NV91C0_SET_SPARE_NOOP05 0x1054 +#define NV91C0_SET_SPARE_NOOP05_V 31:0 + +#define NV91C0_SET_SPARE_NOOP06 0x1058 +#define NV91C0_SET_SPARE_NOOP06_V 31:0 + +#define NV91C0_SET_SPARE_NOOP07 0x105c +#define NV91C0_SET_SPARE_NOOP07_V 31:0 + +#define NV91C0_SET_SPARE_NOOP08 0x1060 +#define NV91C0_SET_SPARE_NOOP08_V 31:0 + +#define NV91C0_SET_SPARE_NOOP09 0x1064 +#define NV91C0_SET_SPARE_NOOP09_V 31:0 + +#define NV91C0_SET_SPARE_NOOP10 0x1068 +#define NV91C0_SET_SPARE_NOOP10_V 31:0 + +#define NV91C0_SET_SPARE_NOOP11 0x106c +#define NV91C0_SET_SPARE_NOOP11_V 31:0 + +#define NV91C0_UNBIND_ALL 0x10f4 +#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS 0:0 +#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 +#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 +#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 +#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 +#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 +#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NV91C0_SET_SAMPLER_BINDING 0x1234 +#define NV91C0_SET_SAMPLER_BINDING_V 0:0 +#define NV91C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV91C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NV91C0_SET_SHADER_SCHEDULING 0x12ac +#define NV91C0_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV91C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV91C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV91C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 + +#define NV91C0_SET_GLOBAL_COLOR_KEY 0x1354 +#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NV91C0_PERFMON_TRANSFER 0x1524 +#define NV91C0_PERFMON_TRANSFER_V 31:0 + +#define NV91C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV91C0_SET_RENDER_ENABLE_A 0x1550 +#define NV91C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_RENDER_ENABLE_B 0x1554 +#define NV91C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_RENDER_ENABLE_C 0x1558 +#define NV91C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV91C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV91C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV91C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV91C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NV91C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NV91C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NV91C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV91C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NV91C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NV91C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_TEX_HEADER_POOL_C 0x157c +#define NV91C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV91C0_SET_PROGRAM_REGION_A 0x1608 +#define NV91C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NV91C0_SET_PROGRAM_REGION_B 0x160c +#define NV91C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 1:0 +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 + +#define NV91C0_SET_SHADER_CONTROL 0x1690 +#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 +#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NV91C0_BIND_CONSTANT_BUFFER 0x1694 +#define NV91C0_BIND_CONSTANT_BUFFER_VALID 0:0 +#define NV91C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV91C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV91C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 12:8 + +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM 8:8 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NV91C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV91C0_PIPE_NOP 0x1a2c +#define NV91C0_PIPE_NOP_V 31:0 + +#define NV91C0_SET_SPARE00 0x1a30 +#define NV91C0_SET_SPARE00_V 31:0 + +#define NV91C0_SET_SPARE01 0x1a34 +#define NV91C0_SET_SPARE01_V 31:0 + +#define NV91C0_SET_SPARE02 0x1a38 +#define NV91C0_SET_SPARE02_V 31:0 + +#define NV91C0_SET_SPARE03 0x1a3c +#define NV91C0_SET_SPARE03_V 31:0 + +#define NV91C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NV91C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NV91C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NV91C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV91C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 + +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NV91C0_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NV91C0_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NV91C0_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 + +#define NV91C0_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 +#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 +#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 +#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 + +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_B8G8R8A8 0x00000047 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT 25:17 + +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 + +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NV91C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV91C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV91C0_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV91C0_CALL_MME_MACRO_V 31:0 + +#define NV91C0_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV91C0_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_compute_b_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cla0b5.h b/src/nouveau/nvidia-headers/classes/cla0b5.h new file mode 100644 index 0000000..92076c6 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cla0b5.h @@ -0,0 +1,262 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _cla0b5_h_ +#define _cla0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define KEPLER_DMA_COPY_A (0x0000A0B5) + +#define NVA0B5_NOP (0x00000100) +#define NVA0B5_NOP_PARAMETER 31:0 +#define NVA0B5_PM_TRIGGER (0x00000140) +#define NVA0B5_PM_TRIGGER_V 31:0 +#define NVA0B5_SET_SEMAPHORE_A (0x00000240) +#define NVA0B5_SET_SEMAPHORE_A_UPPER 7:0 +#define NVA0B5_SET_SEMAPHORE_B (0x00000244) +#define NVA0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVA0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVA0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVA0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVA0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVA0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVA0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVA0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVA0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVA0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_LAUNCH_DMA (0x00000300) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2 11:11 +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL (0x0000000D) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL (0x0000000E) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVA0B5_OFFSET_IN_UPPER (0x00000400) +#define NVA0B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_IN_LOWER (0x00000404) +#define NVA0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVA0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVA0B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVA0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVA0B5_PITCH_IN (0x00000410) +#define NVA0B5_PITCH_IN_VALUE 31:0 +#define NVA0B5_PITCH_OUT (0x00000414) +#define NVA0B5_PITCH_OUT_VALUE 31:0 +#define NVA0B5_LINE_LENGTH_IN (0x00000418) +#define NVA0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVA0B5_LINE_COUNT (0x0000041C) +#define NVA0B5_LINE_COUNT_VALUE 31:0 +#define NVA0B5_SET_REMAP_CONST_A (0x00000700) +#define NVA0B5_SET_REMAP_CONST_A_V 31:0 +#define NVA0B5_SET_REMAP_CONST_B (0x00000704) +#define NVA0B5_SET_REMAP_CONST_B_V 31:0 +#define NVA0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVA0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVA0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVA0B5_SET_DST_WIDTH (0x00000710) +#define NVA0B5_SET_DST_WIDTH_V 31:0 +#define NVA0B5_SET_DST_HEIGHT (0x00000714) +#define NVA0B5_SET_DST_HEIGHT_V 31:0 +#define NVA0B5_SET_DST_DEPTH (0x00000718) +#define NVA0B5_SET_DST_DEPTH_V 31:0 +#define NVA0B5_SET_DST_LAYER (0x0000071C) +#define NVA0B5_SET_DST_LAYER_V 31:0 +#define NVA0B5_SET_DST_ORIGIN (0x00000720) +#define NVA0B5_SET_DST_ORIGIN_X 15:0 +#define NVA0B5_SET_DST_ORIGIN_Y 31:16 +#define NVA0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVA0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVA0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVA0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVA0B5_SET_SRC_WIDTH (0x0000072C) +#define NVA0B5_SET_SRC_WIDTH_V 31:0 +#define NVA0B5_SET_SRC_HEIGHT (0x00000730) +#define NVA0B5_SET_SRC_HEIGHT_V 31:0 +#define NVA0B5_SET_SRC_DEPTH (0x00000734) +#define NVA0B5_SET_SRC_DEPTH_V 31:0 +#define NVA0B5_SET_SRC_LAYER (0x00000738) +#define NVA0B5_SET_SRC_LAYER_V 31:0 +#define NVA0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVA0B5_SET_SRC_ORIGIN_X 15:0 +#define NVA0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVA0B5_PM_TRIGGER_END (0x00001114) +#define NVA0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla0b5_h + diff --git a/src/nouveau/nvidia-headers/classes/cla0c0.h b/src/nouveau/nvidia-headers/classes/cla0c0.h new file mode 100644 index 0000000..b9607df --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cla0c0.h @@ -0,0 +1,645 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_kepler_compute_a_h_ +#define _cl_kepler_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_compute_a */ + +#include "nvtypes.h" + +#define KEPLER_COMPUTE_A 0xA0C0 + +#define NVA0C0_SET_OBJECT 0x0000 +#define NVA0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVA0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA0C0_NO_OPERATION 0x0100 +#define NVA0C0_NO_OPERATION_V 31:0 + +#define NVA0C0_SET_NOTIFY_A 0x0104 +#define NVA0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_NOTIFY_B 0x0108 +#define NVA0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_NOTIFY 0x010c +#define NVA0C0_NOTIFY_TYPE 31:0 +#define NVA0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA0C0_WAIT_FOR_IDLE 0x0110 +#define NVA0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA0C0_SEND_GO_IDLE 0x013c +#define NVA0C0_SEND_GO_IDLE_V 31:0 + +#define NVA0C0_PM_TRIGGER 0x0140 +#define NVA0C0_PM_TRIGGER_V 31:0 + +#define NVA0C0_PM_TRIGGER_WFI 0x0144 +#define NVA0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA0C0_LINE_LENGTH_IN 0x0180 +#define NVA0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA0C0_LINE_COUNT 0x0184 +#define NVA0C0_LINE_COUNT_VALUE 31:0 + +#define NVA0C0_OFFSET_OUT_UPPER 0x0188 +#define NVA0C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA0C0_OFFSET_OUT 0x018c +#define NVA0C0_OFFSET_OUT_VALUE 31:0 + +#define NVA0C0_PITCH_OUT 0x0190 +#define NVA0C0_PITCH_OUT_VALUE 31:0 + +#define NVA0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA0C0_SET_DST_WIDTH 0x0198 +#define NVA0C0_SET_DST_WIDTH_V 31:0 + +#define NVA0C0_SET_DST_HEIGHT 0x019c +#define NVA0C0_SET_DST_HEIGHT_V 31:0 + +#define NVA0C0_SET_DST_DEPTH 0x01a0 +#define NVA0C0_SET_DST_DEPTH_V 31:0 + +#define NVA0C0_SET_DST_LAYER 0x01a4 +#define NVA0C0_SET_DST_LAYER_V 31:0 + +#define NVA0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA0C0_LAUNCH_DMA 0x01b0 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA0C0_LOAD_INLINE_DATA 0x01b4 +#define NVA0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA0C0_PERFMON_TRANSFER 0x0210 +#define NVA0C0_PERFMON_TRANSFER_V 31:0 + +#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA0C0_SET_CWD_CONTROL 0x0240 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVA0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVA0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVA0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVA0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_SET_QMD_VERSION 0x0288 +#define NVA0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVA0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_CHECK_QMD_VERSION 0x0290 +#define NVA0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVA0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVA0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVA0C0_SEND_PCAS_A 0x02b4 +#define NVA0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVA0C0_SEND_PCAS_B 0x02b8 +#define NVA0C0_SEND_PCAS_B_FROM 23:0 +#define NVA0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVA0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA0C0_SET_SPA_VERSION 0x0310 +#define NVA0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVA0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA0C0_SET_FALCON00 0x0500 +#define NVA0C0_SET_FALCON00_V 31:0 + +#define NVA0C0_SET_FALCON01 0x0504 +#define NVA0C0_SET_FALCON01_V 31:0 + +#define NVA0C0_SET_FALCON02 0x0508 +#define NVA0C0_SET_FALCON02_V 31:0 + +#define NVA0C0_SET_FALCON03 0x050c +#define NVA0C0_SET_FALCON03_V 31:0 + +#define NVA0C0_SET_FALCON04 0x0510 +#define NVA0C0_SET_FALCON04_V 31:0 + +#define NVA0C0_SET_FALCON05 0x0514 +#define NVA0C0_SET_FALCON05_V 31:0 + +#define NVA0C0_SET_FALCON06 0x0518 +#define NVA0C0_SET_FALCON06_V 31:0 + +#define NVA0C0_SET_FALCON07 0x051c +#define NVA0C0_SET_FALCON07_V 31:0 + +#define NVA0C0_SET_FALCON08 0x0520 +#define NVA0C0_SET_FALCON08_V 31:0 + +#define NVA0C0_SET_FALCON09 0x0524 +#define NVA0C0_SET_FALCON09_V 31:0 + +#define NVA0C0_SET_FALCON10 0x0528 +#define NVA0C0_SET_FALCON10_V 31:0 + +#define NVA0C0_SET_FALCON11 0x052c +#define NVA0C0_SET_FALCON11_V 31:0 + +#define NVA0C0_SET_FALCON12 0x0530 +#define NVA0C0_SET_FALCON12_V 31:0 + +#define NVA0C0_SET_FALCON13 0x0534 +#define NVA0C0_SET_FALCON13_V 31:0 + +#define NVA0C0_SET_FALCON14 0x0538 +#define NVA0C0_SET_FALCON14_V 31:0 + +#define NVA0C0_SET_FALCON15 0x053c +#define NVA0C0_SET_FALCON15_V 31:0 + +#define NVA0C0_SET_FALCON16 0x0540 +#define NVA0C0_SET_FALCON16_V 31:0 + +#define NVA0C0_SET_FALCON17 0x0544 +#define NVA0C0_SET_FALCON17_V 31:0 + +#define NVA0C0_SET_FALCON18 0x0548 +#define NVA0C0_SET_FALCON18_V 31:0 + +#define NVA0C0_SET_FALCON19 0x054c +#define NVA0C0_SET_FALCON19_V 31:0 + +#define NVA0C0_SET_FALCON20 0x0550 +#define NVA0C0_SET_FALCON20_V 31:0 + +#define NVA0C0_SET_FALCON21 0x0554 +#define NVA0C0_SET_FALCON21_V 31:0 + +#define NVA0C0_SET_FALCON22 0x0558 +#define NVA0C0_SET_FALCON22_V 31:0 + +#define NVA0C0_SET_FALCON23 0x055c +#define NVA0C0_SET_FALCON23_V 31:0 + +#define NVA0C0_SET_FALCON24 0x0560 +#define NVA0C0_SET_FALCON24_V 31:0 + +#define NVA0C0_SET_FALCON25 0x0564 +#define NVA0C0_SET_FALCON25_V 31:0 + +#define NVA0C0_SET_FALCON26 0x0568 +#define NVA0C0_SET_FALCON26_V 31:0 + +#define NVA0C0_SET_FALCON27 0x056c +#define NVA0C0_SET_FALCON27_V 31:0 + +#define NVA0C0_SET_FALCON28 0x0570 +#define NVA0C0_SET_FALCON28_V 31:0 + +#define NVA0C0_SET_FALCON29 0x0574 +#define NVA0C0_SET_FALCON29_V 31:0 + +#define NVA0C0_SET_FALCON30 0x0578 +#define NVA0C0_SET_FALCON30_V 31:0 + +#define NVA0C0_SET_FALCON31 0x057c +#define NVA0C0_SET_FALCON31_V 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA0C0_SET_SPARE_NOOP12 0x0f44 +#define NVA0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP13 0x0f48 +#define NVA0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP14 0x0f4c +#define NVA0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP15 0x0f50 +#define NVA0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP00 0x1040 +#define NVA0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP01 0x1044 +#define NVA0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP02 0x1048 +#define NVA0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP03 0x104c +#define NVA0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP04 0x1050 +#define NVA0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP05 0x1054 +#define NVA0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP06 0x1058 +#define NVA0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP07 0x105c +#define NVA0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP08 0x1060 +#define NVA0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP09 0x1064 +#define NVA0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP10 0x1068 +#define NVA0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP11 0x106c +#define NVA0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVA0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVA0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVA0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVA0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_PROGRAM_REGION_B 0x160c +#define NVA0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_SET_SHADER_CONTROL 0x1690 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 + +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA0C0_PIPE_NOP 0x1a2c +#define NVA0C0_PIPE_NOP_V 31:0 + +#define NVA0C0_SET_SPARE00 0x1a30 +#define NVA0C0_SET_SPARE00_V 31:0 + +#define NVA0C0_SET_SPARE01 0x1a34 +#define NVA0C0_SET_SPARE01_V 31:0 + +#define NVA0C0_SET_SPARE02 0x1a38 +#define NVA0C0_SET_SPARE02_V 31:0 + +#define NVA0C0_SET_SPARE03 0x1a3c +#define NVA0C0_SET_SPARE03_V 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVA0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVA0C0_SET_TRAP_HANDLER 0x260c +#define NVA0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_kepler_compute_a_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cla0c0qmd.h b/src/nouveau/nvidia-headers/classes/cla0c0qmd.h new file mode 100644 index 0000000..c0829f1 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cla0c0qmd.h @@ -0,0 +1,660 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLA0C0QMD_H__ +#define __CLA0C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVA0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVA0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVA0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVA0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVA0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVA0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_06 + */ + +#define NVA0C0_QMDV01_06_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_06_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_06_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_06_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_06_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_06_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_06_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_06_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_06_SCHEDULER_NEXT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_06_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A MW(199:198) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(200:200) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_B MW(207:205) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_ADDR MW(222:208) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID MW(223:223) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA MW(535:512) +#define NVA0C0_QMDV01_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE MW(543:543) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_06_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_06_HW_ONLY_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(1599:1599) +#define NVA0C0_QMDV01_06_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(1606:1600) +#define NVA0C0_QMDV01_06_QMD_RESERVED_Q MW(1609:1607) +#define NVA0C0_QMDV01_06_COALESCE_WAITING_PERIOD MW(1617:1610) +#define NVA0C0_QMDV01_06_QMD_RESERVED_R MW(1631:1618) +#define NVA0C0_QMDV01_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV01_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVA0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A MW(200:198) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVA0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVA0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVA0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLA0C0QMD_H__ diff --git a/src/nouveau/nvidia-headers/classes/cla1c0.h b/src/nouveau/nvidia-headers/classes/cla1c0.h new file mode 100644 index 0000000..cc46f59 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cla1c0.h @@ -0,0 +1,668 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_kepler_compute_b_h_ +#define _cl_kepler_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_compute_b */ + +#include "nvtypes.h" + +#define KEPLER_COMPUTE_B 0xA1C0 + +#define NVA1C0_SET_OBJECT 0x0000 +#define NVA1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVA1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA1C0_NO_OPERATION 0x0100 +#define NVA1C0_NO_OPERATION_V 31:0 + +#define NVA1C0_SET_NOTIFY_A 0x0104 +#define NVA1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_NOTIFY_B 0x0108 +#define NVA1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_NOTIFY 0x010c +#define NVA1C0_NOTIFY_TYPE 31:0 +#define NVA1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA1C0_WAIT_FOR_IDLE 0x0110 +#define NVA1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA1C0_SEND_GO_IDLE 0x013c +#define NVA1C0_SEND_GO_IDLE_V 31:0 + +#define NVA1C0_PM_TRIGGER 0x0140 +#define NVA1C0_PM_TRIGGER_V 31:0 + +#define NVA1C0_PM_TRIGGER_WFI 0x0144 +#define NVA1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA1C0_LINE_LENGTH_IN 0x0180 +#define NVA1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA1C0_LINE_COUNT 0x0184 +#define NVA1C0_LINE_COUNT_VALUE 31:0 + +#define NVA1C0_OFFSET_OUT_UPPER 0x0188 +#define NVA1C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA1C0_OFFSET_OUT 0x018c +#define NVA1C0_OFFSET_OUT_VALUE 31:0 + +#define NVA1C0_PITCH_OUT 0x0190 +#define NVA1C0_PITCH_OUT_VALUE 31:0 + +#define NVA1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA1C0_SET_DST_WIDTH 0x0198 +#define NVA1C0_SET_DST_WIDTH_V 31:0 + +#define NVA1C0_SET_DST_HEIGHT 0x019c +#define NVA1C0_SET_DST_HEIGHT_V 31:0 + +#define NVA1C0_SET_DST_DEPTH 0x01a0 +#define NVA1C0_SET_DST_DEPTH_V 31:0 + +#define NVA1C0_SET_DST_LAYER 0x01a4 +#define NVA1C0_SET_DST_LAYER_V 31:0 + +#define NVA1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA1C0_LAUNCH_DMA 0x01b0 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA1C0_LOAD_INLINE_DATA 0x01b4 +#define NVA1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVA1C0_PERFMON_TRANSFER 0x0210 +#define NVA1C0_PERFMON_TRANSFER_V 31:0 + +#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA1C0_SET_CWD_CONTROL 0x0240 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVA1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVA1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVA1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVA1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_SET_QMD_VERSION 0x0288 +#define NVA1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVA1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_CHECK_QMD_VERSION 0x0290 +#define NVA1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVA1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVA1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVA1C0_SEND_PCAS_A 0x02b4 +#define NVA1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVA1C0_SEND_PCAS_B 0x02b8 +#define NVA1C0_SEND_PCAS_B_FROM 23:0 +#define NVA1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVA1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE 0x02c4 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE 0:0 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX 23:4 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA1C0_SET_SPA_VERSION 0x0310 +#define NVA1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVA1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA1C0_SET_FALCON00 0x0500 +#define NVA1C0_SET_FALCON00_V 31:0 + +#define NVA1C0_SET_FALCON01 0x0504 +#define NVA1C0_SET_FALCON01_V 31:0 + +#define NVA1C0_SET_FALCON02 0x0508 +#define NVA1C0_SET_FALCON02_V 31:0 + +#define NVA1C0_SET_FALCON03 0x050c +#define NVA1C0_SET_FALCON03_V 31:0 + +#define NVA1C0_SET_FALCON04 0x0510 +#define NVA1C0_SET_FALCON04_V 31:0 + +#define NVA1C0_SET_FALCON05 0x0514 +#define NVA1C0_SET_FALCON05_V 31:0 + +#define NVA1C0_SET_FALCON06 0x0518 +#define NVA1C0_SET_FALCON06_V 31:0 + +#define NVA1C0_SET_FALCON07 0x051c +#define NVA1C0_SET_FALCON07_V 31:0 + +#define NVA1C0_SET_FALCON08 0x0520 +#define NVA1C0_SET_FALCON08_V 31:0 + +#define NVA1C0_SET_FALCON09 0x0524 +#define NVA1C0_SET_FALCON09_V 31:0 + +#define NVA1C0_SET_FALCON10 0x0528 +#define NVA1C0_SET_FALCON10_V 31:0 + +#define NVA1C0_SET_FALCON11 0x052c +#define NVA1C0_SET_FALCON11_V 31:0 + +#define NVA1C0_SET_FALCON12 0x0530 +#define NVA1C0_SET_FALCON12_V 31:0 + +#define NVA1C0_SET_FALCON13 0x0534 +#define NVA1C0_SET_FALCON13_V 31:0 + +#define NVA1C0_SET_FALCON14 0x0538 +#define NVA1C0_SET_FALCON14_V 31:0 + +#define NVA1C0_SET_FALCON15 0x053c +#define NVA1C0_SET_FALCON15_V 31:0 + +#define NVA1C0_SET_FALCON16 0x0540 +#define NVA1C0_SET_FALCON16_V 31:0 + +#define NVA1C0_SET_FALCON17 0x0544 +#define NVA1C0_SET_FALCON17_V 31:0 + +#define NVA1C0_SET_FALCON18 0x0548 +#define NVA1C0_SET_FALCON18_V 31:0 + +#define NVA1C0_SET_FALCON19 0x054c +#define NVA1C0_SET_FALCON19_V 31:0 + +#define NVA1C0_SET_FALCON20 0x0550 +#define NVA1C0_SET_FALCON20_V 31:0 + +#define NVA1C0_SET_FALCON21 0x0554 +#define NVA1C0_SET_FALCON21_V 31:0 + +#define NVA1C0_SET_FALCON22 0x0558 +#define NVA1C0_SET_FALCON22_V 31:0 + +#define NVA1C0_SET_FALCON23 0x055c +#define NVA1C0_SET_FALCON23_V 31:0 + +#define NVA1C0_SET_FALCON24 0x0560 +#define NVA1C0_SET_FALCON24_V 31:0 + +#define NVA1C0_SET_FALCON25 0x0564 +#define NVA1C0_SET_FALCON25_V 31:0 + +#define NVA1C0_SET_FALCON26 0x0568 +#define NVA1C0_SET_FALCON26_V 31:0 + +#define NVA1C0_SET_FALCON27 0x056c +#define NVA1C0_SET_FALCON27_V 31:0 + +#define NVA1C0_SET_FALCON28 0x0570 +#define NVA1C0_SET_FALCON28_V 31:0 + +#define NVA1C0_SET_FALCON29 0x0574 +#define NVA1C0_SET_FALCON29_V 31:0 + +#define NVA1C0_SET_FALCON30 0x0578 +#define NVA1C0_SET_FALCON30_V 31:0 + +#define NVA1C0_SET_FALCON31 0x057c +#define NVA1C0_SET_FALCON31_V 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA1C0_SET_SPARE_NOOP12 0x0f44 +#define NVA1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP13 0x0f48 +#define NVA1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP14 0x0f4c +#define NVA1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP15 0x0f50 +#define NVA1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP00 0x1040 +#define NVA1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP01 0x1044 +#define NVA1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP02 0x1048 +#define NVA1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP03 0x104c +#define NVA1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP04 0x1050 +#define NVA1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP05 0x1054 +#define NVA1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP06 0x1058 +#define NVA1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP07 0x105c +#define NVA1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP08 0x1060 +#define NVA1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP09 0x1064 +#define NVA1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP10 0x1068 +#define NVA1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP11 0x106c +#define NVA1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVA1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVA1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVA1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVA1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVA1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_PROGRAM_REGION_B 0x160c +#define NVA1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_SHADER_CONTROL 0x1690 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 + +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA1C0_PIPE_NOP 0x1a2c +#define NVA1C0_PIPE_NOP_V 31:0 + +#define NVA1C0_SET_SPARE00 0x1a30 +#define NVA1C0_SET_SPARE00_V 31:0 + +#define NVA1C0_SET_SPARE01 0x1a34 +#define NVA1C0_SET_SPARE01_V 31:0 + +#define NVA1C0_SET_SPARE02 0x1a38 +#define NVA1C0_SET_SPARE02_V 31:0 + +#define NVA1C0_SET_SPARE03 0x1a3c +#define NVA1C0_SET_SPARE03_V 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVA1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVA1C0_SET_TRAP_HANDLER 0x260c +#define NVA1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_kepler_compute_b_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/cla1c0qmd.h b/src/nouveau/nvidia-headers/classes/cla1c0qmd.h new file mode 100644 index 0000000..b322988 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/cla1c0qmd.h @@ -0,0 +1,451 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLA1C0QMD_H__ +#define __CLA1C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVA1C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVA1C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVA1C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVA1C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVA1C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_THROTTLED MW(372:372) +#define NVA1C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVA1C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA1C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVA1C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA1C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVA1C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA1C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA1C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA1C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA1C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA1C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVA1C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA1C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVA1C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVA1C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA1C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVA1C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVA1C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA1C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA1C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA1C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA1C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA1C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA1C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVA1C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA1C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA1C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVA1C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVA1C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVA1C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVA1C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVA1C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVA1C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVA1C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVA1C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVA1C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVA1C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVA1C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVA1C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVA1C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVA1C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVA1C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA1C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVA1C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVA1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVA1C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVA1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA1C0_QMDV01_07_INNER_GET MW(94:64) +#define NVA1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVA1C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVA1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVA1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVA1C0_QMDV01_07_QMD_RESERVED_A MW(199:198) +#define NVA1C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVA1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_THROTTLED MW(372:372) +#define NVA1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVA1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVA1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVA1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVA1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVA1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVA1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVA1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVA1C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVA1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVA1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVA1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVA1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVA1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA1C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVA1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA1C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVA1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVA1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVA1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVA1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVA1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVA1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVA1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVA1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVA1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVA1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVA1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVA1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVA1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLA1C0QMD_H__ diff --git a/src/nouveau/nvidia-headers/classes/clb0b5.h b/src/nouveau/nvidia-headers/classes/clb0b5.h new file mode 100644 index 0000000..63fe695 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clb0b5.h @@ -0,0 +1,261 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clb0b5_h_ +#define _clb0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAXWELL_DMA_COPY_A (0x0000B0B5) + +#define NVB0B5_NOP (0x00000100) +#define NVB0B5_NOP_PARAMETER 31:0 +#define NVB0B5_PM_TRIGGER (0x00000140) +#define NVB0B5_PM_TRIGGER_V 31:0 +#define NVB0B5_SET_SEMAPHORE_A (0x00000240) +#define NVB0B5_SET_SEMAPHORE_A_UPPER 7:0 +#define NVB0B5_SET_SEMAPHORE_B (0x00000244) +#define NVB0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVB0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVB0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVB0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVB0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVB0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVB0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVB0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVB0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVB0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVB0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVB0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVB0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVB0B5_LAUNCH_DMA (0x00000300) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVB0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVB0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVB0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVB0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVB0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVB0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVB0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVB0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVB0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVB0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVB0B5_LAUNCH_DMA_BYPASS_L2 20:20 +#define NVB0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVB0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVB0B5_OFFSET_IN_UPPER (0x00000400) +#define NVB0B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NVB0B5_OFFSET_IN_LOWER (0x00000404) +#define NVB0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVB0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVB0B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NVB0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVB0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVB0B5_PITCH_IN (0x00000410) +#define NVB0B5_PITCH_IN_VALUE 31:0 +#define NVB0B5_PITCH_OUT (0x00000414) +#define NVB0B5_PITCH_OUT_VALUE 31:0 +#define NVB0B5_LINE_LENGTH_IN (0x00000418) +#define NVB0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVB0B5_LINE_COUNT (0x0000041C) +#define NVB0B5_LINE_COUNT_VALUE 31:0 +#define NVB0B5_SET_REMAP_CONST_A (0x00000700) +#define NVB0B5_SET_REMAP_CONST_A_V 31:0 +#define NVB0B5_SET_REMAP_CONST_B (0x00000704) +#define NVB0B5_SET_REMAP_CONST_B_V 31:0 +#define NVB0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVB0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVB0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_DST_WIDTH (0x00000710) +#define NVB0B5_SET_DST_WIDTH_V 31:0 +#define NVB0B5_SET_DST_HEIGHT (0x00000714) +#define NVB0B5_SET_DST_HEIGHT_V 31:0 +#define NVB0B5_SET_DST_DEPTH (0x00000718) +#define NVB0B5_SET_DST_DEPTH_V 31:0 +#define NVB0B5_SET_DST_LAYER (0x0000071C) +#define NVB0B5_SET_DST_LAYER_V 31:0 +#define NVB0B5_SET_DST_ORIGIN (0x00000720) +#define NVB0B5_SET_DST_ORIGIN_X 15:0 +#define NVB0B5_SET_DST_ORIGIN_Y 31:16 +#define NVB0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) +#define NVB0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVB0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) +#define NVB0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVB0B5_SET_SRC_WIDTH (0x0000072C) +#define NVB0B5_SET_SRC_WIDTH_V 31:0 +#define NVB0B5_SET_SRC_HEIGHT (0x00000730) +#define NVB0B5_SET_SRC_HEIGHT_V 31:0 +#define NVB0B5_SET_SRC_DEPTH (0x00000734) +#define NVB0B5_SET_SRC_DEPTH_V 31:0 +#define NVB0B5_SET_SRC_LAYER (0x00000738) +#define NVB0B5_SET_SRC_LAYER_V 31:0 +#define NVB0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVB0B5_SET_SRC_ORIGIN_X 15:0 +#define NVB0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVB0B5_PM_TRIGGER_END (0x00001114) +#define NVB0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clb0b5_h + diff --git a/src/nouveau/nvidia-headers/classes/clb0c0.h b/src/nouveau/nvidia-headers/classes/clb0c0.h new file mode 100644 index 0000000..9b546e7 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clb0c0.h @@ -0,0 +1,719 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_maxwell_compute_a_h_ +#define _cl_maxwell_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_a */ + +#include "nvtypes.h" + +#define MAXWELL_COMPUTE_A 0xB0C0 + +#define NVB0C0_SET_OBJECT 0x0000 +#define NVB0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVB0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB0C0_NO_OPERATION 0x0100 +#define NVB0C0_NO_OPERATION_V 31:0 + +#define NVB0C0_SET_NOTIFY_A 0x0104 +#define NVB0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_NOTIFY_B 0x0108 +#define NVB0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_NOTIFY 0x010c +#define NVB0C0_NOTIFY_TYPE 31:0 +#define NVB0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB0C0_WAIT_FOR_IDLE 0x0110 +#define NVB0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB0C0_SEND_GO_IDLE 0x013c +#define NVB0C0_SEND_GO_IDLE_V 31:0 + +#define NVB0C0_PM_TRIGGER 0x0140 +#define NVB0C0_PM_TRIGGER_V 31:0 + +#define NVB0C0_PM_TRIGGER_WFI 0x0144 +#define NVB0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB0C0_LINE_LENGTH_IN 0x0180 +#define NVB0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB0C0_LINE_COUNT 0x0184 +#define NVB0C0_LINE_COUNT_VALUE 31:0 + +#define NVB0C0_OFFSET_OUT_UPPER 0x0188 +#define NVB0C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB0C0_OFFSET_OUT 0x018c +#define NVB0C0_OFFSET_OUT_VALUE 31:0 + +#define NVB0C0_PITCH_OUT 0x0190 +#define NVB0C0_PITCH_OUT_VALUE 31:0 + +#define NVB0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB0C0_SET_DST_WIDTH 0x0198 +#define NVB0C0_SET_DST_WIDTH_V 31:0 + +#define NVB0C0_SET_DST_HEIGHT 0x019c +#define NVB0C0_SET_DST_HEIGHT_V 31:0 + +#define NVB0C0_SET_DST_DEPTH 0x01a0 +#define NVB0C0_SET_DST_DEPTH_V 31:0 + +#define NVB0C0_SET_DST_LAYER 0x01a4 +#define NVB0C0_SET_DST_LAYER_V 31:0 + +#define NVB0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB0C0_LAUNCH_DMA 0x01b0 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB0C0_LOAD_INLINE_DATA 0x01b4 +#define NVB0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVB0C0_PERFMON_TRANSFER 0x0210 +#define NVB0C0_PERFMON_TRANSFER_V 31:0 + +#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB0C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVB0C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVB0C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVB0C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVB0C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVB0C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVB0C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVB0C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVB0C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB0C0_SET_CWD_CONTROL 0x0240 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVB0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVB0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVB0C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVB0C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVB0C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVB0C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVB0C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVB0C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVB0C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVB0C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVB0C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVB0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVB0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_SET_QMD_VERSION 0x0288 +#define NVB0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVB0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_CHECK_QMD_VERSION 0x0290 +#define NVB0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVB0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVB0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVB0C0_SEND_PCAS_A 0x02b4 +#define NVB0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVB0C0_SEND_PCAS_B 0x02b8 +#define NVB0C0_SEND_PCAS_B_FROM 23:0 +#define NVB0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVB0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB0C0_SET_SPA_VERSION 0x0310 +#define NVB0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVB0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB0C0_SET_FALCON00 0x0500 +#define NVB0C0_SET_FALCON00_V 31:0 + +#define NVB0C0_SET_FALCON01 0x0504 +#define NVB0C0_SET_FALCON01_V 31:0 + +#define NVB0C0_SET_FALCON02 0x0508 +#define NVB0C0_SET_FALCON02_V 31:0 + +#define NVB0C0_SET_FALCON03 0x050c +#define NVB0C0_SET_FALCON03_V 31:0 + +#define NVB0C0_SET_FALCON04 0x0510 +#define NVB0C0_SET_FALCON04_V 31:0 + +#define NVB0C0_SET_FALCON05 0x0514 +#define NVB0C0_SET_FALCON05_V 31:0 + +#define NVB0C0_SET_FALCON06 0x0518 +#define NVB0C0_SET_FALCON06_V 31:0 + +#define NVB0C0_SET_FALCON07 0x051c +#define NVB0C0_SET_FALCON07_V 31:0 + +#define NVB0C0_SET_FALCON08 0x0520 +#define NVB0C0_SET_FALCON08_V 31:0 + +#define NVB0C0_SET_FALCON09 0x0524 +#define NVB0C0_SET_FALCON09_V 31:0 + +#define NVB0C0_SET_FALCON10 0x0528 +#define NVB0C0_SET_FALCON10_V 31:0 + +#define NVB0C0_SET_FALCON11 0x052c +#define NVB0C0_SET_FALCON11_V 31:0 + +#define NVB0C0_SET_FALCON12 0x0530 +#define NVB0C0_SET_FALCON12_V 31:0 + +#define NVB0C0_SET_FALCON13 0x0534 +#define NVB0C0_SET_FALCON13_V 31:0 + +#define NVB0C0_SET_FALCON14 0x0538 +#define NVB0C0_SET_FALCON14_V 31:0 + +#define NVB0C0_SET_FALCON15 0x053c +#define NVB0C0_SET_FALCON15_V 31:0 + +#define NVB0C0_SET_FALCON16 0x0540 +#define NVB0C0_SET_FALCON16_V 31:0 + +#define NVB0C0_SET_FALCON17 0x0544 +#define NVB0C0_SET_FALCON17_V 31:0 + +#define NVB0C0_SET_FALCON18 0x0548 +#define NVB0C0_SET_FALCON18_V 31:0 + +#define NVB0C0_SET_FALCON19 0x054c +#define NVB0C0_SET_FALCON19_V 31:0 + +#define NVB0C0_SET_FALCON20 0x0550 +#define NVB0C0_SET_FALCON20_V 31:0 + +#define NVB0C0_SET_FALCON21 0x0554 +#define NVB0C0_SET_FALCON21_V 31:0 + +#define NVB0C0_SET_FALCON22 0x0558 +#define NVB0C0_SET_FALCON22_V 31:0 + +#define NVB0C0_SET_FALCON23 0x055c +#define NVB0C0_SET_FALCON23_V 31:0 + +#define NVB0C0_SET_FALCON24 0x0560 +#define NVB0C0_SET_FALCON24_V 31:0 + +#define NVB0C0_SET_FALCON25 0x0564 +#define NVB0C0_SET_FALCON25_V 31:0 + +#define NVB0C0_SET_FALCON26 0x0568 +#define NVB0C0_SET_FALCON26_V 31:0 + +#define NVB0C0_SET_FALCON27 0x056c +#define NVB0C0_SET_FALCON27_V 31:0 + +#define NVB0C0_SET_FALCON28 0x0570 +#define NVB0C0_SET_FALCON28_V 31:0 + +#define NVB0C0_SET_FALCON29 0x0574 +#define NVB0C0_SET_FALCON29_V 31:0 + +#define NVB0C0_SET_FALCON30 0x0578 +#define NVB0C0_SET_FALCON30_V 31:0 + +#define NVB0C0_SET_FALCON31 0x057c +#define NVB0C0_SET_FALCON31_V 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB0C0_SET_SPARE_NOOP12 0x0f44 +#define NVB0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP13 0x0f48 +#define NVB0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP14 0x0f4c +#define NVB0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP15 0x0f50 +#define NVB0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP00 0x1040 +#define NVB0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP01 0x1044 +#define NVB0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP02 0x1048 +#define NVB0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP03 0x104c +#define NVB0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP04 0x1050 +#define NVB0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP05 0x1054 +#define NVB0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP06 0x1058 +#define NVB0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP07 0x105c +#define NVB0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP08 0x1060 +#define NVB0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP09 0x1064 +#define NVB0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP10 0x1068 +#define NVB0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP11 0x106c +#define NVB0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVB0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVB0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVB0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVB0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVB0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_PROGRAM_REGION_B 0x160c +#define NVB0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB0C0_PIPE_NOP 0x1a2c +#define NVB0C0_PIPE_NOP_V 31:0 + +#define NVB0C0_SET_SPARE00 0x1a30 +#define NVB0C0_SET_SPARE00_V 31:0 + +#define NVB0C0_SET_SPARE01 0x1a34 +#define NVB0C0_SET_SPARE01_V 31:0 + +#define NVB0C0_SET_SPARE02 0x1a38 +#define NVB0C0_SET_SPARE02_V 31:0 + +#define NVB0C0_SET_SPARE03 0x1a3c +#define NVB0C0_SET_SPARE03_V 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVB0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVB0C0_SET_TRAP_HANDLER 0x260c +#define NVB0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_maxwell_compute_a_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/clb0c0qmd.h b/src/nouveau/nvidia-headers/classes/clb0c0qmd.h new file mode 100644 index 0000000..c68e893 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clb0c0qmd.h @@ -0,0 +1,454 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLB0C0QMD_H__ +#define __CLB0C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVB0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVB0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVB0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVB0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVB0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_THROTTLED MW(372:372) +#define NVB0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVB0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVB0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVB0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVB0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVB0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVB0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVB0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVB0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVB0C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVB0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVB0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVB0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVB0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVB0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVB0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB0C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVB0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVB0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVB0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVB0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVB0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVB0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVB0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVB0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVB0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVB0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVB0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVB0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVB0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVB0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVB0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVB0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVB0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVB0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVB0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVB0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVB0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVB0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVB0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVB0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVB0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVB0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVB0C0_QMDV01_07_QMD_RESERVED_A MW(198:198) +#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVB0C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVB0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVB0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVB0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVB0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVB0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVB0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVB0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVB0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVB0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVB0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVB0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVB0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVB0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVB0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVB0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVB0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVB0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVB0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVB0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVB0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVB0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVB0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVB0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVB0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVB0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVB0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVB0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVB0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVB0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVB0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVB0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVB0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVB0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVB0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVB0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVB0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLB0C0QMD_H__ diff --git a/src/nouveau/nvidia-headers/classes/clb1c0.h b/src/nouveau/nvidia-headers/classes/clb1c0.h new file mode 100644 index 0000000..fcbc33b --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clb1c0.h @@ -0,0 +1,749 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_maxwell_compute_b_h_ +#define _cl_maxwell_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_b */ + +#include "nvtypes.h" + +#define MAXWELL_COMPUTE_B 0xB1C0 + +#define NVB1C0_SET_OBJECT 0x0000 +#define NVB1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVB1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB1C0_NO_OPERATION 0x0100 +#define NVB1C0_NO_OPERATION_V 31:0 + +#define NVB1C0_SET_NOTIFY_A 0x0104 +#define NVB1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_NOTIFY_B 0x0108 +#define NVB1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_NOTIFY 0x010c +#define NVB1C0_NOTIFY_TYPE 31:0 +#define NVB1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB1C0_WAIT_FOR_IDLE 0x0110 +#define NVB1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB1C0_SEND_GO_IDLE 0x013c +#define NVB1C0_SEND_GO_IDLE_V 31:0 + +#define NVB1C0_PM_TRIGGER 0x0140 +#define NVB1C0_PM_TRIGGER_V 31:0 + +#define NVB1C0_PM_TRIGGER_WFI 0x0144 +#define NVB1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB1C0_LINE_LENGTH_IN 0x0180 +#define NVB1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB1C0_LINE_COUNT 0x0184 +#define NVB1C0_LINE_COUNT_VALUE 31:0 + +#define NVB1C0_OFFSET_OUT_UPPER 0x0188 +#define NVB1C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB1C0_OFFSET_OUT 0x018c +#define NVB1C0_OFFSET_OUT_VALUE 31:0 + +#define NVB1C0_PITCH_OUT 0x0190 +#define NVB1C0_PITCH_OUT_VALUE 31:0 + +#define NVB1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB1C0_SET_DST_WIDTH 0x0198 +#define NVB1C0_SET_DST_WIDTH_V 31:0 + +#define NVB1C0_SET_DST_HEIGHT 0x019c +#define NVB1C0_SET_DST_HEIGHT_V 31:0 + +#define NVB1C0_SET_DST_DEPTH 0x01a0 +#define NVB1C0_SET_DST_DEPTH_V 31:0 + +#define NVB1C0_SET_DST_LAYER 0x01a4 +#define NVB1C0_SET_DST_LAYER_V 31:0 + +#define NVB1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB1C0_LAUNCH_DMA 0x01b0 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB1C0_LOAD_INLINE_DATA 0x01b4 +#define NVB1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVB1C0_PERFMON_TRANSFER 0x0210 +#define NVB1C0_PERFMON_TRANSFER_V 31:0 + +#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB1C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVB1C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVB1C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVB1C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVB1C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVB1C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVB1C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVB1C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVB1C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB1C0_SET_CWD_CONTROL 0x0240 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVB1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVB1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVB1C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVB1C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVB1C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVB1C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVB1C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVB1C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVB1C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVB1C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVB1C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB1C0_SET_GWC_SCG_TYPE 0x026c +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVB1C0_SET_SCG_CONTROL 0x0270 +#define NVB1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVB1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVB1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_SET_QMD_VERSION 0x0288 +#define NVB1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVB1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_SET_WFI_CONFIG 0x028c +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVB1C0_CHECK_QMD_VERSION 0x0290 +#define NVB1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVB1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVB1C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVB1C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVB1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVB1C0_SEND_PCAS_A 0x02b4 +#define NVB1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVB1C0_SEND_PCAS_B 0x02b8 +#define NVB1C0_SEND_PCAS_B_FROM 23:0 +#define NVB1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVB1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB1C0_SET_SPA_VERSION 0x0310 +#define NVB1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVB1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB1C0_SET_FALCON00 0x0500 +#define NVB1C0_SET_FALCON00_V 31:0 + +#define NVB1C0_SET_FALCON01 0x0504 +#define NVB1C0_SET_FALCON01_V 31:0 + +#define NVB1C0_SET_FALCON02 0x0508 +#define NVB1C0_SET_FALCON02_V 31:0 + +#define NVB1C0_SET_FALCON03 0x050c +#define NVB1C0_SET_FALCON03_V 31:0 + +#define NVB1C0_SET_FALCON04 0x0510 +#define NVB1C0_SET_FALCON04_V 31:0 + +#define NVB1C0_SET_FALCON05 0x0514 +#define NVB1C0_SET_FALCON05_V 31:0 + +#define NVB1C0_SET_FALCON06 0x0518 +#define NVB1C0_SET_FALCON06_V 31:0 + +#define NVB1C0_SET_FALCON07 0x051c +#define NVB1C0_SET_FALCON07_V 31:0 + +#define NVB1C0_SET_FALCON08 0x0520 +#define NVB1C0_SET_FALCON08_V 31:0 + +#define NVB1C0_SET_FALCON09 0x0524 +#define NVB1C0_SET_FALCON09_V 31:0 + +#define NVB1C0_SET_FALCON10 0x0528 +#define NVB1C0_SET_FALCON10_V 31:0 + +#define NVB1C0_SET_FALCON11 0x052c +#define NVB1C0_SET_FALCON11_V 31:0 + +#define NVB1C0_SET_FALCON12 0x0530 +#define NVB1C0_SET_FALCON12_V 31:0 + +#define NVB1C0_SET_FALCON13 0x0534 +#define NVB1C0_SET_FALCON13_V 31:0 + +#define NVB1C0_SET_FALCON14 0x0538 +#define NVB1C0_SET_FALCON14_V 31:0 + +#define NVB1C0_SET_FALCON15 0x053c +#define NVB1C0_SET_FALCON15_V 31:0 + +#define NVB1C0_SET_FALCON16 0x0540 +#define NVB1C0_SET_FALCON16_V 31:0 + +#define NVB1C0_SET_FALCON17 0x0544 +#define NVB1C0_SET_FALCON17_V 31:0 + +#define NVB1C0_SET_FALCON18 0x0548 +#define NVB1C0_SET_FALCON18_V 31:0 + +#define NVB1C0_SET_FALCON19 0x054c +#define NVB1C0_SET_FALCON19_V 31:0 + +#define NVB1C0_SET_FALCON20 0x0550 +#define NVB1C0_SET_FALCON20_V 31:0 + +#define NVB1C0_SET_FALCON21 0x0554 +#define NVB1C0_SET_FALCON21_V 31:0 + +#define NVB1C0_SET_FALCON22 0x0558 +#define NVB1C0_SET_FALCON22_V 31:0 + +#define NVB1C0_SET_FALCON23 0x055c +#define NVB1C0_SET_FALCON23_V 31:0 + +#define NVB1C0_SET_FALCON24 0x0560 +#define NVB1C0_SET_FALCON24_V 31:0 + +#define NVB1C0_SET_FALCON25 0x0564 +#define NVB1C0_SET_FALCON25_V 31:0 + +#define NVB1C0_SET_FALCON26 0x0568 +#define NVB1C0_SET_FALCON26_V 31:0 + +#define NVB1C0_SET_FALCON27 0x056c +#define NVB1C0_SET_FALCON27_V 31:0 + +#define NVB1C0_SET_FALCON28 0x0570 +#define NVB1C0_SET_FALCON28_V 31:0 + +#define NVB1C0_SET_FALCON29 0x0574 +#define NVB1C0_SET_FALCON29_V 31:0 + +#define NVB1C0_SET_FALCON30 0x0578 +#define NVB1C0_SET_FALCON30_V 31:0 + +#define NVB1C0_SET_FALCON31 0x057c +#define NVB1C0_SET_FALCON31_V 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB1C0_SET_SPARE_NOOP12 0x0f44 +#define NVB1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP13 0x0f48 +#define NVB1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP14 0x0f4c +#define NVB1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP15 0x0f50 +#define NVB1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP00 0x1040 +#define NVB1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP01 0x1044 +#define NVB1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP02 0x1048 +#define NVB1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP03 0x104c +#define NVB1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP04 0x1050 +#define NVB1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP05 0x1054 +#define NVB1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP06 0x1058 +#define NVB1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP07 0x105c +#define NVB1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP08 0x1060 +#define NVB1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP09 0x1064 +#define NVB1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP10 0x1068 +#define NVB1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP11 0x106c +#define NVB1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVB1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVB1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVB1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVB1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_PROGRAM_REGION_B 0x160c +#define NVB1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB1C0_PIPE_NOP 0x1a2c +#define NVB1C0_PIPE_NOP_V 31:0 + +#define NVB1C0_SET_SPARE00 0x1a30 +#define NVB1C0_SET_SPARE00_V 31:0 + +#define NVB1C0_SET_SPARE01 0x1a34 +#define NVB1C0_SET_SPARE01_V 31:0 + +#define NVB1C0_SET_SPARE02 0x1a38 +#define NVB1C0_SET_SPARE02_V 31:0 + +#define NVB1C0_SET_SPARE03 0x1a3c +#define NVB1C0_SET_SPARE03_V 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVB1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVB1C0_SET_TRAP_HANDLER 0x260c +#define NVB1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_maxwell_compute_b_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/clb1c0qmd.h b/src/nouveau/nvidia-headers/classes/clb1c0qmd.h new file mode 100644 index 0000000..ca98206 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clb1c0qmd.h @@ -0,0 +1,454 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLB1C0QMD_H__ +#define __CLB1C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVB1C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVB1C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVB1C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVB1C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVB1C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_THROTTLED MW(372:372) +#define NVB1C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVB1C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB1C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVB1C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB1C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVB1C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVB1C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVB1C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVB1C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB1C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB1C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVB1C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVB1C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVB1C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVB1C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVB1C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVB1C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVB1C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB1C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB1C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVB1C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB1C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB1C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB1C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVB1C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB1C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB1C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVB1C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVB1C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVB1C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVB1C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVB1C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVB1C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVB1C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVB1C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVB1C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVB1C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVB1C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVB1C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVB1C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVB1C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVB1C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVB1C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVB1C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVB1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVB1C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVB1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVB1C0_QMDV01_07_INNER_GET MW(94:64) +#define NVB1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVB1C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVB1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVB1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVB1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVB1C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVB1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVB1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVB1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_THROTTLED MW(372:372) +#define NVB1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVB1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVB1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVB1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVB1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVB1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVB1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVB1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVB1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVB1C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVB1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVB1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVB1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVB1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVB1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVB1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVB1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB1C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVB1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVB1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVB1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVB1C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVB1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVB1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVB1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVB1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVB1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVB1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVB1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVB1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVB1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVB1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVB1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVB1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVB1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLB1C0QMD_H__ diff --git a/src/nouveau/nvidia-headers/classes/clc0b5.h b/src/nouveau/nvidia-headers/classes/clc0b5.h new file mode 100644 index 0000000..d1fa85a --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc0b5.h @@ -0,0 +1,261 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc0b5_h_ +#define _clc0b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PASCAL_DMA_COPY_A (0x0000C0B5) + +#define NVC0B5_NOP (0x00000100) +#define NVC0B5_NOP_PARAMETER 31:0 +#define NVC0B5_PM_TRIGGER (0x00000140) +#define NVC0B5_PM_TRIGGER_V 31:0 +#define NVC0B5_SET_SEMAPHORE_A (0x00000240) +#define NVC0B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC0B5_SET_SEMAPHORE_B (0x00000244) +#define NVC0B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC0B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC0B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC0B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC0B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC0B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC0B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC0B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC0B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC0B5_LAUNCH_DMA (0x00000300) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC0B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC0B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC0B5_LAUNCH_DMA_RESERVED 31:28 +#define NVC0B5_OFFSET_IN_UPPER (0x00000400) +#define NVC0B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC0B5_OFFSET_IN_LOWER (0x00000404) +#define NVC0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC0B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC0B5_PITCH_IN (0x00000410) +#define NVC0B5_PITCH_IN_VALUE 31:0 +#define NVC0B5_PITCH_OUT (0x00000414) +#define NVC0B5_PITCH_OUT_VALUE 31:0 +#define NVC0B5_LINE_LENGTH_IN (0x00000418) +#define NVC0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC0B5_LINE_COUNT (0x0000041C) +#define NVC0B5_LINE_COUNT_VALUE 31:0 +#define NVC0B5_SET_REMAP_CONST_A (0x00000700) +#define NVC0B5_SET_REMAP_CONST_A_V 31:0 +#define NVC0B5_SET_REMAP_CONST_B (0x00000704) +#define NVC0B5_SET_REMAP_CONST_B_V 31:0 +#define NVC0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_DST_WIDTH (0x00000710) +#define NVC0B5_SET_DST_WIDTH_V 31:0 +#define NVC0B5_SET_DST_HEIGHT (0x00000714) +#define NVC0B5_SET_DST_HEIGHT_V 31:0 +#define NVC0B5_SET_DST_DEPTH (0x00000718) +#define NVC0B5_SET_DST_DEPTH_V 31:0 +#define NVC0B5_SET_DST_LAYER (0x0000071C) +#define NVC0B5_SET_DST_LAYER_V 31:0 +#define NVC0B5_SET_DST_ORIGIN (0x00000720) +#define NVC0B5_SET_DST_ORIGIN_X 15:0 +#define NVC0B5_SET_DST_ORIGIN_Y 31:16 +#define NVC0B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC0B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC0B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC0B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC0B5_SET_SRC_WIDTH (0x0000072C) +#define NVC0B5_SET_SRC_WIDTH_V 31:0 +#define NVC0B5_SET_SRC_HEIGHT (0x00000730) +#define NVC0B5_SET_SRC_HEIGHT_V 31:0 +#define NVC0B5_SET_SRC_DEPTH (0x00000734) +#define NVC0B5_SET_SRC_DEPTH_V 31:0 +#define NVC0B5_SET_SRC_LAYER (0x00000738) +#define NVC0B5_SET_SRC_LAYER_V 31:0 +#define NVC0B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC0B5_SET_SRC_ORIGIN_X 15:0 +#define NVC0B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC0B5_PM_TRIGGER_END (0x00001114) +#define NVC0B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc0b5_h + diff --git a/src/nouveau/nvidia-headers/classes/clc0c0.h b/src/nouveau/nvidia-headers/classes/clc0c0.h new file mode 100644 index 0000000..9f03ce4 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc0c0.h @@ -0,0 +1,776 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_pascal_compute_a_h_ +#define _cl_pascal_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_compute_a */ + +#include "nvtypes.h" + +#define PASCAL_COMPUTE_A 0xC0C0 + +#define NVC0C0_SET_OBJECT 0x0000 +#define NVC0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC0C0_NO_OPERATION 0x0100 +#define NVC0C0_NO_OPERATION_V 31:0 + +#define NVC0C0_SET_NOTIFY_A 0x0104 +#define NVC0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC0C0_SET_NOTIFY_B 0x0108 +#define NVC0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_NOTIFY 0x010c +#define NVC0C0_NOTIFY_TYPE 31:0 +#define NVC0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC0C0_WAIT_FOR_IDLE 0x0110 +#define NVC0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC0C0_SEND_GO_IDLE 0x013c +#define NVC0C0_SEND_GO_IDLE_V 31:0 + +#define NVC0C0_PM_TRIGGER 0x0140 +#define NVC0C0_PM_TRIGGER_V 31:0 + +#define NVC0C0_PM_TRIGGER_WFI 0x0144 +#define NVC0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC0C0_LINE_LENGTH_IN 0x0180 +#define NVC0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC0C0_LINE_COUNT 0x0184 +#define NVC0C0_LINE_COUNT_VALUE 31:0 + +#define NVC0C0_OFFSET_OUT_UPPER 0x0188 +#define NVC0C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC0C0_OFFSET_OUT 0x018c +#define NVC0C0_OFFSET_OUT_VALUE 31:0 + +#define NVC0C0_PITCH_OUT 0x0190 +#define NVC0C0_PITCH_OUT_VALUE 31:0 + +#define NVC0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC0C0_SET_DST_WIDTH 0x0198 +#define NVC0C0_SET_DST_WIDTH_V 31:0 + +#define NVC0C0_SET_DST_HEIGHT 0x019c +#define NVC0C0_SET_DST_HEIGHT_V 31:0 + +#define NVC0C0_SET_DST_DEPTH 0x01a0 +#define NVC0C0_SET_DST_DEPTH_V 31:0 + +#define NVC0C0_SET_DST_LAYER 0x01a4 +#define NVC0C0_SET_DST_LAYER_V 31:0 + +#define NVC0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC0C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC0C0_LAUNCH_DMA 0x01b0 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC0C0_LOAD_INLINE_DATA 0x01b4 +#define NVC0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVC0C0_PERFMON_TRANSFER 0x0210 +#define NVC0C0_PERFMON_TRANSFER_V 31:0 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC0C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC0C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC0C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC0C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC0C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC0C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC0C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC0C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC0C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC0C0_SET_CWD_CONTROL 0x0240 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC0C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC0C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC0C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC0C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC0C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC0C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC0C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC0C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC0C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC0C0_SET_GWC_SCG_TYPE 0x026c +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVC0C0_SET_SCG_CONTROL 0x0270 +#define NVC0C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVC0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_SET_QMD_VERSION 0x0288 +#define NVC0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_SET_WFI_CONFIG 0x028c +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVC0C0_CHECK_QMD_VERSION 0x0290 +#define NVC0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVC0C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC0C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC0C0_SEND_PCAS_A 0x02b4 +#define NVC0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC0C0_SEND_PCAS_B 0x02b8 +#define NVC0C0_SEND_PCAS_B_FROM 23:0 +#define NVC0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC0C0_SET_SPA_VERSION 0x0310 +#define NVC0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC0C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC0C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC0C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC0C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC0C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC0C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC0C0_SET_FALCON00 0x0500 +#define NVC0C0_SET_FALCON00_V 31:0 + +#define NVC0C0_SET_FALCON01 0x0504 +#define NVC0C0_SET_FALCON01_V 31:0 + +#define NVC0C0_SET_FALCON02 0x0508 +#define NVC0C0_SET_FALCON02_V 31:0 + +#define NVC0C0_SET_FALCON03 0x050c +#define NVC0C0_SET_FALCON03_V 31:0 + +#define NVC0C0_SET_FALCON04 0x0510 +#define NVC0C0_SET_FALCON04_V 31:0 + +#define NVC0C0_SET_FALCON05 0x0514 +#define NVC0C0_SET_FALCON05_V 31:0 + +#define NVC0C0_SET_FALCON06 0x0518 +#define NVC0C0_SET_FALCON06_V 31:0 + +#define NVC0C0_SET_FALCON07 0x051c +#define NVC0C0_SET_FALCON07_V 31:0 + +#define NVC0C0_SET_FALCON08 0x0520 +#define NVC0C0_SET_FALCON08_V 31:0 + +#define NVC0C0_SET_FALCON09 0x0524 +#define NVC0C0_SET_FALCON09_V 31:0 + +#define NVC0C0_SET_FALCON10 0x0528 +#define NVC0C0_SET_FALCON10_V 31:0 + +#define NVC0C0_SET_FALCON11 0x052c +#define NVC0C0_SET_FALCON11_V 31:0 + +#define NVC0C0_SET_FALCON12 0x0530 +#define NVC0C0_SET_FALCON12_V 31:0 + +#define NVC0C0_SET_FALCON13 0x0534 +#define NVC0C0_SET_FALCON13_V 31:0 + +#define NVC0C0_SET_FALCON14 0x0538 +#define NVC0C0_SET_FALCON14_V 31:0 + +#define NVC0C0_SET_FALCON15 0x053c +#define NVC0C0_SET_FALCON15_V 31:0 + +#define NVC0C0_SET_FALCON16 0x0540 +#define NVC0C0_SET_FALCON16_V 31:0 + +#define NVC0C0_SET_FALCON17 0x0544 +#define NVC0C0_SET_FALCON17_V 31:0 + +#define NVC0C0_SET_FALCON18 0x0548 +#define NVC0C0_SET_FALCON18_V 31:0 + +#define NVC0C0_SET_FALCON19 0x054c +#define NVC0C0_SET_FALCON19_V 31:0 + +#define NVC0C0_SET_FALCON20 0x0550 +#define NVC0C0_SET_FALCON20_V 31:0 + +#define NVC0C0_SET_FALCON21 0x0554 +#define NVC0C0_SET_FALCON21_V 31:0 + +#define NVC0C0_SET_FALCON22 0x0558 +#define NVC0C0_SET_FALCON22_V 31:0 + +#define NVC0C0_SET_FALCON23 0x055c +#define NVC0C0_SET_FALCON23_V 31:0 + +#define NVC0C0_SET_FALCON24 0x0560 +#define NVC0C0_SET_FALCON24_V 31:0 + +#define NVC0C0_SET_FALCON25 0x0564 +#define NVC0C0_SET_FALCON25_V 31:0 + +#define NVC0C0_SET_FALCON26 0x0568 +#define NVC0C0_SET_FALCON26_V 31:0 + +#define NVC0C0_SET_FALCON27 0x056c +#define NVC0C0_SET_FALCON27_V 31:0 + +#define NVC0C0_SET_FALCON28 0x0570 +#define NVC0C0_SET_FALCON28_V 31:0 + +#define NVC0C0_SET_FALCON29 0x0574 +#define NVC0C0_SET_FALCON29_V 31:0 + +#define NVC0C0_SET_FALCON30 0x0578 +#define NVC0C0_SET_FALCON30_V 31:0 + +#define NVC0C0_SET_FALCON31 0x057c +#define NVC0C0_SET_FALCON31_V 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC0C0_SET_SPARE_NOOP12 0x0f44 +#define NVC0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP13 0x0f48 +#define NVC0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP14 0x0f4c +#define NVC0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP15 0x0f50 +#define NVC0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP00 0x1040 +#define NVC0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP01 0x1044 +#define NVC0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP02 0x1048 +#define NVC0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP03 0x104c +#define NVC0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP04 0x1050 +#define NVC0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP05 0x1054 +#define NVC0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP06 0x1058 +#define NVC0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP07 0x105c +#define NVC0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP08 0x1060 +#define NVC0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP09 0x1064 +#define NVC0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP10 0x1068 +#define NVC0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP11 0x106c +#define NVC0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVC0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_PROGRAM_REGION_B 0x160c +#define NVC0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC0C0_PIPE_NOP 0x1a2c +#define NVC0C0_PIPE_NOP_V 31:0 + +#define NVC0C0_SET_SPARE00 0x1a30 +#define NVC0C0_SET_SPARE00_V 31:0 + +#define NVC0C0_SET_SPARE01 0x1a34 +#define NVC0C0_SET_SPARE01_V 31:0 + +#define NVC0C0_SET_SPARE02 0x1a38 +#define NVC0C0_SET_SPARE02_V 31:0 + +#define NVC0C0_SET_SPARE03 0x1a3c +#define NVC0C0_SET_SPARE03_V 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC0C0_SET_TRAP_HANDLER 0x260c +#define NVC0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_pascal_compute_a_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/clc0c0qmd.h b/src/nouveau/nvidia-headers/classes/clc0c0qmd.h new file mode 100644 index 0000000..040bdcd --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc0c0qmd.h @@ -0,0 +1,665 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC0C0QMD_H__ +#define __CLC0C0QMD_H__ + +/* +** Queue Meta Data, Version 01_07 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVC0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVC0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVC0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVC0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVC0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVC0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVC0C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVC0C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVC0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVC0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVC0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVC0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVC0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVC0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVC0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVC0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVC0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVC0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVC0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVC0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVC0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVC0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVC0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVC0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVC0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVC0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVC0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVC0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVC0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVC0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC0C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVC0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVC0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVC0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVC0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVC0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVC0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVC0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVC0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVC0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVC0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVC0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_00 + */ + +#define NVC0C0_QMDV02_00_OUTER_PUT MW(30:0) +#define NVC0C0_QMDV02_00_OUTER_OVERFLOW MW(31:31) +#define NVC0C0_QMDV02_00_OUTER_GET MW(62:32) +#define NVC0C0_QMDV02_00_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC0C0_QMDV02_00_INNER_GET MW(94:64) +#define NVC0C0_QMDV02_00_INNER_OVERFLOW MW(95:95) +#define NVC0C0_QMDV02_00_INNER_PUT MW(126:96) +#define NVC0C0_QMDV02_00_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC0C0_QMDV02_00_QMD_RESERVED_A_A MW(159:128) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC0C0_QMDV02_00_QMD_GROUP_ID MW(197:192) +#define NVC0C0_QMDV02_00_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_IS_QUEUE MW(200:200) +#define NVC0C0_QMDV02_00_IS_QUEUE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_IS_QUEUE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_QMD_RESERVED_B MW(223:208) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC0C0_QMDV02_00_QMD_RESERVED_C MW(249:249) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_PROGRAM_OFFSET MW(287:256) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC0C0_QMDV02_00_QMD_RESERVED_D MW(335:328) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE MW(369:368) +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_THROTTLED MW(372:372) +#define NVC0C0_QMDV02_00_THROTTLED_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_THROTTLED_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC0C0_QMDV02_00_SAMPLER_INDEX MW(382:382) +#define NVC0C0_QMDV02_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC0C0_QMDV02_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC0C0_QMDV02_00_CTA_RASTER_WIDTH MW(415:384) +#define NVC0C0_QMDV02_00_CTA_RASTER_HEIGHT MW(431:416) +#define NVC0C0_QMDV02_00_QMD_RESERVED13A MW(447:432) +#define NVC0C0_QMDV02_00_CTA_RASTER_DEPTH MW(463:448) +#define NVC0C0_QMDV02_00_QMD_RESERVED14A MW(479:464) +#define NVC0C0_QMDV02_00_QMD_RESERVED15A MW(511:480) +#define NVC0C0_QMDV02_00_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC0C0_QMDV02_00_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC0C0_QMDV02_00_SHARED_MEMORY_SIZE MW(561:544) +#define NVC0C0_QMDV02_00_QMD_RESERVED_G MW(575:562) +#define NVC0C0_QMDV02_00_QMD_VERSION MW(579:576) +#define NVC0C0_QMDV02_00_QMD_MAJOR_VERSION MW(583:580) +#define NVC0C0_QMDV02_00_QMD_RESERVED_H MW(591:584) +#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_QMD_RESERVED_I MW(671:648) +#define NVC0C0_QMDV02_00_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC0C0_QMDV02_00_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC0C0_QMDV02_00_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC0C0_QMDV02_00_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC0C0_QMDV02_00_QMD_RESERVED_J MW(783:776) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_00_QMD_RESERVED_K MW(791:791) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_PAYLOAD MW(831:800) +#define NVC0C0_QMDV02_00_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC0C0_QMDV02_00_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC0C0_QMDV02_00_QMD_RESERVED_L MW(879:872) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_00_QMD_RESERVED_M MW(887:887) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_PAYLOAD MW(927:896) +#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC0C0_QMDV02_00_QMD_RESERVED_N MW(954:952) +#define NVC0C0_QMDV02_00_BARRIER_COUNT MW(959:955) +#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC0C0_QMDV02_00_REGISTER_COUNT MW(991:984) +#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC0C0_QMDV02_00_SASS_VERSION MW(1023:1016) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC0C0_QMDV02_00_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC0C0_QMDV02_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC0C0_QMDV02_00_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC0C0_QMDV02_00_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC0C0_QMDV02_00_QMD_RESERVED_Q MW(1630:1630) +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC0C0_QMDV02_00_CTA_RASTER_WIDTH_RESUME MW(1695:1664) +#define NVC0C0_QMDV02_00_CTA_RASTER_HEIGHT_RESUME MW(1711:1696) +#define NVC0C0_QMDV02_00_CTA_RASTER_DEPTH_RESUME MW(1727:1712) +#define NVC0C0_QMDV02_00_QMD_SPARE_G MW(1759:1728) +#define NVC0C0_QMDV02_00_QMD_SPARE_H MW(1791:1760) +#define NVC0C0_QMDV02_00_QMD_SPARE_I MW(1823:1792) +#define NVC0C0_QMDV02_00_QMD_SPARE_J MW(1855:1824) +#define NVC0C0_QMDV02_00_QMD_SPARE_K MW(1887:1856) +#define NVC0C0_QMDV02_00_QMD_SPARE_L MW(1919:1888) +#define NVC0C0_QMDV02_00_QMD_SPARE_M MW(1951:1920) +#define NVC0C0_QMDV02_00_QMD_SPARE_N MW(1983:1952) +#define NVC0C0_QMDV02_00_DEBUG_ID_UPPER MW(2015:1984) +#define NVC0C0_QMDV02_00_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_01 + */ + +#define NVC0C0_QMDV02_01_OUTER_PUT MW(30:0) +#define NVC0C0_QMDV02_01_OUTER_OVERFLOW MW(31:31) +#define NVC0C0_QMDV02_01_OUTER_GET MW(62:32) +#define NVC0C0_QMDV02_01_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC0C0_QMDV02_01_INNER_GET MW(94:64) +#define NVC0C0_QMDV02_01_INNER_OVERFLOW MW(95:95) +#define NVC0C0_QMDV02_01_INNER_PUT MW(126:96) +#define NVC0C0_QMDV02_01_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC0C0_QMDV02_01_QMD_GROUP_ID MW(133:128) +#define NVC0C0_QMDV02_01_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_IS_QUEUE MW(136:136) +#define NVC0C0_QMDV02_01_IS_QUEUE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_IS_QUEUE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_QMD_RESERVED_B MW(159:144) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC0C0_QMDV02_01_QMD_RESERVED_C MW(185:185) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC0C0_QMDV02_01_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC0C0_QMDV02_01_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC0C0_QMDV02_01_PROGRAM_OFFSET MW(287:256) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC0C0_QMDV02_01_QMD_RESERVED_D MW(335:328) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE MW(369:368) +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_THROTTLED MW(372:372) +#define NVC0C0_QMDV02_01_THROTTLED_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_THROTTLED_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC0C0_QMDV02_01_SAMPLER_INDEX MW(382:382) +#define NVC0C0_QMDV02_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC0C0_QMDV02_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC0C0_QMDV02_01_CTA_RASTER_WIDTH MW(415:384) +#define NVC0C0_QMDV02_01_CTA_RASTER_HEIGHT MW(431:416) +#define NVC0C0_QMDV02_01_QMD_RESERVED13A MW(447:432) +#define NVC0C0_QMDV02_01_CTA_RASTER_DEPTH MW(463:448) +#define NVC0C0_QMDV02_01_QMD_RESERVED14A MW(479:464) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC0C0_QMDV02_01_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC0C0_QMDV02_01_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC0C0_QMDV02_01_SHARED_MEMORY_SIZE MW(561:544) +#define NVC0C0_QMDV02_01_QMD_RESERVED_G MW(575:562) +#define NVC0C0_QMDV02_01_QMD_VERSION MW(579:576) +#define NVC0C0_QMDV02_01_QMD_MAJOR_VERSION MW(583:580) +#define NVC0C0_QMDV02_01_QMD_RESERVED_H MW(591:584) +#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_QMD_RESERVED_I MW(671:648) +#define NVC0C0_QMDV02_01_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC0C0_QMDV02_01_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC0C0_QMDV02_01_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC0C0_QMDV02_01_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC0C0_QMDV02_01_QMD_RESERVED_J MW(783:776) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_01_QMD_RESERVED_K MW(791:791) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_PAYLOAD MW(831:800) +#define NVC0C0_QMDV02_01_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC0C0_QMDV02_01_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC0C0_QMDV02_01_QMD_RESERVED_L MW(879:872) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_01_QMD_RESERVED_M MW(887:887) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_PAYLOAD MW(927:896) +#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC0C0_QMDV02_01_QMD_RESERVED_N MW(954:952) +#define NVC0C0_QMDV02_01_BARRIER_COUNT MW(959:955) +#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC0C0_QMDV02_01_REGISTER_COUNT MW(991:984) +#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC0C0_QMDV02_01_SASS_VERSION MW(1023:1016) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC0C0_QMDV02_01_QMD_RESERVED_R MW(1567:1536) +#define NVC0C0_QMDV02_01_QMD_RESERVED_S MW(1599:1568) +#define NVC0C0_QMDV02_01_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC0C0_QMDV02_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC0C0_QMDV02_01_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC0C0_QMDV02_01_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC0C0_QMDV02_01_QMD_RESERVED_Q MW(1694:1694) +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC0C0_QMDV02_01_QMD_SPARE_G MW(1759:1728) +#define NVC0C0_QMDV02_01_QMD_SPARE_H MW(1791:1760) +#define NVC0C0_QMDV02_01_QMD_SPARE_I MW(1823:1792) +#define NVC0C0_QMDV02_01_QMD_SPARE_J MW(1855:1824) +#define NVC0C0_QMDV02_01_QMD_SPARE_K MW(1887:1856) +#define NVC0C0_QMDV02_01_QMD_SPARE_L MW(1919:1888) +#define NVC0C0_QMDV02_01_QMD_SPARE_M MW(1951:1920) +#define NVC0C0_QMDV02_01_QMD_SPARE_N MW(1983:1952) +#define NVC0C0_QMDV02_01_DEBUG_ID_UPPER MW(2015:1984) +#define NVC0C0_QMDV02_01_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC0C0QMD_H__ diff --git a/src/nouveau/nvidia-headers/classes/clc1b5.h b/src/nouveau/nvidia-headers/classes/clc1b5.h new file mode 100644 index 0000000..fff8467 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc1b5.h @@ -0,0 +1,273 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc1b5_h_ +#define _clc1b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PASCAL_DMA_COPY_B (0x0000C1B5) + +#define NVC1B5_NOP (0x00000100) +#define NVC1B5_NOP_PARAMETER 31:0 +#define NVC1B5_PM_TRIGGER (0x00000140) +#define NVC1B5_PM_TRIGGER_V 31:0 +#define NVC1B5_SET_SEMAPHORE_A (0x00000240) +#define NVC1B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC1B5_SET_SEMAPHORE_B (0x00000244) +#define NVC1B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC1B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC1B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC1B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC1B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC1B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC1B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC1B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC1B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC1B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC1B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC1B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC1B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC1B5_LAUNCH_DMA (0x00000300) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC1B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC1B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC1B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC1B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC1B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC1B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC1B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC1B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC1B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC1B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC1B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC1B5_OFFSET_IN_UPPER (0x00000400) +#define NVC1B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC1B5_OFFSET_IN_LOWER (0x00000404) +#define NVC1B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC1B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC1B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC1B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC1B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC1B5_PITCH_IN (0x00000410) +#define NVC1B5_PITCH_IN_VALUE 31:0 +#define NVC1B5_PITCH_OUT (0x00000414) +#define NVC1B5_PITCH_OUT_VALUE 31:0 +#define NVC1B5_LINE_LENGTH_IN (0x00000418) +#define NVC1B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC1B5_LINE_COUNT (0x0000041C) +#define NVC1B5_LINE_COUNT_VALUE 31:0 +#define NVC1B5_SET_REMAP_CONST_A (0x00000700) +#define NVC1B5_SET_REMAP_CONST_A_V 31:0 +#define NVC1B5_SET_REMAP_CONST_B (0x00000704) +#define NVC1B5_SET_REMAP_CONST_B_V 31:0 +#define NVC1B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC1B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC1B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_DST_WIDTH (0x00000710) +#define NVC1B5_SET_DST_WIDTH_V 31:0 +#define NVC1B5_SET_DST_HEIGHT (0x00000714) +#define NVC1B5_SET_DST_HEIGHT_V 31:0 +#define NVC1B5_SET_DST_DEPTH (0x00000718) +#define NVC1B5_SET_DST_DEPTH_V 31:0 +#define NVC1B5_SET_DST_LAYER (0x0000071C) +#define NVC1B5_SET_DST_LAYER_V 31:0 +#define NVC1B5_SET_DST_ORIGIN (0x00000720) +#define NVC1B5_SET_DST_ORIGIN_X 15:0 +#define NVC1B5_SET_DST_ORIGIN_Y 31:16 +#define NVC1B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC1B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC1B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC1B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC1B5_SET_SRC_WIDTH (0x0000072C) +#define NVC1B5_SET_SRC_WIDTH_V 31:0 +#define NVC1B5_SET_SRC_HEIGHT (0x00000730) +#define NVC1B5_SET_SRC_HEIGHT_V 31:0 +#define NVC1B5_SET_SRC_DEPTH (0x00000734) +#define NVC1B5_SET_SRC_DEPTH_V 31:0 +#define NVC1B5_SET_SRC_LAYER (0x00000738) +#define NVC1B5_SET_SRC_LAYER_V 31:0 +#define NVC1B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC1B5_SET_SRC_ORIGIN_X 15:0 +#define NVC1B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC1B5_SRC_ORIGIN_X (0x00000744) +#define NVC1B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC1B5_SRC_ORIGIN_Y (0x00000748) +#define NVC1B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_X (0x0000074C) +#define NVC1B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC1B5_DST_ORIGIN_Y (0x00000750) +#define NVC1B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC1B5_PM_TRIGGER_END (0x00001114) +#define NVC1B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc1b5_h + diff --git a/src/nouveau/nvidia-headers/classes/clc1c0.h b/src/nouveau/nvidia-headers/classes/clc1c0.h new file mode 100644 index 0000000..a7d6870 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc1c0.h @@ -0,0 +1,794 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_pascal_compute_b_h_ +#define _cl_pascal_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_compute_b */ + +#include "nvtypes.h" + +#define PASCAL_COMPUTE_B 0xC1C0 + +#define NVC1C0_SET_OBJECT 0x0000 +#define NVC1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC1C0_NO_OPERATION 0x0100 +#define NVC1C0_NO_OPERATION_V 31:0 + +#define NVC1C0_SET_NOTIFY_A 0x0104 +#define NVC1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC1C0_SET_NOTIFY_B 0x0108 +#define NVC1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_NOTIFY 0x010c +#define NVC1C0_NOTIFY_TYPE 31:0 +#define NVC1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC1C0_WAIT_FOR_IDLE 0x0110 +#define NVC1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC1C0_SEND_GO_IDLE 0x013c +#define NVC1C0_SEND_GO_IDLE_V 31:0 + +#define NVC1C0_PM_TRIGGER 0x0140 +#define NVC1C0_PM_TRIGGER_V 31:0 + +#define NVC1C0_PM_TRIGGER_WFI 0x0144 +#define NVC1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC1C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC1C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC1C0_LINE_LENGTH_IN 0x0180 +#define NVC1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC1C0_LINE_COUNT 0x0184 +#define NVC1C0_LINE_COUNT_VALUE 31:0 + +#define NVC1C0_OFFSET_OUT_UPPER 0x0188 +#define NVC1C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC1C0_OFFSET_OUT 0x018c +#define NVC1C0_OFFSET_OUT_VALUE 31:0 + +#define NVC1C0_PITCH_OUT 0x0190 +#define NVC1C0_PITCH_OUT_VALUE 31:0 + +#define NVC1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC1C0_SET_DST_WIDTH 0x0198 +#define NVC1C0_SET_DST_WIDTH_V 31:0 + +#define NVC1C0_SET_DST_HEIGHT 0x019c +#define NVC1C0_SET_DST_HEIGHT_V 31:0 + +#define NVC1C0_SET_DST_DEPTH 0x01a0 +#define NVC1C0_SET_DST_DEPTH_V 31:0 + +#define NVC1C0_SET_DST_LAYER 0x01a4 +#define NVC1C0_SET_DST_LAYER_V 31:0 + +#define NVC1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC1C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC1C0_LAUNCH_DMA 0x01b0 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC1C0_LOAD_INLINE_DATA 0x01b4 +#define NVC1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVC1C0_PERFMON_TRANSFER 0x0210 +#define NVC1C0_PERFMON_TRANSFER_V 31:0 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC1C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC1C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC1C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC1C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC1C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC1C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC1C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC1C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC1C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC1C0_SET_CWD_CONTROL 0x0240 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC1C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC1C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC1C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC1C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC1C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC1C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC1C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC1C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC1C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC1C0_SET_GWC_SCG_TYPE 0x026c +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVC1C0_SET_SCG_CONTROL 0x0270 +#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVC1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_SET_QMD_VERSION 0x0288 +#define NVC1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_SET_WFI_CONFIG 0x028c +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVC1C0_CHECK_QMD_VERSION 0x0290 +#define NVC1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVC1C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC1C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC1C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC1C0_SEND_PCAS_A 0x02b4 +#define NVC1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC1C0_SEND_PCAS_B 0x02b8 +#define NVC1C0_SEND_PCAS_B_FROM 23:0 +#define NVC1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC1C0_SET_SPA_VERSION 0x0310 +#define NVC1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC1C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC1C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC1C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC1C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC1C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC1C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC1C0_SET_FALCON00 0x0500 +#define NVC1C0_SET_FALCON00_V 31:0 + +#define NVC1C0_SET_FALCON01 0x0504 +#define NVC1C0_SET_FALCON01_V 31:0 + +#define NVC1C0_SET_FALCON02 0x0508 +#define NVC1C0_SET_FALCON02_V 31:0 + +#define NVC1C0_SET_FALCON03 0x050c +#define NVC1C0_SET_FALCON03_V 31:0 + +#define NVC1C0_SET_FALCON04 0x0510 +#define NVC1C0_SET_FALCON04_V 31:0 + +#define NVC1C0_SET_FALCON05 0x0514 +#define NVC1C0_SET_FALCON05_V 31:0 + +#define NVC1C0_SET_FALCON06 0x0518 +#define NVC1C0_SET_FALCON06_V 31:0 + +#define NVC1C0_SET_FALCON07 0x051c +#define NVC1C0_SET_FALCON07_V 31:0 + +#define NVC1C0_SET_FALCON08 0x0520 +#define NVC1C0_SET_FALCON08_V 31:0 + +#define NVC1C0_SET_FALCON09 0x0524 +#define NVC1C0_SET_FALCON09_V 31:0 + +#define NVC1C0_SET_FALCON10 0x0528 +#define NVC1C0_SET_FALCON10_V 31:0 + +#define NVC1C0_SET_FALCON11 0x052c +#define NVC1C0_SET_FALCON11_V 31:0 + +#define NVC1C0_SET_FALCON12 0x0530 +#define NVC1C0_SET_FALCON12_V 31:0 + +#define NVC1C0_SET_FALCON13 0x0534 +#define NVC1C0_SET_FALCON13_V 31:0 + +#define NVC1C0_SET_FALCON14 0x0538 +#define NVC1C0_SET_FALCON14_V 31:0 + +#define NVC1C0_SET_FALCON15 0x053c +#define NVC1C0_SET_FALCON15_V 31:0 + +#define NVC1C0_SET_FALCON16 0x0540 +#define NVC1C0_SET_FALCON16_V 31:0 + +#define NVC1C0_SET_FALCON17 0x0544 +#define NVC1C0_SET_FALCON17_V 31:0 + +#define NVC1C0_SET_FALCON18 0x0548 +#define NVC1C0_SET_FALCON18_V 31:0 + +#define NVC1C0_SET_FALCON19 0x054c +#define NVC1C0_SET_FALCON19_V 31:0 + +#define NVC1C0_SET_FALCON20 0x0550 +#define NVC1C0_SET_FALCON20_V 31:0 + +#define NVC1C0_SET_FALCON21 0x0554 +#define NVC1C0_SET_FALCON21_V 31:0 + +#define NVC1C0_SET_FALCON22 0x0558 +#define NVC1C0_SET_FALCON22_V 31:0 + +#define NVC1C0_SET_FALCON23 0x055c +#define NVC1C0_SET_FALCON23_V 31:0 + +#define NVC1C0_SET_FALCON24 0x0560 +#define NVC1C0_SET_FALCON24_V 31:0 + +#define NVC1C0_SET_FALCON25 0x0564 +#define NVC1C0_SET_FALCON25_V 31:0 + +#define NVC1C0_SET_FALCON26 0x0568 +#define NVC1C0_SET_FALCON26_V 31:0 + +#define NVC1C0_SET_FALCON27 0x056c +#define NVC1C0_SET_FALCON27_V 31:0 + +#define NVC1C0_SET_FALCON28 0x0570 +#define NVC1C0_SET_FALCON28_V 31:0 + +#define NVC1C0_SET_FALCON29 0x0574 +#define NVC1C0_SET_FALCON29_V 31:0 + +#define NVC1C0_SET_FALCON30 0x0578 +#define NVC1C0_SET_FALCON30_V 31:0 + +#define NVC1C0_SET_FALCON31 0x057c +#define NVC1C0_SET_FALCON31_V 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC1C0_SET_SPARE_NOOP12 0x0f44 +#define NVC1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP13 0x0f48 +#define NVC1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP14 0x0f4c +#define NVC1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP15 0x0f50 +#define NVC1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP00 0x1040 +#define NVC1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP01 0x1044 +#define NVC1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP02 0x1048 +#define NVC1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP03 0x104c +#define NVC1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP04 0x1050 +#define NVC1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP05 0x1054 +#define NVC1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP06 0x1058 +#define NVC1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP07 0x105c +#define NVC1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP08 0x1060 +#define NVC1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP09 0x1064 +#define NVC1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP10 0x1068 +#define NVC1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP11 0x106c +#define NVC1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVC1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_PROGRAM_REGION_B 0x160c +#define NVC1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC1C0_PIPE_NOP 0x1a2c +#define NVC1C0_PIPE_NOP_V 31:0 + +#define NVC1C0_SET_SPARE00 0x1a30 +#define NVC1C0_SET_SPARE00_V 31:0 + +#define NVC1C0_SET_SPARE01 0x1a34 +#define NVC1C0_SET_SPARE01_V 31:0 + +#define NVC1C0_SET_SPARE02 0x1a38 +#define NVC1C0_SET_SPARE02_V 31:0 + +#define NVC1C0_SET_SPARE03 0x1a3c +#define NVC1C0_SET_SPARE03_V 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC1C0_SET_TRAP_HANDLER 0x260c +#define NVC1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_pascal_compute_b_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/clc1c0qmd.h b/src/nouveau/nvidia-headers/classes/clc1c0qmd.h new file mode 100644 index 0000000..41f68a4 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc1c0qmd.h @@ -0,0 +1,665 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC1C0QMD_H__ +#define __CLC1C0QMD_H__ + +/* +** Queue Meta Data, Version 01_07 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC1C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVC1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVC1C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVC1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC1C0_QMDV01_07_INNER_GET MW(94:64) +#define NVC1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVC1C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVC1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVC1C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVC1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_THROTTLED MW(372:372) +#define NVC1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVC1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVC1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVC1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVC1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVC1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVC1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVC1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVC1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVC1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVC1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVC1C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVC1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVC1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVC1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVC1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVC1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVC1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVC1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVC1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVC1C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVC1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC1C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVC1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVC1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVC1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVC1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVC1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVC1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVC1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVC1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVC1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVC1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVC1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_00 + */ + +#define NVC1C0_QMDV02_00_OUTER_PUT MW(30:0) +#define NVC1C0_QMDV02_00_OUTER_OVERFLOW MW(31:31) +#define NVC1C0_QMDV02_00_OUTER_GET MW(62:32) +#define NVC1C0_QMDV02_00_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC1C0_QMDV02_00_INNER_GET MW(94:64) +#define NVC1C0_QMDV02_00_INNER_OVERFLOW MW(95:95) +#define NVC1C0_QMDV02_00_INNER_PUT MW(126:96) +#define NVC1C0_QMDV02_00_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC1C0_QMDV02_00_QMD_RESERVED_A_A MW(159:128) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC1C0_QMDV02_00_QMD_GROUP_ID MW(197:192) +#define NVC1C0_QMDV02_00_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_IS_QUEUE MW(200:200) +#define NVC1C0_QMDV02_00_IS_QUEUE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_IS_QUEUE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_QMD_RESERVED_B MW(223:208) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC1C0_QMDV02_00_QMD_RESERVED_C MW(249:249) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_PROGRAM_OFFSET MW(287:256) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC1C0_QMDV02_00_QMD_RESERVED_D MW(335:328) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE MW(369:368) +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_THROTTLED MW(372:372) +#define NVC1C0_QMDV02_00_THROTTLED_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_THROTTLED_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC1C0_QMDV02_00_SAMPLER_INDEX MW(382:382) +#define NVC1C0_QMDV02_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC1C0_QMDV02_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC1C0_QMDV02_00_CTA_RASTER_WIDTH MW(415:384) +#define NVC1C0_QMDV02_00_CTA_RASTER_HEIGHT MW(431:416) +#define NVC1C0_QMDV02_00_QMD_RESERVED13A MW(447:432) +#define NVC1C0_QMDV02_00_CTA_RASTER_DEPTH MW(463:448) +#define NVC1C0_QMDV02_00_QMD_RESERVED14A MW(479:464) +#define NVC1C0_QMDV02_00_QMD_RESERVED15A MW(511:480) +#define NVC1C0_QMDV02_00_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC1C0_QMDV02_00_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC1C0_QMDV02_00_SHARED_MEMORY_SIZE MW(561:544) +#define NVC1C0_QMDV02_00_QMD_RESERVED_G MW(575:562) +#define NVC1C0_QMDV02_00_QMD_VERSION MW(579:576) +#define NVC1C0_QMDV02_00_QMD_MAJOR_VERSION MW(583:580) +#define NVC1C0_QMDV02_00_QMD_RESERVED_H MW(591:584) +#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_QMD_RESERVED_I MW(671:648) +#define NVC1C0_QMDV02_00_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC1C0_QMDV02_00_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC1C0_QMDV02_00_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC1C0_QMDV02_00_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC1C0_QMDV02_00_QMD_RESERVED_J MW(783:776) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_00_QMD_RESERVED_K MW(791:791) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_PAYLOAD MW(831:800) +#define NVC1C0_QMDV02_00_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC1C0_QMDV02_00_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC1C0_QMDV02_00_QMD_RESERVED_L MW(879:872) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_00_QMD_RESERVED_M MW(887:887) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_PAYLOAD MW(927:896) +#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC1C0_QMDV02_00_QMD_RESERVED_N MW(954:952) +#define NVC1C0_QMDV02_00_BARRIER_COUNT MW(959:955) +#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC1C0_QMDV02_00_REGISTER_COUNT MW(991:984) +#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC1C0_QMDV02_00_SASS_VERSION MW(1023:1016) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC1C0_QMDV02_00_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC1C0_QMDV02_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC1C0_QMDV02_00_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC1C0_QMDV02_00_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC1C0_QMDV02_00_QMD_RESERVED_Q MW(1630:1630) +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC1C0_QMDV02_00_CTA_RASTER_WIDTH_RESUME MW(1695:1664) +#define NVC1C0_QMDV02_00_CTA_RASTER_HEIGHT_RESUME MW(1711:1696) +#define NVC1C0_QMDV02_00_CTA_RASTER_DEPTH_RESUME MW(1727:1712) +#define NVC1C0_QMDV02_00_QMD_SPARE_G MW(1759:1728) +#define NVC1C0_QMDV02_00_QMD_SPARE_H MW(1791:1760) +#define NVC1C0_QMDV02_00_QMD_SPARE_I MW(1823:1792) +#define NVC1C0_QMDV02_00_QMD_SPARE_J MW(1855:1824) +#define NVC1C0_QMDV02_00_QMD_SPARE_K MW(1887:1856) +#define NVC1C0_QMDV02_00_QMD_SPARE_L MW(1919:1888) +#define NVC1C0_QMDV02_00_QMD_SPARE_M MW(1951:1920) +#define NVC1C0_QMDV02_00_QMD_SPARE_N MW(1983:1952) +#define NVC1C0_QMDV02_00_DEBUG_ID_UPPER MW(2015:1984) +#define NVC1C0_QMDV02_00_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_01 + */ + +#define NVC1C0_QMDV02_01_OUTER_PUT MW(30:0) +#define NVC1C0_QMDV02_01_OUTER_OVERFLOW MW(31:31) +#define NVC1C0_QMDV02_01_OUTER_GET MW(62:32) +#define NVC1C0_QMDV02_01_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC1C0_QMDV02_01_INNER_GET MW(94:64) +#define NVC1C0_QMDV02_01_INNER_OVERFLOW MW(95:95) +#define NVC1C0_QMDV02_01_INNER_PUT MW(126:96) +#define NVC1C0_QMDV02_01_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC1C0_QMDV02_01_QMD_GROUP_ID MW(133:128) +#define NVC1C0_QMDV02_01_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_IS_QUEUE MW(136:136) +#define NVC1C0_QMDV02_01_IS_QUEUE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_IS_QUEUE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_QMD_RESERVED_B MW(159:144) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC1C0_QMDV02_01_QMD_RESERVED_C MW(185:185) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC1C0_QMDV02_01_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC1C0_QMDV02_01_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC1C0_QMDV02_01_PROGRAM_OFFSET MW(287:256) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC1C0_QMDV02_01_QMD_RESERVED_D MW(335:328) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE MW(369:368) +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_THROTTLED MW(372:372) +#define NVC1C0_QMDV02_01_THROTTLED_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_THROTTLED_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC1C0_QMDV02_01_SAMPLER_INDEX MW(382:382) +#define NVC1C0_QMDV02_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC1C0_QMDV02_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC1C0_QMDV02_01_CTA_RASTER_WIDTH MW(415:384) +#define NVC1C0_QMDV02_01_CTA_RASTER_HEIGHT MW(431:416) +#define NVC1C0_QMDV02_01_QMD_RESERVED13A MW(447:432) +#define NVC1C0_QMDV02_01_CTA_RASTER_DEPTH MW(463:448) +#define NVC1C0_QMDV02_01_QMD_RESERVED14A MW(479:464) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC1C0_QMDV02_01_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC1C0_QMDV02_01_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC1C0_QMDV02_01_SHARED_MEMORY_SIZE MW(561:544) +#define NVC1C0_QMDV02_01_QMD_RESERVED_G MW(575:562) +#define NVC1C0_QMDV02_01_QMD_VERSION MW(579:576) +#define NVC1C0_QMDV02_01_QMD_MAJOR_VERSION MW(583:580) +#define NVC1C0_QMDV02_01_QMD_RESERVED_H MW(591:584) +#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_QMD_RESERVED_I MW(671:648) +#define NVC1C0_QMDV02_01_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC1C0_QMDV02_01_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC1C0_QMDV02_01_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC1C0_QMDV02_01_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC1C0_QMDV02_01_QMD_RESERVED_J MW(783:776) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_01_QMD_RESERVED_K MW(791:791) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_PAYLOAD MW(831:800) +#define NVC1C0_QMDV02_01_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC1C0_QMDV02_01_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC1C0_QMDV02_01_QMD_RESERVED_L MW(879:872) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_01_QMD_RESERVED_M MW(887:887) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_PAYLOAD MW(927:896) +#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC1C0_QMDV02_01_QMD_RESERVED_N MW(954:952) +#define NVC1C0_QMDV02_01_BARRIER_COUNT MW(959:955) +#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC1C0_QMDV02_01_REGISTER_COUNT MW(991:984) +#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC1C0_QMDV02_01_SASS_VERSION MW(1023:1016) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC1C0_QMDV02_01_QMD_RESERVED_R MW(1567:1536) +#define NVC1C0_QMDV02_01_QMD_RESERVED_S MW(1599:1568) +#define NVC1C0_QMDV02_01_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC1C0_QMDV02_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC1C0_QMDV02_01_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC1C0_QMDV02_01_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC1C0_QMDV02_01_QMD_RESERVED_Q MW(1694:1694) +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC1C0_QMDV02_01_QMD_SPARE_G MW(1759:1728) +#define NVC1C0_QMDV02_01_QMD_SPARE_H MW(1791:1760) +#define NVC1C0_QMDV02_01_QMD_SPARE_I MW(1823:1792) +#define NVC1C0_QMDV02_01_QMD_SPARE_J MW(1855:1824) +#define NVC1C0_QMDV02_01_QMD_SPARE_K MW(1887:1856) +#define NVC1C0_QMDV02_01_QMD_SPARE_L MW(1919:1888) +#define NVC1C0_QMDV02_01_QMD_SPARE_M MW(1951:1920) +#define NVC1C0_QMDV02_01_QMD_SPARE_N MW(1983:1952) +#define NVC1C0_QMDV02_01_DEBUG_ID_UPPER MW(2015:1984) +#define NVC1C0_QMDV02_01_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC1C0QMD_H__ diff --git a/src/nouveau/nvidia-headers/classes/clc3b5.h b/src/nouveau/nvidia-headers/classes/clc3b5.h new file mode 100644 index 0000000..74ee1b7 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc3b5.h @@ -0,0 +1,278 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc3b5_h_ +#define _clc3b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define VOLTA_DMA_COPY_A (0x0000C3B5) + +#define NVC3B5_NOP (0x00000100) +#define NVC3B5_NOP_PARAMETER 31:0 +#define NVC3B5_PM_TRIGGER (0x00000140) +#define NVC3B5_PM_TRIGGER_V 31:0 +#define NVC3B5_SET_SEMAPHORE_A (0x00000240) +#define NVC3B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC3B5_SET_SEMAPHORE_B (0x00000244) +#define NVC3B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC3B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC3B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC3B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC3B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC3B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC3B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC3B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC3B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC3B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC3B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC3B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC3B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC3B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC3B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC3B5_LAUNCH_DMA (0x00000300) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC3B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC3B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC3B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC3B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC3B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC3B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC3B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC3B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC3B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC3B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC3B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC3B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC3B5_OFFSET_IN_UPPER (0x00000400) +#define NVC3B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC3B5_OFFSET_IN_LOWER (0x00000404) +#define NVC3B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC3B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC3B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC3B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC3B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC3B5_PITCH_IN (0x00000410) +#define NVC3B5_PITCH_IN_VALUE 31:0 +#define NVC3B5_PITCH_OUT (0x00000414) +#define NVC3B5_PITCH_OUT_VALUE 31:0 +#define NVC3B5_LINE_LENGTH_IN (0x00000418) +#define NVC3B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC3B5_LINE_COUNT (0x0000041C) +#define NVC3B5_LINE_COUNT_VALUE 31:0 +#define NVC3B5_SET_REMAP_CONST_A (0x00000700) +#define NVC3B5_SET_REMAP_CONST_A_V 31:0 +#define NVC3B5_SET_REMAP_CONST_B (0x00000704) +#define NVC3B5_SET_REMAP_CONST_B_V 31:0 +#define NVC3B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC3B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC3B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_DST_WIDTH (0x00000710) +#define NVC3B5_SET_DST_WIDTH_V 31:0 +#define NVC3B5_SET_DST_HEIGHT (0x00000714) +#define NVC3B5_SET_DST_HEIGHT_V 31:0 +#define NVC3B5_SET_DST_DEPTH (0x00000718) +#define NVC3B5_SET_DST_DEPTH_V 31:0 +#define NVC3B5_SET_DST_LAYER (0x0000071C) +#define NVC3B5_SET_DST_LAYER_V 31:0 +#define NVC3B5_SET_DST_ORIGIN (0x00000720) +#define NVC3B5_SET_DST_ORIGIN_X 15:0 +#define NVC3B5_SET_DST_ORIGIN_Y 31:16 +#define NVC3B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC3B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC3B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC3B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC3B5_SET_SRC_WIDTH (0x0000072C) +#define NVC3B5_SET_SRC_WIDTH_V 31:0 +#define NVC3B5_SET_SRC_HEIGHT (0x00000730) +#define NVC3B5_SET_SRC_HEIGHT_V 31:0 +#define NVC3B5_SET_SRC_DEPTH (0x00000734) +#define NVC3B5_SET_SRC_DEPTH_V 31:0 +#define NVC3B5_SET_SRC_LAYER (0x00000738) +#define NVC3B5_SET_SRC_LAYER_V 31:0 +#define NVC3B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC3B5_SET_SRC_ORIGIN_X 15:0 +#define NVC3B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC3B5_SRC_ORIGIN_X (0x00000744) +#define NVC3B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC3B5_SRC_ORIGIN_Y (0x00000748) +#define NVC3B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_X (0x0000074C) +#define NVC3B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC3B5_DST_ORIGIN_Y (0x00000750) +#define NVC3B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC3B5_PM_TRIGGER_END (0x00001114) +#define NVC3B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc3b5_h + diff --git a/src/nouveau/nvidia-headers/classes/clc3c0.h b/src/nouveau/nvidia-headers/classes/clc3c0.h new file mode 100644 index 0000000..c24db5c --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc3c0.h @@ -0,0 +1,702 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_volta_compute_a_h_ +#define _cl_volta_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_compute_a */ + +#include "nvtypes.h" + +#define VOLTA_COMPUTE_A 0xC3C0 + +#define NVC3C0_SET_OBJECT 0x0000 +#define NVC3C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC3C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC3C0_NO_OPERATION 0x0100 +#define NVC3C0_NO_OPERATION_V 31:0 + +#define NVC3C0_SET_NOTIFY_A 0x0104 +#define NVC3C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC3C0_SET_NOTIFY_B 0x0108 +#define NVC3C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_NOTIFY 0x010c +#define NVC3C0_NOTIFY_TYPE 31:0 +#define NVC3C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC3C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC3C0_WAIT_FOR_IDLE 0x0110 +#define NVC3C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC3C0_SEND_GO_IDLE 0x013c +#define NVC3C0_SEND_GO_IDLE_V 31:0 + +#define NVC3C0_PM_TRIGGER 0x0140 +#define NVC3C0_PM_TRIGGER_V 31:0 + +#define NVC3C0_PM_TRIGGER_WFI 0x0144 +#define NVC3C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC3C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC3C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC3C0_LINE_LENGTH_IN 0x0180 +#define NVC3C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC3C0_LINE_COUNT 0x0184 +#define NVC3C0_LINE_COUNT_VALUE 31:0 + +#define NVC3C0_OFFSET_OUT_UPPER 0x0188 +#define NVC3C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC3C0_OFFSET_OUT 0x018c +#define NVC3C0_OFFSET_OUT_VALUE 31:0 + +#define NVC3C0_PITCH_OUT 0x0190 +#define NVC3C0_PITCH_OUT_VALUE 31:0 + +#define NVC3C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC3C0_SET_DST_WIDTH 0x0198 +#define NVC3C0_SET_DST_WIDTH_V 31:0 + +#define NVC3C0_SET_DST_HEIGHT 0x019c +#define NVC3C0_SET_DST_HEIGHT_V 31:0 + +#define NVC3C0_SET_DST_DEPTH 0x01a0 +#define NVC3C0_SET_DST_DEPTH_V 31:0 + +#define NVC3C0_SET_DST_LAYER 0x01a4 +#define NVC3C0_SET_DST_LAYER_V 31:0 + +#define NVC3C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC3C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC3C0_LAUNCH_DMA 0x01b0 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC3C0_LOAD_INLINE_DATA 0x01b4 +#define NVC3C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC3C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC3C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC3C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC3C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC3C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC3C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC3C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC3C0_PERFMON_TRANSFER 0x0210 +#define NVC3C0_PERFMON_TRANSFER_V 31:0 + +#define NVC3C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC3C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC3C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC3C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC3C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC3C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC3C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC3C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC3C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC3C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC3C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC3C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC3C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC3C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC3C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC3C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC3C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC3C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC3C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC3C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC3C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC3C0_SET_SCG_CONTROL 0x0270 +#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC3C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC3C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC3C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_SET_QMD_VERSION 0x0288 +#define NVC3C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC3C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_CHECK_QMD_VERSION 0x0290 +#define NVC3C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC3C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC3C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC3C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC3C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC3C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC3C0_SEND_PCAS_A 0x02b4 +#define NVC3C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC3C0_SEND_PCAS_B 0x02b8 +#define NVC3C0_SEND_PCAS_B_FROM 23:0 +#define NVC3C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC3C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC3C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC3C0_SET_SPA_VERSION 0x0310 +#define NVC3C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC3C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC3C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC3C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC3C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC3C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC3C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC3C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC3C0_SET_FALCON00 0x0500 +#define NVC3C0_SET_FALCON00_V 31:0 + +#define NVC3C0_SET_FALCON01 0x0504 +#define NVC3C0_SET_FALCON01_V 31:0 + +#define NVC3C0_SET_FALCON02 0x0508 +#define NVC3C0_SET_FALCON02_V 31:0 + +#define NVC3C0_SET_FALCON03 0x050c +#define NVC3C0_SET_FALCON03_V 31:0 + +#define NVC3C0_SET_FALCON04 0x0510 +#define NVC3C0_SET_FALCON04_V 31:0 + +#define NVC3C0_SET_FALCON05 0x0514 +#define NVC3C0_SET_FALCON05_V 31:0 + +#define NVC3C0_SET_FALCON06 0x0518 +#define NVC3C0_SET_FALCON06_V 31:0 + +#define NVC3C0_SET_FALCON07 0x051c +#define NVC3C0_SET_FALCON07_V 31:0 + +#define NVC3C0_SET_FALCON08 0x0520 +#define NVC3C0_SET_FALCON08_V 31:0 + +#define NVC3C0_SET_FALCON09 0x0524 +#define NVC3C0_SET_FALCON09_V 31:0 + +#define NVC3C0_SET_FALCON10 0x0528 +#define NVC3C0_SET_FALCON10_V 31:0 + +#define NVC3C0_SET_FALCON11 0x052c +#define NVC3C0_SET_FALCON11_V 31:0 + +#define NVC3C0_SET_FALCON12 0x0530 +#define NVC3C0_SET_FALCON12_V 31:0 + +#define NVC3C0_SET_FALCON13 0x0534 +#define NVC3C0_SET_FALCON13_V 31:0 + +#define NVC3C0_SET_FALCON14 0x0538 +#define NVC3C0_SET_FALCON14_V 31:0 + +#define NVC3C0_SET_FALCON15 0x053c +#define NVC3C0_SET_FALCON15_V 31:0 + +#define NVC3C0_SET_FALCON16 0x0540 +#define NVC3C0_SET_FALCON16_V 31:0 + +#define NVC3C0_SET_FALCON17 0x0544 +#define NVC3C0_SET_FALCON17_V 31:0 + +#define NVC3C0_SET_FALCON18 0x0548 +#define NVC3C0_SET_FALCON18_V 31:0 + +#define NVC3C0_SET_FALCON19 0x054c +#define NVC3C0_SET_FALCON19_V 31:0 + +#define NVC3C0_SET_FALCON20 0x0550 +#define NVC3C0_SET_FALCON20_V 31:0 + +#define NVC3C0_SET_FALCON21 0x0554 +#define NVC3C0_SET_FALCON21_V 31:0 + +#define NVC3C0_SET_FALCON22 0x0558 +#define NVC3C0_SET_FALCON22_V 31:0 + +#define NVC3C0_SET_FALCON23 0x055c +#define NVC3C0_SET_FALCON23_V 31:0 + +#define NVC3C0_SET_FALCON24 0x0560 +#define NVC3C0_SET_FALCON24_V 31:0 + +#define NVC3C0_SET_FALCON25 0x0564 +#define NVC3C0_SET_FALCON25_V 31:0 + +#define NVC3C0_SET_FALCON26 0x0568 +#define NVC3C0_SET_FALCON26_V 31:0 + +#define NVC3C0_SET_FALCON27 0x056c +#define NVC3C0_SET_FALCON27_V 31:0 + +#define NVC3C0_SET_FALCON28 0x0570 +#define NVC3C0_SET_FALCON28_V 31:0 + +#define NVC3C0_SET_FALCON29 0x0574 +#define NVC3C0_SET_FALCON29_V 31:0 + +#define NVC3C0_SET_FALCON30 0x0578 +#define NVC3C0_SET_FALCON30_V 31:0 + +#define NVC3C0_SET_FALCON31 0x057c +#define NVC3C0_SET_FALCON31_V 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC3C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC3C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC3C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC3C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC3C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC3C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC3C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC3C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC3C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC3C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC3C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC3C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC3C0_PIPE_NOP 0x1a2c +#define NVC3C0_PIPE_NOP_V 31:0 + +#define NVC3C0_SET_SPARE00 0x1a30 +#define NVC3C0_SET_SPARE00_V 31:0 + +#define NVC3C0_SET_SPARE01 0x1a34 +#define NVC3C0_SET_SPARE01_V 31:0 + +#define NVC3C0_SET_SPARE02 0x1a38 +#define NVC3C0_SET_SPARE02_V 31:0 + +#define NVC3C0_SET_SPARE03 0x1a3c +#define NVC3C0_SET_SPARE03_V 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC3C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC3C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC3C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC3C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC3C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC3C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC3C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC3C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC3C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_volta_compute_a_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/clc3c0qmd.h b/src/nouveau/nvidia-headers/classes/clc3c0qmd.h new file mode 100644 index 0000000..fe6e4be --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc3c0qmd.h @@ -0,0 +1,245 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC3C0QMD_H__ +#define __CLC3C0QMD_H__ + +/* +** Queue Meta Data, Version 02_02 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC3C0_QMDV02_02_OUTER_PUT MW(30:0) +#define NVC3C0_QMDV02_02_OUTER_OVERFLOW MW(31:31) +#define NVC3C0_QMDV02_02_OUTER_GET MW(62:32) +#define NVC3C0_QMDV02_02_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC3C0_QMDV02_02_INNER_GET MW(94:64) +#define NVC3C0_QMDV02_02_INNER_OVERFLOW MW(95:95) +#define NVC3C0_QMDV02_02_INNER_PUT MW(126:96) +#define NVC3C0_QMDV02_02_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC3C0_QMDV02_02_QMD_GROUP_ID MW(133:128) +#define NVC3C0_QMDV02_02_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_IS_QUEUE MW(136:136) +#define NVC3C0_QMDV02_02_IS_QUEUE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_IS_QUEUE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_QMD_RESERVED_B MW(159:144) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC3C0_QMDV02_02_QMD_RESERVED_C MW(185:185) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC3C0_QMDV02_02_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC3C0_QMDV02_02_PROGRAM_OFFSET MW(287:256) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC3C0_QMDV02_02_QMD_RESERVED_D MW(335:328) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE MW(369:368) +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC3C0_QMDV02_02_SAMPLER_INDEX MW(382:382) +#define NVC3C0_QMDV02_02_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC3C0_QMDV02_02_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC3C0_QMDV02_02_CTA_RASTER_WIDTH MW(415:384) +#define NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT MW(431:416) +#define NVC3C0_QMDV02_02_QMD_RESERVED13A MW(447:432) +#define NVC3C0_QMDV02_02_CTA_RASTER_DEPTH MW(463:448) +#define NVC3C0_QMDV02_02_QMD_RESERVED14A MW(479:464) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC3C0_QMDV02_02_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC3C0_QMDV02_02_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC3C0_QMDV02_02_SHARED_MEMORY_SIZE MW(561:544) +#define NVC3C0_QMDV02_02_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC3C0_QMDV02_02_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC3C0_QMDV02_02_QMD_VERSION MW(579:576) +#define NVC3C0_QMDV02_02_QMD_MAJOR_VERSION MW(583:580) +#define NVC3C0_QMDV02_02_QMD_RESERVED_H MW(591:584) +#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_REGISTER_COUNT_V MW(656:648) +#define NVC3C0_QMDV02_02_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC3C0_QMDV02_02_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC3C0_QMDV02_02_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC3C0_QMDV02_02_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC3C0_QMDV02_02_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC3C0_QMDV02_02_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC3C0_QMDV02_02_QMD_RESERVED_J MW(783:776) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_QMDV02_02_QMD_RESERVED_K MW(791:791) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_PAYLOAD MW(831:800) +#define NVC3C0_QMDV02_02_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC3C0_QMDV02_02_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC3C0_QMDV02_02_QMD_RESERVED_L MW(879:872) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_QMDV02_02_QMD_RESERVED_M MW(887:887) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_PAYLOAD MW(927:896) +#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC3C0_QMDV02_02_QMD_RESERVED_N MW(954:952) +#define NVC3C0_QMDV02_02_BARRIER_COUNT MW(959:955) +#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC3C0_QMDV02_02_REGISTER_COUNT MW(991:984) +#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC3C0_QMDV02_02_SASS_VERSION MW(1023:1016) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC3C0_QMDV02_02_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC3C0_QMDV02_02_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC3C0_QMDV02_02_QMD_RESERVED_S MW(1599:1585) +#define NVC3C0_QMDV02_02_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC3C0_QMDV02_02_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC3C0_QMDV02_02_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC3C0_QMDV02_02_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC3C0_QMDV02_02_QMD_RESERVED_Q MW(1694:1694) +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC3C0_QMDV02_02_QMD_SPARE_G MW(1759:1728) +#define NVC3C0_QMDV02_02_QMD_SPARE_H MW(1791:1760) +#define NVC3C0_QMDV02_02_QMD_SPARE_I MW(1823:1792) +#define NVC3C0_QMDV02_02_QMD_SPARE_J MW(1855:1824) +#define NVC3C0_QMDV02_02_QMD_SPARE_K MW(1887:1856) +#define NVC3C0_QMDV02_02_QMD_SPARE_L MW(1919:1888) +#define NVC3C0_QMDV02_02_QMD_SPARE_M MW(1951:1920) +#define NVC3C0_QMDV02_02_QMD_SPARE_N MW(1983:1952) +#define NVC3C0_QMDV02_02_DEBUG_ID_UPPER MW(2015:1984) +#define NVC3C0_QMDV02_02_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC3C0QMD_H__ diff --git a/src/nouveau/nvidia-headers/classes/clc4c0qmd.h b/src/nouveau/nvidia-headers/classes/clc4c0qmd.h new file mode 100644 index 0000000..868278e --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc4c0qmd.h @@ -0,0 +1,245 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC4C0QMD_H__ +#define __CLC4C0QMD_H__ + +/* +** Queue Meta Data, Version 02_02 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC4C0_QMDV02_02_OUTER_PUT MW(30:0) +#define NVC4C0_QMDV02_02_OUTER_OVERFLOW MW(31:31) +#define NVC4C0_QMDV02_02_OUTER_GET MW(62:32) +#define NVC4C0_QMDV02_02_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC4C0_QMDV02_02_INNER_GET MW(94:64) +#define NVC4C0_QMDV02_02_INNER_OVERFLOW MW(95:95) +#define NVC4C0_QMDV02_02_INNER_PUT MW(126:96) +#define NVC4C0_QMDV02_02_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC4C0_QMDV02_02_QMD_GROUP_ID MW(133:128) +#define NVC4C0_QMDV02_02_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC4C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC4C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_IS_QUEUE MW(136:136) +#define NVC4C0_QMDV02_02_IS_QUEUE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_IS_QUEUE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC4C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC4C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC4C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC4C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC4C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC4C0_QMDV02_02_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC4C0_QMDV02_02_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC4C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC4C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_QMD_RESERVED_B MW(159:144) +#define NVC4C0_QMDV02_02_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC4C0_QMDV02_02_QMD_RESERVED_C MW(185:185) +#define NVC4C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC4C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC4C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC4C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC4C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC4C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC4C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC4C0_QMDV02_02_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC4C0_QMDV02_02_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC4C0_QMDV02_02_PROGRAM_OFFSET MW(287:256) +#define NVC4C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC4C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC4C0_QMDV02_02_QMD_RESERVED_D MW(335:328) +#define NVC4C0_QMDV02_02_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC4C0_QMDV02_02_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC4C0_QMDV02_02_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC4C0_QMDV02_02_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC4C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC4C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC4C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC4C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_CWD_MEMBAR_TYPE MW(369:368) +#define NVC4C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC4C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC4C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC4C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC4C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC4C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC4C0_QMDV02_02_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC4C0_QMDV02_02_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC4C0_QMDV02_02_SAMPLER_INDEX MW(382:382) +#define NVC4C0_QMDV02_02_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC4C0_QMDV02_02_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC4C0_QMDV02_02_CTA_RASTER_WIDTH MW(415:384) +#define NVC4C0_QMDV02_02_CTA_RASTER_HEIGHT MW(431:416) +#define NVC4C0_QMDV02_02_QMD_RESERVED13A MW(447:432) +#define NVC4C0_QMDV02_02_CTA_RASTER_DEPTH MW(463:448) +#define NVC4C0_QMDV02_02_QMD_RESERVED14A MW(479:464) +#define NVC4C0_QMDV02_02_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC4C0_QMDV02_02_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC4C0_QMDV02_02_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC4C0_QMDV02_02_SHARED_MEMORY_SIZE MW(561:544) +#define NVC4C0_QMDV02_02_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC4C0_QMDV02_02_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC4C0_QMDV02_02_QMD_VERSION MW(579:576) +#define NVC4C0_QMDV02_02_QMD_MAJOR_VERSION MW(583:580) +#define NVC4C0_QMDV02_02_QMD_RESERVED_H MW(591:584) +#define NVC4C0_QMDV02_02_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC4C0_QMDV02_02_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC4C0_QMDV02_02_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC4C0_QMDV02_02_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC4C0_QMDV02_02_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_REGISTER_COUNT_V MW(656:648) +#define NVC4C0_QMDV02_02_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC4C0_QMDV02_02_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC4C0_QMDV02_02_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC4C0_QMDV02_02_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC4C0_QMDV02_02_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC4C0_QMDV02_02_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC4C0_QMDV02_02_QMD_RESERVED_J MW(783:776) +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC4C0_QMDV02_02_QMD_RESERVED_K MW(791:791) +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC4C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC4C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC4C0_QMDV02_02_RELEASE0_PAYLOAD MW(831:800) +#define NVC4C0_QMDV02_02_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC4C0_QMDV02_02_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC4C0_QMDV02_02_QMD_RESERVED_L MW(879:872) +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC4C0_QMDV02_02_QMD_RESERVED_M MW(887:887) +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC4C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC4C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC4C0_QMDV02_02_RELEASE1_PAYLOAD MW(927:896) +#define NVC4C0_QMDV02_02_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC4C0_QMDV02_02_QMD_RESERVED_N MW(954:952) +#define NVC4C0_QMDV02_02_BARRIER_COUNT MW(959:955) +#define NVC4C0_QMDV02_02_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC4C0_QMDV02_02_REGISTER_COUNT MW(991:984) +#define NVC4C0_QMDV02_02_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC4C0_QMDV02_02_SASS_VERSION MW(1023:1016) +#define NVC4C0_QMDV02_02_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC4C0_QMDV02_02_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC4C0_QMDV02_02_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC4C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC4C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC4C0_QMDV02_02_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC4C0_QMDV02_02_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC4C0_QMDV02_02_QMD_RESERVED_S MW(1599:1585) +#define NVC4C0_QMDV02_02_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC4C0_QMDV02_02_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC4C0_QMDV02_02_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC4C0_QMDV02_02_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC4C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC4C0_QMDV02_02_QMD_RESERVED_Q MW(1694:1694) +#define NVC4C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC4C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC4C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC4C0_QMDV02_02_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC4C0_QMDV02_02_QMD_SPARE_G MW(1759:1728) +#define NVC4C0_QMDV02_02_QMD_SPARE_H MW(1791:1760) +#define NVC4C0_QMDV02_02_QMD_SPARE_I MW(1823:1792) +#define NVC4C0_QMDV02_02_QMD_SPARE_J MW(1855:1824) +#define NVC4C0_QMDV02_02_QMD_SPARE_K MW(1887:1856) +#define NVC4C0_QMDV02_02_QMD_SPARE_L MW(1919:1888) +#define NVC4C0_QMDV02_02_QMD_SPARE_M MW(1951:1920) +#define NVC4C0_QMDV02_02_QMD_SPARE_N MW(1983:1952) +#define NVC4C0_QMDV02_02_DEBUG_ID_UPPER MW(2015:1984) +#define NVC4C0_QMDV02_02_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC4C0QMD_H__ diff --git a/src/nouveau/nvidia-headers/classes/clc5b5.h b/src/nouveau/nvidia-headers/classes/clc5b5.h new file mode 100644 index 0000000..cc3633e --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc5b5.h @@ -0,0 +1,282 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc5b5_h_ +#define _clc5b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define TURING_DMA_COPY_A (0x0000C5B5) + +#define NVC5B5_NOP (0x00000100) +#define NVC5B5_NOP_PARAMETER 31:0 +#define NVC5B5_PM_TRIGGER (0x00000140) +#define NVC5B5_PM_TRIGGER_V 31:0 +#define NVC5B5_SET_SEMAPHORE_A (0x00000240) +#define NVC5B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC5B5_SET_SEMAPHORE_B (0x00000244) +#define NVC5B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC5B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC5B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC5B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC5B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC5B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC5B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC5B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC5B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC5B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC5B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC5B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC5B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC5B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC5B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC5B5_LAUNCH_DMA (0x00000300) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC5B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC5B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC5B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC5B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC5B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2 20:20 +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC5B5_LAUNCH_DMA_SRC_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2 21:21 +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVC5B5_LAUNCH_DMA_DST_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVC5B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC5B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC5B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC5B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC5B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC5B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC5B5_OFFSET_IN_UPPER (0x00000400) +#define NVC5B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC5B5_OFFSET_IN_LOWER (0x00000404) +#define NVC5B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC5B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC5B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC5B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC5B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC5B5_PITCH_IN (0x00000410) +#define NVC5B5_PITCH_IN_VALUE 31:0 +#define NVC5B5_PITCH_OUT (0x00000414) +#define NVC5B5_PITCH_OUT_VALUE 31:0 +#define NVC5B5_LINE_LENGTH_IN (0x00000418) +#define NVC5B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC5B5_LINE_COUNT (0x0000041C) +#define NVC5B5_LINE_COUNT_VALUE 31:0 +#define NVC5B5_SET_REMAP_CONST_A (0x00000700) +#define NVC5B5_SET_REMAP_CONST_A_V 31:0 +#define NVC5B5_SET_REMAP_CONST_B (0x00000704) +#define NVC5B5_SET_REMAP_CONST_B_V 31:0 +#define NVC5B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC5B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC5B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC5B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC5B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC5B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC5B5_SET_DST_WIDTH (0x00000710) +#define NVC5B5_SET_DST_WIDTH_V 31:0 +#define NVC5B5_SET_DST_HEIGHT (0x00000714) +#define NVC5B5_SET_DST_HEIGHT_V 31:0 +#define NVC5B5_SET_DST_DEPTH (0x00000718) +#define NVC5B5_SET_DST_DEPTH_V 31:0 +#define NVC5B5_SET_DST_LAYER (0x0000071C) +#define NVC5B5_SET_DST_LAYER_V 31:0 +#define NVC5B5_SET_DST_ORIGIN (0x00000720) +#define NVC5B5_SET_DST_ORIGIN_X 15:0 +#define NVC5B5_SET_DST_ORIGIN_Y 31:16 +#define NVC5B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC5B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC5B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC5B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC5B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC5B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC5B5_SET_SRC_WIDTH (0x0000072C) +#define NVC5B5_SET_SRC_WIDTH_V 31:0 +#define NVC5B5_SET_SRC_HEIGHT (0x00000730) +#define NVC5B5_SET_SRC_HEIGHT_V 31:0 +#define NVC5B5_SET_SRC_DEPTH (0x00000734) +#define NVC5B5_SET_SRC_DEPTH_V 31:0 +#define NVC5B5_SET_SRC_LAYER (0x00000738) +#define NVC5B5_SET_SRC_LAYER_V 31:0 +#define NVC5B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC5B5_SET_SRC_ORIGIN_X 15:0 +#define NVC5B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC5B5_SRC_ORIGIN_X (0x00000744) +#define NVC5B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC5B5_SRC_ORIGIN_Y (0x00000748) +#define NVC5B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC5B5_DST_ORIGIN_X (0x0000074C) +#define NVC5B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC5B5_DST_ORIGIN_Y (0x00000750) +#define NVC5B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC5B5_PM_TRIGGER_END (0x00001114) +#define NVC5B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc5b5_h + diff --git a/src/nouveau/nvidia-headers/classes/clc5c0.h b/src/nouveau/nvidia-headers/classes/clc5c0.h new file mode 100644 index 0000000..88060cd --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc5c0.h @@ -0,0 +1,731 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_turing_compute_a_h_ +#define _cl_turing_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl turing_compute_a */ + +#include "nvtypes.h" + +#define TURING_COMPUTE_A 0xC5C0 + +#define NVC5C0_SET_OBJECT 0x0000 +#define NVC5C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC5C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC5C0_NO_OPERATION 0x0100 +#define NVC5C0_NO_OPERATION_V 31:0 + +#define NVC5C0_SET_NOTIFY_A 0x0104 +#define NVC5C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_NOTIFY_B 0x0108 +#define NVC5C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_NOTIFY 0x010c +#define NVC5C0_NOTIFY_TYPE 31:0 +#define NVC5C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC5C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC5C0_WAIT_FOR_IDLE 0x0110 +#define NVC5C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC5C0_SEND_GO_IDLE 0x013c +#define NVC5C0_SEND_GO_IDLE_V 31:0 + +#define NVC5C0_PM_TRIGGER 0x0140 +#define NVC5C0_PM_TRIGGER_V 31:0 + +#define NVC5C0_PM_TRIGGER_WFI 0x0144 +#define NVC5C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC5C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC5C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC5C0_LINE_LENGTH_IN 0x0180 +#define NVC5C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC5C0_LINE_COUNT 0x0184 +#define NVC5C0_LINE_COUNT_VALUE 31:0 + +#define NVC5C0_OFFSET_OUT_UPPER 0x0188 +#define NVC5C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC5C0_OFFSET_OUT 0x018c +#define NVC5C0_OFFSET_OUT_VALUE 31:0 + +#define NVC5C0_PITCH_OUT 0x0190 +#define NVC5C0_PITCH_OUT_VALUE 31:0 + +#define NVC5C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC5C0_SET_DST_WIDTH 0x0198 +#define NVC5C0_SET_DST_WIDTH_V 31:0 + +#define NVC5C0_SET_DST_HEIGHT 0x019c +#define NVC5C0_SET_DST_HEIGHT_V 31:0 + +#define NVC5C0_SET_DST_DEPTH 0x01a0 +#define NVC5C0_SET_DST_DEPTH_V 31:0 + +#define NVC5C0_SET_DST_LAYER 0x01a4 +#define NVC5C0_SET_DST_LAYER_V 31:0 + +#define NVC5C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC5C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC5C0_LAUNCH_DMA 0x01b0 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC5C0_LOAD_INLINE_DATA 0x01b4 +#define NVC5C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC5C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC5C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC5C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC5C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC5C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC5C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC5C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC5C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC5C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC5C0_PERFMON_TRANSFER 0x0210 +#define NVC5C0_PERFMON_TRANSFER_V 31:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC5C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC5C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC5C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC5C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC5C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC5C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC5C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC5C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC5C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC5C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC5C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC5C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC5C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC5C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC5C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC5C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC5C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC5C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC5C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC5C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC5C0_SET_SCG_CONTROL 0x0270 +#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC5C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC5C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC5C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_SET_QMD_VERSION 0x0288 +#define NVC5C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC5C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_CHECK_QMD_VERSION 0x0290 +#define NVC5C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC5C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC5C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC5C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC5C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC5C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC5C0_SEND_PCAS_A 0x02b4 +#define NVC5C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC5C0_SEND_PCAS_B 0x02b8 +#define NVC5C0_SEND_PCAS_B_FROM 23:0 +#define NVC5C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC5C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC5C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC5C0_SET_SPA_VERSION 0x0310 +#define NVC5C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC5C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC5C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC5C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC5C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC5C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC5C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC5C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC5C0_SET_FALCON00 0x0500 +#define NVC5C0_SET_FALCON00_V 31:0 + +#define NVC5C0_SET_FALCON01 0x0504 +#define NVC5C0_SET_FALCON01_V 31:0 + +#define NVC5C0_SET_FALCON02 0x0508 +#define NVC5C0_SET_FALCON02_V 31:0 + +#define NVC5C0_SET_FALCON03 0x050c +#define NVC5C0_SET_FALCON03_V 31:0 + +#define NVC5C0_SET_FALCON04 0x0510 +#define NVC5C0_SET_FALCON04_V 31:0 + +#define NVC5C0_SET_FALCON05 0x0514 +#define NVC5C0_SET_FALCON05_V 31:0 + +#define NVC5C0_SET_FALCON06 0x0518 +#define NVC5C0_SET_FALCON06_V 31:0 + +#define NVC5C0_SET_FALCON07 0x051c +#define NVC5C0_SET_FALCON07_V 31:0 + +#define NVC5C0_SET_FALCON08 0x0520 +#define NVC5C0_SET_FALCON08_V 31:0 + +#define NVC5C0_SET_FALCON09 0x0524 +#define NVC5C0_SET_FALCON09_V 31:0 + +#define NVC5C0_SET_FALCON10 0x0528 +#define NVC5C0_SET_FALCON10_V 31:0 + +#define NVC5C0_SET_FALCON11 0x052c +#define NVC5C0_SET_FALCON11_V 31:0 + +#define NVC5C0_SET_FALCON12 0x0530 +#define NVC5C0_SET_FALCON12_V 31:0 + +#define NVC5C0_SET_FALCON13 0x0534 +#define NVC5C0_SET_FALCON13_V 31:0 + +#define NVC5C0_SET_FALCON14 0x0538 +#define NVC5C0_SET_FALCON14_V 31:0 + +#define NVC5C0_SET_FALCON15 0x053c +#define NVC5C0_SET_FALCON15_V 31:0 + +#define NVC5C0_SET_FALCON16 0x0540 +#define NVC5C0_SET_FALCON16_V 31:0 + +#define NVC5C0_SET_FALCON17 0x0544 +#define NVC5C0_SET_FALCON17_V 31:0 + +#define NVC5C0_SET_FALCON18 0x0548 +#define NVC5C0_SET_FALCON18_V 31:0 + +#define NVC5C0_SET_FALCON19 0x054c +#define NVC5C0_SET_FALCON19_V 31:0 + +#define NVC5C0_SET_FALCON20 0x0550 +#define NVC5C0_SET_FALCON20_V 31:0 + +#define NVC5C0_SET_FALCON21 0x0554 +#define NVC5C0_SET_FALCON21_V 31:0 + +#define NVC5C0_SET_FALCON22 0x0558 +#define NVC5C0_SET_FALCON22_V 31:0 + +#define NVC5C0_SET_FALCON23 0x055c +#define NVC5C0_SET_FALCON23_V 31:0 + +#define NVC5C0_SET_FALCON24 0x0560 +#define NVC5C0_SET_FALCON24_V 31:0 + +#define NVC5C0_SET_FALCON25 0x0564 +#define NVC5C0_SET_FALCON25_V 31:0 + +#define NVC5C0_SET_FALCON26 0x0568 +#define NVC5C0_SET_FALCON26_V 31:0 + +#define NVC5C0_SET_FALCON27 0x056c +#define NVC5C0_SET_FALCON27_V 31:0 + +#define NVC5C0_SET_FALCON28 0x0570 +#define NVC5C0_SET_FALCON28_V 31:0 + +#define NVC5C0_SET_FALCON29 0x0574 +#define NVC5C0_SET_FALCON29_V 31:0 + +#define NVC5C0_SET_FALCON30 0x0578 +#define NVC5C0_SET_FALCON30_V 31:0 + +#define NVC5C0_SET_FALCON31 0x057c +#define NVC5C0_SET_FALCON31_V 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC5C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC5C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC5C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC5C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC5C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC5C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC5C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC5C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC5C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC5C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC5C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC5C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC5C0_PIPE_NOP 0x1a2c +#define NVC5C0_PIPE_NOP_V 31:0 + +#define NVC5C0_SET_SPARE00 0x1a30 +#define NVC5C0_SET_SPARE00_V 31:0 + +#define NVC5C0_SET_SPARE01 0x1a34 +#define NVC5C0_SET_SPARE01_V 31:0 + +#define NVC5C0_SET_SPARE02 0x1a38 +#define NVC5C0_SET_SPARE02_V 31:0 + +#define NVC5C0_SET_SPARE03 0x1a3c +#define NVC5C0_SET_SPARE03_V 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC5C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC5C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC5C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC5C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC5C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC5C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC5C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC5C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC5C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_turing_compute_a_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/clc5c0qmd.h b/src/nouveau/nvidia-headers/classes/clc5c0qmd.h new file mode 100644 index 0000000..180a491 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc5c0qmd.h @@ -0,0 +1,247 @@ +/******************************************************************************* + Copyright (c) 2001-2010 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC5C0QMD_H__ +#define __CLC5C0QMD_H__ + +/* +** Queue Meta Data, Version 02_03 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC5C0_QMDV02_03_OUTER_PUT MW(30:0) +#define NVC5C0_QMDV02_03_OUTER_OVERFLOW MW(31:31) +#define NVC5C0_QMDV02_03_OUTER_GET MW(62:32) +#define NVC5C0_QMDV02_03_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC5C0_QMDV02_03_INNER_GET MW(94:64) +#define NVC5C0_QMDV02_03_INNER_OVERFLOW MW(95:95) +#define NVC5C0_QMDV02_03_INNER_PUT MW(126:96) +#define NVC5C0_QMDV02_03_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC5C0_QMDV02_03_QMD_GROUP_ID MW(133:128) +#define NVC5C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_IS_QUEUE MW(136:136) +#define NVC5C0_QMDV02_03_IS_QUEUE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_IS_QUEUE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_QMD_RESERVED_B MW(159:144) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC5C0_QMDV02_03_QMD_RESERVED_C MW(185:185) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC5C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC5C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC5C0_QMDV02_03_QMD_RESERVED_D MW(335:328) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE MW(369:368) +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC5C0_QMDV02_03_SAMPLER_INDEX MW(382:382) +#define NVC5C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC5C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC5C0_QMDV02_03_CTA_RASTER_WIDTH MW(415:384) +#define NVC5C0_QMDV02_03_CTA_RASTER_HEIGHT MW(431:416) +#define NVC5C0_QMDV02_03_QMD_RESERVED13A MW(447:432) +#define NVC5C0_QMDV02_03_CTA_RASTER_DEPTH MW(463:448) +#define NVC5C0_QMDV02_03_QMD_RESERVED14A MW(479:464) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC5C0_QMDV02_03_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC5C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) +#define NVC5C0_QMDV02_03_SHARED_MEMORY_SIZE MW(561:544) +#define NVC5C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC5C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC5C0_QMDV02_03_QMD_VERSION MW(579:576) +#define NVC5C0_QMDV02_03_QMD_MAJOR_VERSION MW(583:580) +#define NVC5C0_QMDV02_03_QMD_RESERVED_H MW(591:584) +#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_REGISTER_COUNT_V MW(656:648) +#define NVC5C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC5C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC5C0_QMDV02_03_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC5C0_QMDV02_03_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC5C0_QMDV02_03_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC5C0_QMDV02_03_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC5C0_QMDV02_03_QMD_RESERVED_J MW(783:776) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_QMDV02_03_QMD_RESERVED_K MW(791:791) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_PAYLOAD MW(831:800) +#define NVC5C0_QMDV02_03_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC5C0_QMDV02_03_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC5C0_QMDV02_03_QMD_RESERVED_L MW(879:872) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_QMDV02_03_QMD_RESERVED_M MW(887:887) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_PAYLOAD MW(927:896) +#define NVC5C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC5C0_QMDV02_03_QMD_RESERVED_N MW(954:952) +#define NVC5C0_QMDV02_03_BARRIER_COUNT MW(959:955) +#define NVC5C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC5C0_QMDV02_03_REGISTER_COUNT MW(991:984) +#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) +#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_SIZE MW(1009:1001) +#define NVC5C0_QMDV02_03_QMD_RESERVED_A MW(1015:1010) +#define NVC5C0_QMDV02_03_SASS_VERSION MW(1023:1016) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC5C0_QMDV02_03_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC5C0_QMDV02_03_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC5C0_QMDV02_03_QMD_RESERVED_S MW(1599:1585) +#define NVC5C0_QMDV02_03_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC5C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC5C0_QMDV02_03_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC5C0_QMDV02_03_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC5C0_QMDV02_03_QMD_RESERVED_Q MW(1694:1694) +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC5C0_QMDV02_03_QMD_SPARE_G MW(1759:1728) +#define NVC5C0_QMDV02_03_QMD_SPARE_H MW(1791:1760) +#define NVC5C0_QMDV02_03_QMD_SPARE_I MW(1823:1792) +#define NVC5C0_QMDV02_03_QMD_SPARE_J MW(1855:1824) +#define NVC5C0_QMDV02_03_QMD_SPARE_K MW(1887:1856) +#define NVC5C0_QMDV02_03_QMD_SPARE_L MW(1919:1888) +#define NVC5C0_QMDV02_03_QMD_SPARE_M MW(1951:1920) +#define NVC5C0_QMDV02_03_QMD_SPARE_N MW(1983:1952) +#define NVC5C0_QMDV02_03_DEBUG_ID_UPPER MW(2015:1984) +#define NVC5C0_QMDV02_03_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC5C0QMD_H__ diff --git a/src/nouveau/nvidia-headers/classes/clc6b5.h b/src/nouveau/nvidia-headers/classes/clc6b5.h new file mode 100644 index 0000000..873ca74 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc6b5.h @@ -0,0 +1,282 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc6b5_h_ +#define _clc6b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMPERE_DMA_COPY_A (0x0000C6B5) + +#define NVC6B5_NOP (0x00000100) +#define NVC6B5_NOP_PARAMETER 31:0 +#define NVC6B5_PM_TRIGGER (0x00000140) +#define NVC6B5_PM_TRIGGER_V 31:0 +#define NVC6B5_SET_SEMAPHORE_A (0x00000240) +#define NVC6B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC6B5_SET_SEMAPHORE_B (0x00000244) +#define NVC6B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC6B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC6B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC6B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC6B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC6B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC6B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC6B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC6B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC6B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC6B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC6B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC6B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC6B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC6B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC6B5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVC6B5_LAUNCH_DMA (0x00000300) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC6B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC6B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC6B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC6B5_OFFSET_IN_UPPER (0x00000400) +#define NVC6B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC6B5_OFFSET_IN_LOWER (0x00000404) +#define NVC6B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC6B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC6B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC6B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC6B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC6B5_PITCH_IN (0x00000410) +#define NVC6B5_PITCH_IN_VALUE 31:0 +#define NVC6B5_PITCH_OUT (0x00000414) +#define NVC6B5_PITCH_OUT_VALUE 31:0 +#define NVC6B5_LINE_LENGTH_IN (0x00000418) +#define NVC6B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC6B5_LINE_COUNT (0x0000041C) +#define NVC6B5_LINE_COUNT_VALUE 31:0 +#define NVC6B5_SET_REMAP_CONST_A (0x00000700) +#define NVC6B5_SET_REMAP_CONST_A_V 31:0 +#define NVC6B5_SET_REMAP_CONST_B (0x00000704) +#define NVC6B5_SET_REMAP_CONST_B_V 31:0 +#define NVC6B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC6B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC6B5_SET_DST_WIDTH (0x00000710) +#define NVC6B5_SET_DST_WIDTH_V 31:0 +#define NVC6B5_SET_DST_HEIGHT (0x00000714) +#define NVC6B5_SET_DST_HEIGHT_V 31:0 +#define NVC6B5_SET_DST_DEPTH (0x00000718) +#define NVC6B5_SET_DST_DEPTH_V 31:0 +#define NVC6B5_SET_DST_LAYER (0x0000071C) +#define NVC6B5_SET_DST_LAYER_V 31:0 +#define NVC6B5_SET_DST_ORIGIN (0x00000720) +#define NVC6B5_SET_DST_ORIGIN_X 15:0 +#define NVC6B5_SET_DST_ORIGIN_Y 31:16 +#define NVC6B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC6B5_SET_SRC_WIDTH (0x0000072C) +#define NVC6B5_SET_SRC_WIDTH_V 31:0 +#define NVC6B5_SET_SRC_HEIGHT (0x00000730) +#define NVC6B5_SET_SRC_HEIGHT_V 31:0 +#define NVC6B5_SET_SRC_DEPTH (0x00000734) +#define NVC6B5_SET_SRC_DEPTH_V 31:0 +#define NVC6B5_SET_SRC_LAYER (0x00000738) +#define NVC6B5_SET_SRC_LAYER_V 31:0 +#define NVC6B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC6B5_SET_SRC_ORIGIN_X 15:0 +#define NVC6B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC6B5_SRC_ORIGIN_X (0x00000744) +#define NVC6B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC6B5_SRC_ORIGIN_Y (0x00000748) +#define NVC6B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC6B5_DST_ORIGIN_X (0x0000074C) +#define NVC6B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC6B5_DST_ORIGIN_Y (0x00000750) +#define NVC6B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC6B5_PM_TRIGGER_END (0x00001114) +#define NVC6B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc6b5_h + diff --git a/src/nouveau/nvidia-headers/classes/clc6c0.h b/src/nouveau/nvidia-headers/classes/clc6c0.h new file mode 100644 index 0000000..35897880 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc6c0.h @@ -0,0 +1,697 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_ampere_compute_a_h_ +#define _cl_ampere_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_compute_a */ + +#include "nvtypes.h" + +#define AMPERE_COMPUTE_A 0xC6C0 + +#define NVC6C0_SET_OBJECT 0x0000 +#define NVC6C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC6C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC6C0_NO_OPERATION 0x0100 +#define NVC6C0_NO_OPERATION_V 31:0 + +#define NVC6C0_SET_NOTIFY_A 0x0104 +#define NVC6C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_NOTIFY_B 0x0108 +#define NVC6C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_NOTIFY 0x010c +#define NVC6C0_NOTIFY_TYPE 31:0 +#define NVC6C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC6C0_WAIT_FOR_IDLE 0x0110 +#define NVC6C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC6C0_SEND_GO_IDLE 0x013c +#define NVC6C0_SEND_GO_IDLE_V 31:0 + +#define NVC6C0_PM_TRIGGER 0x0140 +#define NVC6C0_PM_TRIGGER_V 31:0 + +#define NVC6C0_PM_TRIGGER_WFI 0x0144 +#define NVC6C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC6C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC6C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC6C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC6C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC6C0_LINE_LENGTH_IN 0x0180 +#define NVC6C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC6C0_LINE_COUNT 0x0184 +#define NVC6C0_LINE_COUNT_VALUE 31:0 + +#define NVC6C0_OFFSET_OUT_UPPER 0x0188 +#define NVC6C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC6C0_OFFSET_OUT 0x018c +#define NVC6C0_OFFSET_OUT_VALUE 31:0 + +#define NVC6C0_PITCH_OUT 0x0190 +#define NVC6C0_PITCH_OUT_VALUE 31:0 + +#define NVC6C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC6C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC6C0_SET_DST_WIDTH 0x0198 +#define NVC6C0_SET_DST_WIDTH_V 31:0 + +#define NVC6C0_SET_DST_HEIGHT 0x019c +#define NVC6C0_SET_DST_HEIGHT_V 31:0 + +#define NVC6C0_SET_DST_DEPTH 0x01a0 +#define NVC6C0_SET_DST_DEPTH_V 31:0 + +#define NVC6C0_SET_DST_LAYER 0x01a4 +#define NVC6C0_SET_DST_LAYER_V 31:0 + +#define NVC6C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC6C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC6C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC6C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC6C0_LAUNCH_DMA 0x01b0 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC6C0_LOAD_INLINE_DATA 0x01b4 +#define NVC6C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC6C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC6C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC6C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC6C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC6C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC6C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC6C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC6C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC6C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC6C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC6C0_PERFMON_TRANSFER 0x0210 +#define NVC6C0_PERFMON_TRANSFER_V 31:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC6C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC6C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC6C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC6C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC6C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC6C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC6C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC6C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC6C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC6C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC6C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC6C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC6C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC6C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC6C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC6C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC6C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC6C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC6C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC6C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC6C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC6C0_SET_SCG_CONTROL 0x0270 +#define NVC6C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC6C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC6C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC6C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC6C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC6C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_SET_QMD_VERSION 0x0288 +#define NVC6C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC6C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_CHECK_QMD_VERSION 0x0290 +#define NVC6C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC6C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC6C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC6C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC6C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC6C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC6C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC6C0_SEND_PCAS_A 0x02b4 +#define NVC6C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC6C0_SEND_PCAS_B 0x02b8 +#define NVC6C0_SEND_PCAS_B_FROM 23:0 +#define NVC6C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC6C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC6C0_SEND_SIGNALING_PCAS2_B 0x02c0 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION 3:0 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP 0x00000000 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE 0x00000001 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE 0x00000002 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT 0x00000006 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE 0x00000007 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH 0x00000008 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE 0x00000009 +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE 0x0000000A +#define NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING 0x0000000B + +#define NVC6C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC6C0_SET_SPA_VERSION 0x0310 +#define NVC6C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC6C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC6C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC6C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC6C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC6C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC6C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC6C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC6C0_SET_FALCON00 0x0500 +#define NVC6C0_SET_FALCON00_V 31:0 + +#define NVC6C0_SET_FALCON01 0x0504 +#define NVC6C0_SET_FALCON01_V 31:0 + +#define NVC6C0_SET_FALCON02 0x0508 +#define NVC6C0_SET_FALCON02_V 31:0 + +#define NVC6C0_SET_FALCON03 0x050c +#define NVC6C0_SET_FALCON03_V 31:0 + +#define NVC6C0_SET_FALCON04 0x0510 +#define NVC6C0_SET_FALCON04_V 31:0 + +#define NVC6C0_SET_FALCON05 0x0514 +#define NVC6C0_SET_FALCON05_V 31:0 + +#define NVC6C0_SET_FALCON06 0x0518 +#define NVC6C0_SET_FALCON06_V 31:0 + +#define NVC6C0_SET_FALCON07 0x051c +#define NVC6C0_SET_FALCON07_V 31:0 + +#define NVC6C0_SET_FALCON08 0x0520 +#define NVC6C0_SET_FALCON08_V 31:0 + +#define NVC6C0_SET_FALCON09 0x0524 +#define NVC6C0_SET_FALCON09_V 31:0 + +#define NVC6C0_SET_FALCON10 0x0528 +#define NVC6C0_SET_FALCON10_V 31:0 + +#define NVC6C0_SET_FALCON11 0x052c +#define NVC6C0_SET_FALCON11_V 31:0 + +#define NVC6C0_SET_FALCON12 0x0530 +#define NVC6C0_SET_FALCON12_V 31:0 + +#define NVC6C0_SET_FALCON13 0x0534 +#define NVC6C0_SET_FALCON13_V 31:0 + +#define NVC6C0_SET_FALCON14 0x0538 +#define NVC6C0_SET_FALCON14_V 31:0 + +#define NVC6C0_SET_FALCON15 0x053c +#define NVC6C0_SET_FALCON15_V 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC6C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC6C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC6C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC6C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC6C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC6C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC6C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC6C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC6C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC6C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC6C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC6C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC6C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC6C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC6C0_PIPE_NOP 0x1a2c +#define NVC6C0_PIPE_NOP_V 31:0 + +#define NVC6C0_SET_SPARE00 0x1a30 +#define NVC6C0_SET_SPARE00_V 31:0 + +#define NVC6C0_SET_SPARE01 0x1a34 +#define NVC6C0_SET_SPARE01_V 31:0 + +#define NVC6C0_SET_SPARE02 0x1a38 +#define NVC6C0_SET_SPARE02_V 31:0 + +#define NVC6C0_SET_SPARE03 0x1a3c +#define NVC6C0_SET_SPARE03_V 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC6C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC6C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC6C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC6C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC6C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC6C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC6C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC6C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC6C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC6C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC6C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC6C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC6C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC6C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_ampere_compute_a_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/clc6c0qmd.h b/src/nouveau/nvidia-headers/classes/clc6c0qmd.h new file mode 100644 index 0000000..e22f3fe --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc6c0qmd.h @@ -0,0 +1,763 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC6C0QMD_H__ +#define __CLC6C0QMD_H__ + +/* +** Queue Meta Data, Version 02_03 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC6C0_QMDV02_03_OUTER_PUT MW(30:0) +#define NVC6C0_QMDV02_03_OUTER_OVERFLOW MW(31:31) +#define NVC6C0_QMDV02_03_OUTER_GET MW(62:32) +#define NVC6C0_QMDV02_03_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC6C0_QMDV02_03_INNER_GET MW(94:64) +#define NVC6C0_QMDV02_03_INNER_OVERFLOW MW(95:95) +#define NVC6C0_QMDV02_03_INNER_PUT MW(126:96) +#define NVC6C0_QMDV02_03_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC6C0_QMDV02_03_QMD_GROUP_ID MW(133:128) +#define NVC6C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_IS_QUEUE MW(136:136) +#define NVC6C0_QMDV02_03_IS_QUEUE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_IS_QUEUE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_QMD_RESERVED_B MW(159:144) +#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC6C0_QMDV02_03_QMD_RESERVED_C MW(185:185) +#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC6C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) +#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC6C0_QMDV02_03_QMD_RESERVED_D MW(335:328) +#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE MW(369:368) +#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC6C0_QMDV02_03_SAMPLER_INDEX MW(382:382) +#define NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC6C0_QMDV02_03_CTA_RASTER_WIDTH MW(415:384) +#define NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT MW(431:416) +#define NVC6C0_QMDV02_03_QMD_RESERVED13A MW(447:432) +#define NVC6C0_QMDV02_03_CTA_RASTER_DEPTH MW(463:448) +#define NVC6C0_QMDV02_03_QMD_RESERVED14A MW(479:464) +#define NVC6C0_QMDV02_03_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC6C0_QMDV02_03_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC6C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) +#define NVC6C0_QMDV02_03_SHARED_MEMORY_SIZE MW(561:544) +#define NVC6C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC6C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC6C0_QMDV02_03_QMD_VERSION MW(579:576) +#define NVC6C0_QMDV02_03_QMD_MAJOR_VERSION MW(583:580) +#define NVC6C0_QMDV02_03_QMD_RESERVED_H MW(591:584) +#define NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_REGISTER_COUNT_V MW(656:648) +#define NVC6C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC6C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC6C0_QMDV02_03_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC6C0_QMDV02_03_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC6C0_QMDV02_03_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC6C0_QMDV02_03_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC6C0_QMDV02_03_QMD_RESERVED_J MW(783:776) +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_QMDV02_03_QMD_RESERVED_K MW(791:791) +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_QMDV02_03_RELEASE0_PAYLOAD MW(831:800) +#define NVC6C0_QMDV02_03_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC6C0_QMDV02_03_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC6C0_QMDV02_03_QMD_RESERVED_L MW(879:872) +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_QMDV02_03_QMD_RESERVED_M MW(887:887) +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_QMDV02_03_RELEASE1_PAYLOAD MW(927:896) +#define NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC6C0_QMDV02_03_QMD_RESERVED_N MW(954:952) +#define NVC6C0_QMDV02_03_BARRIER_COUNT MW(959:955) +#define NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC6C0_QMDV02_03_REGISTER_COUNT MW(991:984) +#define NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) +#define NVC6C0_QMDV02_03_PROGRAM_PREFETCH_SIZE MW(1009:1001) +#define NVC6C0_QMDV02_03_QMD_RESERVED_A MW(1015:1010) +#define NVC6C0_QMDV02_03_SASS_VERSION MW(1023:1016) +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC6C0_QMDV02_03_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC6C0_QMDV02_03_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC6C0_QMDV02_03_QMD_RESERVED_S MW(1599:1585) +#define NVC6C0_QMDV02_03_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC6C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC6C0_QMDV02_03_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC6C0_QMDV02_03_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC6C0_QMDV02_03_QMD_RESERVED_Q MW(1694:1694) +#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC6C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC6C0_QMDV02_03_QMD_SPARE_G MW(1759:1728) +#define NVC6C0_QMDV02_03_QMD_SPARE_H MW(1791:1760) +#define NVC6C0_QMDV02_03_QMD_SPARE_I MW(1823:1792) +#define NVC6C0_QMDV02_03_QMD_SPARE_J MW(1855:1824) +#define NVC6C0_QMDV02_03_QMD_SPARE_K MW(1887:1856) +#define NVC6C0_QMDV02_03_QMD_SPARE_L MW(1919:1888) +#define NVC6C0_QMDV02_03_QMD_SPARE_M MW(1951:1920) +#define NVC6C0_QMDV02_03_QMD_SPARE_N MW(1983:1952) +#define NVC6C0_QMDV02_03_DEBUG_ID_UPPER MW(2015:1984) +#define NVC6C0_QMDV02_03_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_04 + */ + +#define NVC6C0_QMDV02_04_OUTER_PUT MW(30:0) +#define NVC6C0_QMDV02_04_OUTER_OVERFLOW MW(31:31) +#define NVC6C0_QMDV02_04_OUTER_GET MW(62:32) +#define NVC6C0_QMDV02_04_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC6C0_QMDV02_04_INNER_GET MW(94:64) +#define NVC6C0_QMDV02_04_INNER_OVERFLOW MW(95:95) +#define NVC6C0_QMDV02_04_INNER_PUT MW(126:96) +#define NVC6C0_QMDV02_04_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC6C0_QMDV02_04_QMD_GROUP_ID MW(133:128) +#define NVC6C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_IS_QUEUE MW(136:136) +#define NVC6C0_QMDV02_04_IS_QUEUE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_IS_QUEUE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE MW(141:141) +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION MW(144:142) +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH MW(145:145) +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE MW(146:146) +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION MW(149:147) +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH MW(150:150) +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_DEPENDENCE_COUNTER MW(157:151) +#define NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION MW(158:158) +#define NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_QMD_RESERVED_B MW(159:159) +#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC6C0_QMDV02_04_DEMOTE_L2_EVICT_LAST MW(185:185) +#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC6C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) +#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC6C0_QMDV02_04_QMD_RESERVED_D MW(335:328) +#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE MW(369:368) +#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC6C0_QMDV02_04_SAMPLER_INDEX MW(382:382) +#define NVC6C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC6C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE MW(383:383) +#define NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_CTA_RASTER_WIDTH MW(415:384) +#define NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT MW(431:416) +#define NVC6C0_QMDV02_04_QMD_RESERVED13A MW(447:432) +#define NVC6C0_QMDV02_04_CTA_RASTER_DEPTH MW(463:448) +#define NVC6C0_QMDV02_04_QMD_RESERVED14A MW(479:464) +#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_POINTER MW(511:480) +#define NVC6C0_QMDV02_04_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC6C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) +#define NVC6C0_QMDV02_04_SHARED_MEMORY_SIZE MW(561:544) +#define NVC6C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC6C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC6C0_QMDV02_04_QMD_VERSION MW(579:576) +#define NVC6C0_QMDV02_04_QMD_MAJOR_VERSION MW(583:580) +#define NVC6C0_QMDV02_04_QMD_RESERVED_H MW(591:584) +#define NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_REGISTER_COUNT_V MW(656:648) +#define NVC6C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC6C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC6C0_QMDV02_04_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC6C0_QMDV02_04_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC6C0_QMDV02_04_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC6C0_QMDV02_04_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC6C0_QMDV02_04_QMD_RESERVED_J MW(783:776) +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_QMDV02_04_QMD_RESERVED_K MW(791:791) +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_QMDV02_04_RELEASE0_PAYLOAD MW(831:800) +#define NVC6C0_QMDV02_04_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC6C0_QMDV02_04_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC6C0_QMDV02_04_QMD_RESERVED_L MW(879:872) +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_QMDV02_04_QMD_RESERVED_M MW(887:887) +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC6C0_QMDV02_04_RELEASE1_PAYLOAD MW(927:896) +#define NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC6C0_QMDV02_04_QMD_RESERVED_N MW(954:952) +#define NVC6C0_QMDV02_04_BARRIER_COUNT MW(959:955) +#define NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC6C0_QMDV02_04_QMD_RESERVED_G MW(991:984) +#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) +#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_SIZE MW(1009:1001) +#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE MW(1011:1010) +#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 +#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 +#define NVC6C0_QMDV02_04_QMD_RESERVED_A MW(1015:1012) +#define NVC6C0_QMDV02_04_SASS_VERSION MW(1023:1016) +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC6C0_QMDV02_04_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC6C0_QMDV02_04_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC6C0_QMDV02_04_QMD_RESERVED_S MW(1599:1585) +#define NVC6C0_QMDV02_04_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC6C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC6C0_QMDV02_04_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC6C0_QMDV02_04_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC6C0_QMDV02_04_QMD_RESERVED_Q MW(1694:1694) +#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC6C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC6C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER MW(1734:1728) +#define NVC6C0_QMDV02_04_QMD_RESERVED_I MW(1759:1735) +#define NVC6C0_QMDV02_04_QMD_SPARE_H MW(1791:1760) +#define NVC6C0_QMDV02_04_QMD_SPARE_I MW(1823:1792) +#define NVC6C0_QMDV02_04_QMD_SPARE_J MW(1855:1824) +#define NVC6C0_QMDV02_04_QMD_SPARE_K MW(1887:1856) +#define NVC6C0_QMDV02_04_QMD_SPARE_L MW(1919:1888) +#define NVC6C0_QMDV02_04_QMD_SPARE_M MW(1951:1920) +#define NVC6C0_QMDV02_04_QMD_SPARE_N MW(1983:1952) +#define NVC6C0_QMDV02_04_DEBUG_ID_UPPER MW(2015:1984) +#define NVC6C0_QMDV02_04_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 03_00 + */ + +#define NVC6C0_QMDV03_00_OUTER_PUT MW(30:0) +#define NVC6C0_QMDV03_00_OUTER_OVERFLOW MW(31:31) +#define NVC6C0_QMDV03_00_OUTER_GET MW(62:32) +#define NVC6C0_QMDV03_00_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC6C0_QMDV03_00_INNER_GET MW(94:64) +#define NVC6C0_QMDV03_00_INNER_OVERFLOW MW(95:95) +#define NVC6C0_QMDV03_00_INNER_PUT MW(126:96) +#define NVC6C0_QMDV03_00_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC6C0_QMDV03_00_QMD_GROUP_ID MW(133:128) +#define NVC6C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_IS_QUEUE MW(136:136) +#define NVC6C0_QMDV03_00_IS_QUEUE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_IS_QUEUE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_QMD_RESERVED04A MW(139:138) +#define NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_QMD_RESERVED04B MW(141:141) +#define NVC6C0_QMDV03_00_DEPENDENCE_COUNTER MW(157:142) +#define NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION MW(158:158) +#define NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_QMD_RESERVED04C MW(159:159) +#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC6C0_QMDV03_00_DEMOTE_L2_EVICT_LAST MW(185:185) +#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC6C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) +#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC6C0_QMDV03_00_QMD_RESERVED_D MW(335:328) +#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC6C0_QMDV03_00_QMD_RESERVED11A MW(366:366) +#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE MW(369:368) +#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_QMD_RESERVED11B MW(377:372) +#define NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC6C0_QMDV03_00_QMD_RESERVED11C MW(381:379) +#define NVC6C0_QMDV03_00_SAMPLER_INDEX MW(382:382) +#define NVC6C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC6C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE MW(383:383) +#define NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_CTA_RASTER_WIDTH MW(415:384) +#define NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT MW(431:416) +#define NVC6C0_QMDV03_00_CTA_RASTER_DEPTH MW(463:448) +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_POINTER MW(511:480) +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE MW(512:512) +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION MW(515:513) +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH MW(516:516) +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE MW(517:517) +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION MW(520:518) +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH MW(521:521) +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC6C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) +#define NVC6C0_QMDV03_00_SHARED_MEMORY_SIZE MW(561:544) +#define NVC6C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(567:562) +#define NVC6C0_QMDV03_00_QMD_RESERVED17A MW(568:568) +#define NVC6C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(574:569) +#define NVC6C0_QMDV03_00_QMD_RESERVED17B MW(575:575) +#define NVC6C0_QMDV03_00_QMD_VERSION MW(579:576) +#define NVC6C0_QMDV03_00_QMD_MAJOR_VERSION MW(583:580) +#define NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_REGISTER_COUNT_V MW(656:648) +#define NVC6C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(662:657) +#define NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE MW(663:663) +#define NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC6C0_QMDV03_00_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC6C0_QMDV03_00_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(759:736) +#define NVC6C0_QMDV03_00_BARRIER_COUNT MW(767:763) +#define NVC6C0_QMDV03_00_RELEASE0_ADDRESS_LOWER MW(799:768) +#define NVC6C0_QMDV03_00_RELEASE0_ADDRESS_UPPER MW(807:800) +#define NVC6C0_QMDV03_00_SEMAPHORE_RESERVED25A MW(818:808) +#define NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE MW(819:819) +#define NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP MW(822:820) +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_QMDV03_00_RELEASE0_ENABLE MW(823:823) +#define NVC6C0_QMDV03_00_RELEASE0_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE0_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT MW(825:824) +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE MW(826:826) +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE MW(828:827) +#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_NONE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_TRAP 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP 0x00000002 +#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B MW(829:829) +#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE MW(831:830) +#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER MW(863:832) +#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER MW(895:864) +#define NVC6C0_QMDV03_00_RELEASE1_ADDRESS_LOWER MW(927:896) +#define NVC6C0_QMDV03_00_RELEASE1_ADDRESS_UPPER MW(935:928) +#define NVC6C0_QMDV03_00_SEMAPHORE_RESERVED29A MW(946:936) +#define NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE MW(947:947) +#define NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP MW(950:948) +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_QMDV03_00_RELEASE1_ENABLE MW(951:951) +#define NVC6C0_QMDV03_00_RELEASE1_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE1_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT MW(953:952) +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE MW(954:954) +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE MW(956:955) +#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_NONE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_TRAP 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP 0x00000002 +#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B MW(957:957) +#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE MW(959:958) +#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER MW(991:960) +#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER MW(1023:992) +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC6C0_QMDV03_00_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC6C0_QMDV03_00_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1623:1600) +#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1640:1632) +#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_SIZE MW(1649:1641) +#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE MW(1651:1650) +#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 +#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 +#define NVC6C0_QMDV03_00_SASS_VERSION MW(1663:1656) +#define NVC6C0_QMDV03_00_RELEASE2_ADDRESS_LOWER MW(1695:1664) +#define NVC6C0_QMDV03_00_RELEASE2_ADDRESS_UPPER MW(1703:1696) +#define NVC6C0_QMDV03_00_SEMAPHORE_RESERVED53A MW(1714:1704) +#define NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE MW(1715:1715) +#define NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP MW(1718:1716) +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC 0x00000003 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND 0x00000005 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR 0x00000006 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC6C0_QMDV03_00_RELEASE2_ENABLE MW(1719:1719) +#define NVC6C0_QMDV03_00_RELEASE2_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE2_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT MW(1721:1720) +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE MW(1722:1722) +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE MW(1724:1723) +#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_NONE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_TRAP 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP 0x00000002 +#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B MW(1725:1725) +#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE MW(1727:1726) +#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER MW(1759:1728) +#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER MW(1791:1760) +#define NVC6C0_QMDV03_00_QMD_SPARE_I MW(1823:1792) +#define NVC6C0_QMDV03_00_HW_ONLY_INNER_GET MW(1854:1824) +#define NVC6C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1855:1855) +#define NVC6C0_QMDV03_00_HW_ONLY_INNER_PUT MW(1886:1856) +#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1917:1888) +#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1919:1919) +#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC6C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1951:1920) +#define NVC6C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER MW(1958:1952) +#define NVC6C0_QMDV03_00_DEBUG_ID_UPPER MW(2015:1984) +#define NVC6C0_QMDV03_00_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC6C0QMD_H__ diff --git a/src/nouveau/nvidia-headers/classes/clc7b5.h b/src/nouveau/nvidia-headers/classes/clc7b5.h new file mode 100644 index 0000000..df331e8 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc7b5.h @@ -0,0 +1,304 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "nvtypes.h" + +#ifndef _clc7b5_h_ +#define _clc7b5_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMPERE_DMA_COPY_B (0x0000C7B5) + +#define NVC7B5_NOP (0x00000100) +#define NVC7B5_NOP_PARAMETER 31:0 +#define NVC7B5_PM_TRIGGER (0x00000140) +#define NVC7B5_PM_TRIGGER_V 31:0 +#define NVC7B5_SET_MONITORED_FENCE_TYPE (0x0000021C) +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE 0:0 +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE (0x00000000) +#define NVC7B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT (0x00000001) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER (0x00000220) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER 16:0 +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER (0x00000224) +#define NVC7B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER 31:0 +#define NVC7B5_SET_SEMAPHORE_A (0x00000240) +#define NVC7B5_SET_SEMAPHORE_A_UPPER 16:0 +#define NVC7B5_SET_SEMAPHORE_B (0x00000244) +#define NVC7B5_SET_SEMAPHORE_B_LOWER 31:0 +#define NVC7B5_SET_SEMAPHORE_PAYLOAD (0x00000248) +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_UPPER (0x0000024C) +#define NVC7B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD 31:0 +#define NVC7B5_SET_RENDER_ENABLE_A (0x00000254) +#define NVC7B5_SET_RENDER_ENABLE_A_UPPER 7:0 +#define NVC7B5_SET_RENDER_ENABLE_B (0x00000258) +#define NVC7B5_SET_RENDER_ENABLE_B_LOWER 31:0 +#define NVC7B5_SET_RENDER_ENABLE_C (0x0000025C) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_FALSE (0x00000000) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_TRUE (0x00000001) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL (0x00000002) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL (0x00000003) +#define NVC7B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL (0x00000004) +#define NVC7B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC7B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC7B5_SET_SRC_PHYS_MODE_BASIC_KIND 5:2 +#define NVC7B5_SET_SRC_PHYS_MODE_PEER_ID 8:6 +#define NVC7B5_SET_SRC_PHYS_MODE_FLA 9:9 +#define NVC7B5_SET_DST_PHYS_MODE (0x00000264) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVC7B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003) +#define NVC7B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2 +#define NVC7B5_SET_DST_PHYS_MODE_PEER_ID 8:6 +#define NVC7B5_SET_DST_PHYS_MODE_FLA 9:9 +#define NVC7B5_LAUNCH_DMA (0x00000300) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE 25:25 +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000) +#define NVC7B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE (0x00000003) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVC7B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC7B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC7B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE 11:11 +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVC7B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVC7B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVC7B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVC7B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVC7B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA (0x00000008) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB (0x00000009) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC (0x0000000D) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD (0x0000000E) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE (0x0000000F) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_VPRMODE 23:22 +#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000) +#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001) +#define NVC7B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24 +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC 26:26 +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000) +#define NVC7B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27 +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000) +#define NVC7B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD (0x00000001) +#define NVC7B5_LAUNCH_DMA_RESERVED_ERR_CODE 31:28 +#define NVC7B5_OFFSET_IN_UPPER (0x00000400) +#define NVC7B5_OFFSET_IN_UPPER_UPPER 16:0 +#define NVC7B5_OFFSET_IN_LOWER (0x00000404) +#define NVC7B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVC7B5_OFFSET_OUT_UPPER (0x00000408) +#define NVC7B5_OFFSET_OUT_UPPER_UPPER 16:0 +#define NVC7B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVC7B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVC7B5_PITCH_IN (0x00000410) +#define NVC7B5_PITCH_IN_VALUE 31:0 +#define NVC7B5_PITCH_OUT (0x00000414) +#define NVC7B5_PITCH_OUT_VALUE 31:0 +#define NVC7B5_LINE_LENGTH_IN (0x00000418) +#define NVC7B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVC7B5_LINE_COUNT (0x0000041C) +#define NVC7B5_LINE_COUNT_VALUE 31:0 +#define NVC7B5_SET_REMAP_CONST_A (0x00000700) +#define NVC7B5_SET_REMAP_CONST_A_V 31:0 +#define NVC7B5_SET_REMAP_CONST_B (0x00000704) +#define NVC7B5_SET_REMAP_CONST_B_V 31:0 +#define NVC7B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVC7B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVC7B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE (0x0000070C) +#define NVC7B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC7B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC7B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC7B5_SET_DST_WIDTH (0x00000710) +#define NVC7B5_SET_DST_WIDTH_V 31:0 +#define NVC7B5_SET_DST_HEIGHT (0x00000714) +#define NVC7B5_SET_DST_HEIGHT_V 31:0 +#define NVC7B5_SET_DST_DEPTH (0x00000718) +#define NVC7B5_SET_DST_DEPTH_V 31:0 +#define NVC7B5_SET_DST_LAYER (0x0000071C) +#define NVC7B5_SET_DST_LAYER_V 31:0 +#define NVC7B5_SET_DST_ORIGIN (0x00000720) +#define NVC7B5_SET_DST_ORIGIN_X 15:0 +#define NVC7B5_SET_DST_ORIGIN_Y 31:16 +#define NVC7B5_SET_SRC_BLOCK_SIZE (0x00000728) +#define NVC7B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NVC7B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) +#define NVC7B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) +#define NVC7B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 +#define NVC7B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) +#define NVC7B5_SET_SRC_WIDTH (0x0000072C) +#define NVC7B5_SET_SRC_WIDTH_V 31:0 +#define NVC7B5_SET_SRC_HEIGHT (0x00000730) +#define NVC7B5_SET_SRC_HEIGHT_V 31:0 +#define NVC7B5_SET_SRC_DEPTH (0x00000734) +#define NVC7B5_SET_SRC_DEPTH_V 31:0 +#define NVC7B5_SET_SRC_LAYER (0x00000738) +#define NVC7B5_SET_SRC_LAYER_V 31:0 +#define NVC7B5_SET_SRC_ORIGIN (0x0000073C) +#define NVC7B5_SET_SRC_ORIGIN_X 15:0 +#define NVC7B5_SET_SRC_ORIGIN_Y 31:16 +#define NVC7B5_SRC_ORIGIN_X (0x00000744) +#define NVC7B5_SRC_ORIGIN_X_VALUE 31:0 +#define NVC7B5_SRC_ORIGIN_Y (0x00000748) +#define NVC7B5_SRC_ORIGIN_Y_VALUE 31:0 +#define NVC7B5_DST_ORIGIN_X (0x0000074C) +#define NVC7B5_DST_ORIGIN_X_VALUE 31:0 +#define NVC7B5_DST_ORIGIN_Y (0x00000750) +#define NVC7B5_DST_ORIGIN_Y_VALUE 31:0 +#define NVC7B5_PM_TRIGGER_END (0x00001114) +#define NVC7B5_PM_TRIGGER_END_V 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _clc7b5_h + diff --git a/src/nouveau/nvidia-headers/classes/clc7c0.h b/src/nouveau/nvidia-headers/classes/clc7c0.h new file mode 100644 index 0000000..87ad72d --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc7c0.h @@ -0,0 +1,848 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_ampere_compute_b_h_ +#define _cl_ampere_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_compute_b */ + +#include "nvtypes.h" + +#define AMPERE_COMPUTE_B 0xC7C0 + +#define NVC7C0_SET_OBJECT 0x0000 +#define NVC7C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC7C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC7C0_NO_OPERATION 0x0100 +#define NVC7C0_NO_OPERATION_V 31:0 + +#define NVC7C0_SET_NOTIFY_A 0x0104 +#define NVC7C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_NOTIFY_B 0x0108 +#define NVC7C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_NOTIFY 0x010c +#define NVC7C0_NOTIFY_TYPE 31:0 +#define NVC7C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC7C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC7C0_WAIT_FOR_IDLE 0x0110 +#define NVC7C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC7C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC7C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC7C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC7C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC7C0_SEND_GO_IDLE 0x013c +#define NVC7C0_SEND_GO_IDLE_V 31:0 + +#define NVC7C0_PM_TRIGGER 0x0140 +#define NVC7C0_PM_TRIGGER_V 31:0 + +#define NVC7C0_PM_TRIGGER_WFI 0x0144 +#define NVC7C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC7C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC7C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC7C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC7C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC7C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC7C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC7C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC7C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC7C0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC7C0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 2:2 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 4:3 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 5:5 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 6:6 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 9:7 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 11:10 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 12:12 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 14:13 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC7C0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC7C0_LINE_LENGTH_IN 0x0180 +#define NVC7C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC7C0_LINE_COUNT 0x0184 +#define NVC7C0_LINE_COUNT_VALUE 31:0 + +#define NVC7C0_OFFSET_OUT_UPPER 0x0188 +#define NVC7C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC7C0_OFFSET_OUT 0x018c +#define NVC7C0_OFFSET_OUT_VALUE 31:0 + +#define NVC7C0_PITCH_OUT 0x0190 +#define NVC7C0_PITCH_OUT_VALUE 31:0 + +#define NVC7C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC7C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC7C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC7C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC7C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC7C0_SET_DST_WIDTH 0x0198 +#define NVC7C0_SET_DST_WIDTH_V 31:0 + +#define NVC7C0_SET_DST_HEIGHT 0x019c +#define NVC7C0_SET_DST_HEIGHT_V 31:0 + +#define NVC7C0_SET_DST_DEPTH 0x01a0 +#define NVC7C0_SET_DST_DEPTH_V 31:0 + +#define NVC7C0_SET_DST_LAYER 0x01a4 +#define NVC7C0_SET_DST_LAYER_V 31:0 + +#define NVC7C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC7C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC7C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC7C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC7C0_LAUNCH_DMA 0x01b0 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC7C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC7C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC7C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC7C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC7C0_LOAD_INLINE_DATA 0x01b4 +#define NVC7C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC7C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC7C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC7C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC7C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC7C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC7C0_SET_MME_SWITCH_STATE 0x01ec +#define NVC7C0_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC7C0_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC7C0_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC7C0_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC7C0_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC7C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC7C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC7C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC7C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC7C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC7C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC7C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC7C0_PERFMON_TRANSFER 0x0210 +#define NVC7C0_PERFMON_TRANSFER_V 31:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC7C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC7C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC7C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC7C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC7C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC7C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC7C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC7C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC7C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC7C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC7C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC7C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC7C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC7C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC7C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC7C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC7C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC7C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC7C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC7C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC7C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC7C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC7C0_SET_SCG_CONTROL 0x0270 +#define NVC7C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC7C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC7C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC7C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC7C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC7C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC7C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_SET_QMD_VERSION 0x0288 +#define NVC7C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC7C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_CHECK_QMD_VERSION 0x0290 +#define NVC7C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC7C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC7C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC7C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE 9:9 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_DEPENDENT_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE 10:10 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_DEPENDENT_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC7C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC7C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC7C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC7C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC7C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC7C0_SEND_PCAS_A 0x02b4 +#define NVC7C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC7C0_SEND_PCAS_B 0x02b8 +#define NVC7C0_SEND_PCAS_B_FROM 23:0 +#define NVC7C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC7C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC7C0_SEND_SIGNALING_PCAS2_B 0x02c0 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION 3:0 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP 0x00000000 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE 0x00000001 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE 0x00000002 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT 0x00000006 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE 0x00000007 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH 0x00000008 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE 0x00000009 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE 0x0000000A +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING 0x0000000B +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_DEPENDENCE 0x0000000C +#define NVC7C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_CWD_REF_COUNTER 0x0000000D +#define NVC7C0_SEND_SIGNALING_PCAS2_B_SELECT 13:8 +#define NVC7C0_SEND_SIGNALING_PCAS2_B_OFFSET_MINUS_ONE 23:14 + +#define NVC7C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC7C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC7C0_SET_SPA_VERSION 0x0310 +#define NVC7C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC7C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC7C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC7C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC7C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC7C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC7C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC7C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC7C0_SET_FALCON00 0x0500 +#define NVC7C0_SET_FALCON00_V 31:0 + +#define NVC7C0_SET_FALCON01 0x0504 +#define NVC7C0_SET_FALCON01_V 31:0 + +#define NVC7C0_SET_FALCON02 0x0508 +#define NVC7C0_SET_FALCON02_V 31:0 + +#define NVC7C0_SET_FALCON03 0x050c +#define NVC7C0_SET_FALCON03_V 31:0 + +#define NVC7C0_SET_FALCON04 0x0510 +#define NVC7C0_SET_FALCON04_V 31:0 + +#define NVC7C0_SET_FALCON05 0x0514 +#define NVC7C0_SET_FALCON05_V 31:0 + +#define NVC7C0_SET_FALCON06 0x0518 +#define NVC7C0_SET_FALCON06_V 31:0 + +#define NVC7C0_SET_FALCON07 0x051c +#define NVC7C0_SET_FALCON07_V 31:0 + +#define NVC7C0_SET_FALCON08 0x0520 +#define NVC7C0_SET_FALCON08_V 31:0 + +#define NVC7C0_SET_FALCON09 0x0524 +#define NVC7C0_SET_FALCON09_V 31:0 + +#define NVC7C0_SET_FALCON10 0x0528 +#define NVC7C0_SET_FALCON10_V 31:0 + +#define NVC7C0_SET_FALCON11 0x052c +#define NVC7C0_SET_FALCON11_V 31:0 + +#define NVC7C0_SET_FALCON12 0x0530 +#define NVC7C0_SET_FALCON12_V 31:0 + +#define NVC7C0_SET_FALCON13 0x0534 +#define NVC7C0_SET_FALCON13_V 31:0 + +#define NVC7C0_SET_FALCON14 0x0538 +#define NVC7C0_SET_FALCON14_V 31:0 + +#define NVC7C0_SET_FALCON15 0x053c +#define NVC7C0_SET_FALCON15_V 31:0 + +#define NVC7C0_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC7C0_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC7C0_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC7C0_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC7C0_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC7C0_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC7C0_MME_DMA_READ 0x055c +#define NVC7C0_MME_DMA_READ_LENGTH 31:0 + +#define NVC7C0_MME_DMA_READ_FIFOED 0x0560 +#define NVC7C0_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC7C0_MME_DMA_WRITE 0x0564 +#define NVC7C0_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC7C0_MME_DMA_REDUCTION 0x0568 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC7C0_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC7C0_MME_DMA_SYSMEMBAR 0x056c +#define NVC7C0_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC7C0_MME_DMA_SYNC 0x0570 +#define NVC7C0_MME_DMA_SYNC_VALUE 31:0 + +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC7C0_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC7C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC7C0_THROTTLE_SM 0x07fc +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC7C0_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC7C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC7C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC7C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC7C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC7C0_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC7C0_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC7C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC7C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC7C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC7C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC7C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC7C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC7C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC7C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC7C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC7C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC7C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC7C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC7C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC7C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC7C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC7C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC7C0_PIPE_NOP 0x1a2c +#define NVC7C0_PIPE_NOP_V 31:0 + +#define NVC7C0_SET_SPARE00 0x1a30 +#define NVC7C0_SET_SPARE00_V 31:0 + +#define NVC7C0_SET_SPARE01 0x1a34 +#define NVC7C0_SET_SPARE01_V 31:0 + +#define NVC7C0_SET_SPARE02 0x1a38 +#define NVC7C0_SET_SPARE02_V 31:0 + +#define NVC7C0_SET_SPARE03 0x1a3c +#define NVC7C0_SET_SPARE03_V 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC7C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC7C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC7C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC7C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC7C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC7C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC7C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC7C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC7C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC7C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC7C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC7C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC7C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC7C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC7C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC7C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC7C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC7C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC7C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC7C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC7C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC7C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC7C0_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC7C0_CALL_MME_MACRO_V 31:0 + +#define NVC7C0_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC7C0_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_compute_b_h_ */ diff --git a/src/nouveau/nvidia-headers/classes/clc7c0qmd.h b/src/nouveau/nvidia-headers/classes/clc7c0qmd.h new file mode 100644 index 0000000..3be28b7 --- /dev/null +++ b/src/nouveau/nvidia-headers/classes/clc7c0qmd.h @@ -0,0 +1,771 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC7C0QMD_H__ +#define __CLC7C0QMD_H__ + +/* +** Queue Meta Data, Version 02_03 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC7C0_QMDV02_03_OUTER_PUT MW(30:0) +#define NVC7C0_QMDV02_03_OUTER_OVERFLOW MW(31:31) +#define NVC7C0_QMDV02_03_OUTER_GET MW(62:32) +#define NVC7C0_QMDV02_03_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC7C0_QMDV02_03_INNER_GET MW(94:64) +#define NVC7C0_QMDV02_03_INNER_OVERFLOW MW(95:95) +#define NVC7C0_QMDV02_03_INNER_PUT MW(126:96) +#define NVC7C0_QMDV02_03_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC7C0_QMDV02_03_QMD_GROUP_ID MW(133:128) +#define NVC7C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC7C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC7C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_IS_QUEUE MW(136:136) +#define NVC7C0_QMDV02_03_IS_QUEUE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_IS_QUEUE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC7C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC7C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC7C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC7C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC7C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC7C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC7C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_QMD_RESERVED_B MW(159:144) +#define NVC7C0_QMDV02_03_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC7C0_QMDV02_03_QMD_RESERVED_C MW(185:185) +#define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC7C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC7C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC7C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC7C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC7C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC7C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) +#define NVC7C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC7C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC7C0_QMDV02_03_QMD_RESERVED_D MW(335:328) +#define NVC7C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC7C0_QMDV02_03_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC7C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC7C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_CWD_MEMBAR_TYPE MW(369:368) +#define NVC7C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC7C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC7C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC7C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC7C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC7C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC7C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC7C0_QMDV02_03_SAMPLER_INDEX MW(382:382) +#define NVC7C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC7C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC7C0_QMDV02_03_CTA_RASTER_WIDTH MW(415:384) +#define NVC7C0_QMDV02_03_CTA_RASTER_HEIGHT MW(431:416) +#define NVC7C0_QMDV02_03_QMD_RESERVED13A MW(447:432) +#define NVC7C0_QMDV02_03_CTA_RASTER_DEPTH MW(463:448) +#define NVC7C0_QMDV02_03_QMD_RESERVED14A MW(479:464) +#define NVC7C0_QMDV02_03_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC7C0_QMDV02_03_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC7C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) +#define NVC7C0_QMDV02_03_SHARED_MEMORY_SIZE MW(561:544) +#define NVC7C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC7C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC7C0_QMDV02_03_QMD_VERSION MW(579:576) +#define NVC7C0_QMDV02_03_QMD_MAJOR_VERSION MW(583:580) +#define NVC7C0_QMDV02_03_QMD_RESERVED_H MW(591:584) +#define NVC7C0_QMDV02_03_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC7C0_QMDV02_03_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC7C0_QMDV02_03_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_REGISTER_COUNT_V MW(656:648) +#define NVC7C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC7C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC7C0_QMDV02_03_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC7C0_QMDV02_03_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC7C0_QMDV02_03_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC7C0_QMDV02_03_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC7C0_QMDV02_03_QMD_RESERVED_J MW(783:776) +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_QMDV02_03_QMD_RESERVED_K MW(791:791) +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC7C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_QMDV02_03_RELEASE0_PAYLOAD MW(831:800) +#define NVC7C0_QMDV02_03_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC7C0_QMDV02_03_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC7C0_QMDV02_03_QMD_RESERVED_L MW(879:872) +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_QMDV02_03_QMD_RESERVED_M MW(887:887) +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC7C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_QMDV02_03_RELEASE1_PAYLOAD MW(927:896) +#define NVC7C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC7C0_QMDV02_03_QMD_RESERVED_N MW(954:952) +#define NVC7C0_QMDV02_03_BARRIER_COUNT MW(959:955) +#define NVC7C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC7C0_QMDV02_03_REGISTER_COUNT MW(991:984) +#define NVC7C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) +#define NVC7C0_QMDV02_03_PROGRAM_PREFETCH_SIZE MW(1009:1001) +#define NVC7C0_QMDV02_03_QMD_RESERVED_A MW(1015:1010) +#define NVC7C0_QMDV02_03_SASS_VERSION MW(1023:1016) +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC7C0_QMDV02_03_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC7C0_QMDV02_03_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC7C0_QMDV02_03_QMD_RESERVED_S MW(1599:1585) +#define NVC7C0_QMDV02_03_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC7C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC7C0_QMDV02_03_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC7C0_QMDV02_03_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC7C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC7C0_QMDV02_03_QMD_RESERVED_Q MW(1694:1694) +#define NVC7C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC7C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC7C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC7C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC7C0_QMDV02_03_QMD_SPARE_G MW(1759:1728) +#define NVC7C0_QMDV02_03_QMD_SPARE_H MW(1791:1760) +#define NVC7C0_QMDV02_03_QMD_SPARE_I MW(1823:1792) +#define NVC7C0_QMDV02_03_QMD_SPARE_J MW(1855:1824) +#define NVC7C0_QMDV02_03_QMD_SPARE_K MW(1887:1856) +#define NVC7C0_QMDV02_03_QMD_SPARE_L MW(1919:1888) +#define NVC7C0_QMDV02_03_QMD_SPARE_M MW(1951:1920) +#define NVC7C0_QMDV02_03_QMD_SPARE_N MW(1983:1952) +#define NVC7C0_QMDV02_03_DEBUG_ID_UPPER MW(2015:1984) +#define NVC7C0_QMDV02_03_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_04 + */ + +#define NVC7C0_QMDV02_04_OUTER_PUT MW(30:0) +#define NVC7C0_QMDV02_04_OUTER_OVERFLOW MW(31:31) +#define NVC7C0_QMDV02_04_OUTER_GET MW(62:32) +#define NVC7C0_QMDV02_04_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC7C0_QMDV02_04_INNER_GET MW(94:64) +#define NVC7C0_QMDV02_04_INNER_OVERFLOW MW(95:95) +#define NVC7C0_QMDV02_04_INNER_PUT MW(126:96) +#define NVC7C0_QMDV02_04_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC7C0_QMDV02_04_QMD_GROUP_ID MW(133:128) +#define NVC7C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC7C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC7C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_IS_QUEUE MW(136:136) +#define NVC7C0_QMDV02_04_IS_QUEUE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_IS_QUEUE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC7C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC7C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ENABLE MW(141:141) +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ACTION MW(144:142) +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH MW(145:145) +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ENABLE MW(146:146) +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ACTION MW(149:147) +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH MW(150:150) +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_DEPENDENCE_COUNTER MW(157:151) +#define NVC7C0_QMDV02_04_SELF_COPY_ON_COMPLETION MW(158:158) +#define NVC7C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_QMD_RESERVED_B MW(159:159) +#define NVC7C0_QMDV02_04_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC7C0_QMDV02_04_DEMOTE_L2_EVICT_LAST MW(185:185) +#define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC7C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC7C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC7C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC7C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC7C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) +#define NVC7C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC7C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC7C0_QMDV02_04_QMD_RESERVED_D MW(335:328) +#define NVC7C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC7C0_QMDV02_04_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC7C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC7C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_CWD_MEMBAR_TYPE MW(369:368) +#define NVC7C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC7C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC7C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC7C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC7C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC7C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC7C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC7C0_QMDV02_04_SAMPLER_INDEX MW(382:382) +#define NVC7C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC7C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC7C0_QMDV02_04_DISABLE_AUTO_INVALIDATE MW(383:383) +#define NVC7C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_CTA_RASTER_WIDTH MW(415:384) +#define NVC7C0_QMDV02_04_CTA_RASTER_HEIGHT MW(431:416) +#define NVC7C0_QMDV02_04_QMD_RESERVED13A MW(447:432) +#define NVC7C0_QMDV02_04_CTA_RASTER_DEPTH MW(463:448) +#define NVC7C0_QMDV02_04_QMD_RESERVED14A MW(479:464) +#define NVC7C0_QMDV02_04_DEPENDENT_QMD0_POINTER MW(511:480) +#define NVC7C0_QMDV02_04_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC7C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) +#define NVC7C0_QMDV02_04_SHARED_MEMORY_SIZE MW(561:544) +#define NVC7C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC7C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC7C0_QMDV02_04_QMD_VERSION MW(579:576) +#define NVC7C0_QMDV02_04_QMD_MAJOR_VERSION MW(583:580) +#define NVC7C0_QMDV02_04_QMD_RESERVED_H MW(591:584) +#define NVC7C0_QMDV02_04_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC7C0_QMDV02_04_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC7C0_QMDV02_04_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_REGISTER_COUNT_V MW(656:648) +#define NVC7C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC7C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC7C0_QMDV02_04_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC7C0_QMDV02_04_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC7C0_QMDV02_04_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC7C0_QMDV02_04_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC7C0_QMDV02_04_QMD_RESERVED_J MW(783:776) +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_QMDV02_04_QMD_RESERVED_K MW(791:791) +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC7C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_QMDV02_04_RELEASE0_PAYLOAD MW(831:800) +#define NVC7C0_QMDV02_04_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC7C0_QMDV02_04_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC7C0_QMDV02_04_QMD_RESERVED_L MW(879:872) +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_QMDV02_04_QMD_RESERVED_M MW(887:887) +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC7C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC7C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC7C0_QMDV02_04_RELEASE1_PAYLOAD MW(927:896) +#define NVC7C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC7C0_QMDV02_04_QMD_RESERVED_N MW(954:952) +#define NVC7C0_QMDV02_04_BARRIER_COUNT MW(959:955) +#define NVC7C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC7C0_QMDV02_04_QMD_RESERVED_G MW(991:984) +#define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) +#define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_SIZE MW(1009:1001) +#define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_TYPE MW(1011:1010) +#define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 +#define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 +#define NVC7C0_QMDV02_04_QMD_RESERVED_A MW(1015:1012) +#define NVC7C0_QMDV02_04_SASS_VERSION MW(1023:1016) +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC7C0_QMDV02_04_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC7C0_QMDV02_04_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC7C0_QMDV02_04_QMD_RESERVED_S MW(1599:1585) +#define NVC7C0_QMDV02_04_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC7C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC7C0_QMDV02_04_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC7C0_QMDV02_04_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC7C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC7C0_QMDV02_04_QMD_RESERVED_Q MW(1694:1694) +#define NVC7C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC7C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC7C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC7C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC7C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER MW(1734:1728) +#define NVC7C0_QMDV02_04_QMD_RESERVED_I MW(1759:1735) +#define NVC7C0_QMDV02_04_QMD_SPARE_H MW(1791:1760) +#define NVC7C0_QMDV02_04_QMD_SPARE_I MW(1823:1792) +#define NVC7C0_QMDV02_04_QMD_SPARE_J MW(1855:1824) +#define NVC7C0_QMDV02_04_QMD_SPARE_K MW(1887:1856) +#define NVC7C0_QMDV02_04_QMD_SPARE_L MW(1919:1888) +#define NVC7C0_QMDV02_04_QMD_SPARE_M MW(1951:1920) +#define NVC7C0_QMDV02_04_QMD_SPARE_N MW(1983:1952) +#define NVC7C0_QMDV02_04_DEBUG_ID_UPPER MW(2015:1984) +#define NVC7C0_QMDV02_04_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 03_00 + */ + +#define NVC7C0_QMDV03_00_OUTER_PUT MW(30:0) +#define NVC7C0_QMDV03_00_OUTER_OVERFLOW MW(31:31) +#define NVC7C0_QMDV03_00_OUTER_GET MW(62:32) +#define NVC7C0_QMDV03_00_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC7C0_QMDV03_00_INNER_GET MW(94:64) +#define NVC7C0_QMDV03_00_INNER_OVERFLOW MW(95:95) +#define NVC7C0_QMDV03_00_INNER_PUT MW(126:96) +#define NVC7C0_QMDV03_00_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC7C0_QMDV03_00_QMD_GROUP_ID MW(133:128) +#define NVC7C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC7C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC7C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_IS_QUEUE MW(136:136) +#define NVC7C0_QMDV03_00_IS_QUEUE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_IS_QUEUE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC7C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_QMD_RESERVED04A MW(139:138) +#define NVC7C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC7C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_QMD_RESERVED04B MW(141:141) +#define NVC7C0_QMDV03_00_DEPENDENCE_COUNTER MW(157:142) +#define NVC7C0_QMDV03_00_SELF_COPY_ON_COMPLETION MW(158:158) +#define NVC7C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_QMD_RESERVED04C MW(159:159) +#define NVC7C0_QMDV03_00_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC7C0_QMDV03_00_DEMOTE_L2_EVICT_LAST MW(185:185) +#define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC7C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC7C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC7C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC7C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC7C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) +#define NVC7C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC7C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC7C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC7C0_QMDV03_00_QMD_RESERVED11A MW(366:366) +#define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_CWD_MEMBAR_TYPE MW(369:368) +#define NVC7C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC7C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC7C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC7C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC7C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_QMD_RESERVED11B MW(377:372) +#define NVC7C0_QMDV03_00_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC7C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC7C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC7C0_QMDV03_00_QMD_RESERVED11C MW(381:379) +#define NVC7C0_QMDV03_00_SAMPLER_INDEX MW(382:382) +#define NVC7C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC7C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC7C0_QMDV03_00_DISABLE_AUTO_INVALIDATE MW(383:383) +#define NVC7C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_CTA_RASTER_WIDTH MW(415:384) +#define NVC7C0_QMDV03_00_CTA_RASTER_HEIGHT MW(431:416) +#define NVC7C0_QMDV03_00_CTA_RASTER_DEPTH MW(463:448) +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_POINTER MW(511:480) +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ENABLE MW(512:512) +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ACTION MW(515:513) +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH MW(516:516) +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ENABLE MW(517:517) +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ACTION MW(520:518) +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH MW(521:521) +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC7C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) +#define NVC7C0_QMDV03_00_OCCUPANCY_THRESHOLD_SHARED_MEM MW(542:535) +#define NVC7C0_QMDV03_00_CTA_LAUNCH_QUEUE MW(543:543) +#define NVC7C0_QMDV03_00_SHARED_MEMORY_SIZE MW(561:544) +#define NVC7C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(567:562) +#define NVC7C0_QMDV03_00_QMD_RESERVED17A MW(568:568) +#define NVC7C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(574:569) +#define NVC7C0_QMDV03_00_QMD_RESERVED17B MW(575:575) +#define NVC7C0_QMDV03_00_QMD_VERSION MW(579:576) +#define NVC7C0_QMDV03_00_QMD_MAJOR_VERSION MW(583:580) +#define NVC7C0_QMDV03_00_OCCUPANCY_MAX_SHARED_MEM MW(591:584) +#define NVC7C0_QMDV03_00_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC7C0_QMDV03_00_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC7C0_QMDV03_00_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_REGISTER_COUNT_V MW(656:648) +#define NVC7C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(662:657) +#define NVC7C0_QMDV03_00_SHARED_ALLOCATION_ENABLE MW(663:663) +#define NVC7C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC7C0_QMDV03_00_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC7C0_QMDV03_00_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC7C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(759:736) +#define NVC7C0_QMDV03_00_BARRIER_COUNT MW(767:763) +#define NVC7C0_QMDV03_00_RELEASE0_ADDRESS_LOWER MW(799:768) +#define NVC7C0_QMDV03_00_RELEASE0_ADDRESS_UPPER MW(807:800) +#define NVC7C0_QMDV03_00_SEMAPHORE_RESERVED25A MW(818:808) +#define NVC7C0_QMDV03_00_RELEASE0_MEMBAR_TYPE MW(819:819) +#define NVC7C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP MW(822:820) +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_QMDV03_00_RELEASE0_ENABLE MW(823:823) +#define NVC7C0_QMDV03_00_RELEASE0_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE0_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT MW(825:824) +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE MW(826:826) +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE0_TRAP_TYPE MW(828:827) +#define NVC7C0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC7C0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 +#define NVC7C0_QMDV03_00_RELEASE0_PAYLOAD64B MW(829:829) +#define NVC7C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE MW(831:830) +#define NVC7C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC7C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER MW(863:832) +#define NVC7C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER MW(895:864) +#define NVC7C0_QMDV03_00_RELEASE1_ADDRESS_LOWER MW(927:896) +#define NVC7C0_QMDV03_00_RELEASE1_ADDRESS_UPPER MW(935:928) +#define NVC7C0_QMDV03_00_SEMAPHORE_RESERVED29A MW(946:936) +#define NVC7C0_QMDV03_00_RELEASE1_MEMBAR_TYPE MW(947:947) +#define NVC7C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP MW(950:948) +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_QMDV03_00_RELEASE1_ENABLE MW(951:951) +#define NVC7C0_QMDV03_00_RELEASE1_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE1_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT MW(953:952) +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE MW(954:954) +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE1_TRAP_TYPE MW(956:955) +#define NVC7C0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC7C0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 +#define NVC7C0_QMDV03_00_RELEASE1_PAYLOAD64B MW(957:957) +#define NVC7C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE MW(959:958) +#define NVC7C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC7C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER MW(991:960) +#define NVC7C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER MW(1023:992) +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC7C0_QMDV03_00_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC7C0_QMDV03_00_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC7C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1623:1600) +#define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1640:1632) +#define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_SIZE MW(1649:1641) +#define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_TYPE MW(1651:1650) +#define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 +#define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 +#define NVC7C0_QMDV03_00_SASS_VERSION MW(1663:1656) +#define NVC7C0_QMDV03_00_RELEASE2_ADDRESS_LOWER MW(1695:1664) +#define NVC7C0_QMDV03_00_RELEASE2_ADDRESS_UPPER MW(1703:1696) +#define NVC7C0_QMDV03_00_SEMAPHORE_RESERVED53A MW(1714:1704) +#define NVC7C0_QMDV03_00_RELEASE2_MEMBAR_TYPE MW(1715:1715) +#define NVC7C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP MW(1718:1716) +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC 0x00000003 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND 0x00000005 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR 0x00000006 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC7C0_QMDV03_00_RELEASE2_ENABLE MW(1719:1719) +#define NVC7C0_QMDV03_00_RELEASE2_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE2_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT MW(1721:1720) +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE MW(1722:1722) +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE2_TRAP_TYPE MW(1724:1723) +#define NVC7C0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC7C0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 +#define NVC7C0_QMDV03_00_RELEASE2_PAYLOAD64B MW(1725:1725) +#define NVC7C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE MW(1727:1726) +#define NVC7C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC7C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC7C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC7C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER MW(1759:1728) +#define NVC7C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER MW(1791:1760) +#define NVC7C0_QMDV03_00_OCCUPANCY_THRESHOLD_WARP MW(1799:1792) +#define NVC7C0_QMDV03_00_OCCUPANCY_MAX_WARP MW(1807:1800) +#define NVC7C0_QMDV03_00_OCCUPANCY_THRESHOLD_REGISTER MW(1815:1808) +#define NVC7C0_QMDV03_00_OCCUPANCY_MAX_REGISTER MW(1823:1816) +#define NVC7C0_QMDV03_00_HW_ONLY_INNER_GET MW(1854:1824) +#define NVC7C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1855:1855) +#define NVC7C0_QMDV03_00_HW_ONLY_INNER_PUT MW(1886:1856) +#define NVC7C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1917:1888) +#define NVC7C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1919:1919) +#define NVC7C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC7C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC7C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1951:1920) +#define NVC7C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER MW(1967:1952) +#define NVC7C0_QMDV03_00_DEBUG_ID_UPPER MW(2015:1984) +#define NVC7C0_QMDV03_00_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC7C0QMD_H__