From: Ben Skeggs <bskeggs@redhat.com>
Date: Mon, 2 Dec 2013 22:25:04 +0000 (+1000)
Subject: drm/nouveau/clk: allow fb to signal it needs to do a multi-stage reclock
X-Git-Tag: v3.14-rc1~47^2^2~30
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1789cab4efbe5d9a3058a52aaecc9246f71aa0e2;p=platform%2Fkernel%2Flinux-exynos.git

drm/nouveau/clk: allow fb to signal it needs to do a multi-stage reclock

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---

diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
index e2938a21b06f..dd62baead39c 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c
@@ -182,9 +182,12 @@ nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
 	clk->pstate = pstatei;
 
 	if (pfb->ram->calc) {
-		ret = pfb->ram->calc(pfb, pstate->base.domain[nv_clk_src_mem]);
-		if (ret == 0)
-			ret = pfb->ram->prog(pfb);
+		int khz = pstate->base.domain[nv_clk_src_mem];
+		do {
+			ret = pfb->ram->calc(pfb, khz);
+			if (ret == 0)
+				ret = pfb->ram->prog(pfb);
+		} while (ret > 0);
 		pfb->ram->tidy(pfb);
 	}