From: David Sherwood <david.sherwood@arm.com>
Date: Thu, 3 Nov 2022 11:51:29 +0000 (+0000)
Subject: [AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions
X-Git-Tag: upstream/17.0.6~28246
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=17813095de1769abb3ab6196115556fce6d81496;p=platform%2Fupstream%2Fllvm.git

[AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions

This patch adds the assembly/disassembly for the following instructions:

faddqv   : Floating-point add recursive reduction of quadword vector segments
fmaxqv   : Floating-point maximum reduction of quadword vector segments
fmaxnmqv : Floating-point maximum number recursive reduction of quadword vector segments
fminqv   : Floating-point minimum recursive reduction of quadword vector segments
fminnmqv : Floating-point minimum number recursive reduction of quadword vector segments

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Differential Revision: https://reviews.llvm.org/D137419
---

diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 32bdf17..c8d131a 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3748,3 +3748,15 @@ defm BFMUL_ZZZI : sve2p1_fp_bfmul_by_indexed_elem<"bfmul">;
 
 def BFCLAMP_ZZZ : sve2p1_fclamp<"bfclamp", 0b00, ZPR16>;
 } // End HasSVE2p1_or_HasSME2p1, HasB16B16
+
+
+//===----------------------------------------------------------------------===//
+// SME2.1 or SVE2.1 instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasSVE2p1_or_HasSME2p1] in {
+defm FADDQV   : sve2p1_fp_reduction_q<0b000, "faddqv">;
+defm FMAXNMQV : sve2p1_fp_reduction_q<0b100, "fmaxnmqv">;
+defm FMINNMQV : sve2p1_fp_reduction_q<0b101, "fminnmqv">;
+defm FMAXQV   : sve2p1_fp_reduction_q<0b110, "fmaxqv">;
+defm FMINQV   : sve2p1_fp_reduction_q<0b111, "fminqv">;
+}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
index dec56e7..afdb1d4 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -22,7 +22,8 @@ def A64FXModel : SchedMachineModel {
 
   list<Predicate> UnsupportedFeatures =
     [HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
-     HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2];
+     HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2, HasSME2p1, HasSVE2p1,
+     HasSVE2p1_or_HasSME2p1];
 
   let FullInstRWOverlapCheck = 0;
 }
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index f9d6abdd..c036db4 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -9283,3 +9283,29 @@ multiclass sve_mem_128b_cld_ss<bits<2> dtype, string mnemonic, RegisterOperand g
   def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Rn, $Rm]",
                  (!cast<Instruction>(NAME) ZPR128:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprsh_ty:$Rm), 0>;
 }
+
+
+// SVE floating-point recursive reduction (quadwords)
+class sve2p1_fp_reduction_q<bits<2> sz, bits<3> opc, string mnemonic,
+                            RegisterOperand zpr_ty, string vec_sfx>
+    : I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
+        mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn",
+        "", []>, Sched<[]> {
+  bits<5> Vd;
+  bits<5> Zn;
+  bits<3> Pg;
+  let Inst{31-24} = 0b01100100;
+  let Inst{23-22} = sz;
+  let Inst{21-19} = 0b010;
+  let Inst{18-16} = opc;
+  let Inst{15-13} = 0b101;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Vd;
+}
+
+multiclass sve2p1_fp_reduction_q<bits<3> opc, string mnemonic> {
+  def _H : sve2p1_fp_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">;
+  def _S : sve2p1_fp_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">;
+  def _D : sve2p1_fp_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">;
+}
diff --git a/llvm/test/MC/AArch64/SVE2p1/faddqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/faddqv-diagnostics.s
new file mode 100644
index 0000000..85a2ab2
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/faddqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+faddqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: faddqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+faddqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: faddqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+faddqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: faddqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+faddqv v0.2d, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: faddqv v0.2d, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/faddqv.s b/llvm/test/MC/AArch64/SVE2p1/faddqv.s
new file mode 100644
index 0000000..cc1dbb4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/faddqv.s
@@ -0,0 +1,90 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+faddqv  v0.2d, p0, z0.d  // 01100100-11010000-10100000-00000000
+// CHECK-INST: faddqv  v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd0,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d0a000 <unknown>
+
+faddqv  v21.2d, p5, z10.d  // 01100100-11010000-10110101-01010101
+// CHECK-INST: faddqv  v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0xb5,0xd0,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d0b555 <unknown>
+
+faddqv  v23.2d, p3, z13.d  // 01100100-11010000-10101101-10110111
+// CHECK-INST: faddqv  v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0xad,0xd0,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d0adb7 <unknown>
+
+faddqv  v31.2d, p7, z31.d  // 01100100-11010000-10111111-11111111
+// CHECK-INST: faddqv  v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xd0,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d0bfff <unknown>
+
+
+faddqv  v0.8h, p0, z0.h  // 01100100-01010000-10100000-00000000
+// CHECK-INST: faddqv  v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x50,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6450a000 <unknown>
+
+faddqv  v21.8h, p5, z10.h  // 01100100-01010000-10110101-01010101
+// CHECK-INST: faddqv  v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0xb5,0x50,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6450b555 <unknown>
+
+faddqv  v23.8h, p3, z13.h  // 01100100-01010000-10101101-10110111
+// CHECK-INST: faddqv  v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0xad,0x50,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6450adb7 <unknown>
+
+faddqv  v31.8h, p7, z31.h  // 01100100-01010000-10111111-11111111
+// CHECK-INST: faddqv  v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x50,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6450bfff <unknown>
+
+
+faddqv  v0.4s, p0, z0.s  // 01100100-10010000-10100000-00000000
+// CHECK-INST: faddqv  v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x90,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6490a000 <unknown>
+
+faddqv  v21.4s, p5, z10.s  // 01100100-10010000-10110101-01010101
+// CHECK-INST: faddqv  v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0xb5,0x90,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6490b555 <unknown>
+
+faddqv  v23.4s, p3, z13.s  // 01100100-10010000-10101101-10110111
+// CHECK-INST: faddqv  v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0xad,0x90,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6490adb7 <unknown>
+
+faddqv  v31.4s, p7, z31.s  // 01100100-10010000-10111111-11111111
+// CHECK-INST: faddqv  v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x90,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6490bfff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/fmaxnmqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/fmaxnmqv-diagnostics.s
new file mode 100644
index 0000000..0dd80cb
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/fmaxnmqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+fmaxnmqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fmaxnmqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+fmaxnmqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxnmqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxnmqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxnmqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+fmaxnmqv v0.2d, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmaxnmqv v0.2d, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/fmaxnmqv.s b/llvm/test/MC/AArch64/SVE2p1/fmaxnmqv.s
new file mode 100644
index 0000000..de1c312
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/fmaxnmqv.s
@@ -0,0 +1,90 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fmaxnmqv v0.2d, p0, z0.d  // 01100100-11010100-10100000-00000000
+// CHECK-INST: fmaxnmqv v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd4,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d4a000 <unknown>
+
+fmaxnmqv v21.2d, p5, z10.d  // 01100100-11010100-10110101-01010101
+// CHECK-INST: fmaxnmqv v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0xb5,0xd4,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d4b555 <unknown>
+
+fmaxnmqv v23.2d, p3, z13.d  // 01100100-11010100-10101101-10110111
+// CHECK-INST: fmaxnmqv v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0xad,0xd4,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d4adb7 <unknown>
+
+fmaxnmqv v31.2d, p7, z31.d  // 01100100-11010100-10111111-11111111
+// CHECK-INST: fmaxnmqv v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xd4,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d4bfff <unknown>
+
+
+fmaxnmqv v0.8h, p0, z0.h  // 01100100-01010100-10100000-00000000
+// CHECK-INST: fmaxnmqv v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x54,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6454a000 <unknown>
+
+fmaxnmqv v21.8h, p5, z10.h  // 01100100-01010100-10110101-01010101
+// CHECK-INST: fmaxnmqv v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0xb5,0x54,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6454b555 <unknown>
+
+fmaxnmqv v23.8h, p3, z13.h  // 01100100-01010100-10101101-10110111
+// CHECK-INST: fmaxnmqv v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0xad,0x54,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6454adb7 <unknown>
+
+fmaxnmqv v31.8h, p7, z31.h  // 01100100-01010100-10111111-11111111
+// CHECK-INST: fmaxnmqv v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x54,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6454bfff <unknown>
+
+
+fmaxnmqv v0.4s, p0, z0.s  // 01100100-10010100-10100000-00000000
+// CHECK-INST: fmaxnmqv v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x94,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6494a000 <unknown>
+
+fmaxnmqv v21.4s, p5, z10.s  // 01100100-10010100-10110101-01010101
+// CHECK-INST: fmaxnmqv v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0xb5,0x94,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6494b555 <unknown>
+
+fmaxnmqv v23.4s, p3, z13.s  // 01100100-10010100-10101101-10110111
+// CHECK-INST: fmaxnmqv v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0xad,0x94,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6494adb7 <unknown>
+
+fmaxnmqv v31.4s, p7, z31.s  // 01100100-10010100-10111111-11111111
+// CHECK-INST: fmaxnmqv v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x94,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6494bfff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/fmaxqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/fmaxqv-diagnostics.s
new file mode 100644
index 0000000..3a5366b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/fmaxqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+fmaxqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fmaxqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+fmaxqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+fmaxqv v0.2d, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmaxqv v0.2d, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/fmaxqv.s b/llvm/test/MC/AArch64/SVE2p1/fmaxqv.s
new file mode 100644
index 0000000..1d00885
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/fmaxqv.s
@@ -0,0 +1,90 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fmaxqv  v0.2d, p0, z0.d  // 01100100-11010110-10100000-00000000
+// CHECK-INST: fmaxqv  v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd6,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d6a000 <unknown>
+
+fmaxqv  v21.2d, p5, z10.d  // 01100100-11010110-10110101-01010101
+// CHECK-INST: fmaxqv  v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0xb5,0xd6,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d6b555 <unknown>
+
+fmaxqv  v23.2d, p3, z13.d  // 01100100-11010110-10101101-10110111
+// CHECK-INST: fmaxqv  v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0xad,0xd6,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d6adb7 <unknown>
+
+fmaxqv  v31.2d, p7, z31.d  // 01100100-11010110-10111111-11111111
+// CHECK-INST: fmaxqv  v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xd6,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d6bfff <unknown>
+
+
+fmaxqv  v0.8h, p0, z0.h  // 01100100-01010110-10100000-00000000
+// CHECK-INST: fmaxqv  v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x56,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6456a000 <unknown>
+
+fmaxqv  v21.8h, p5, z10.h  // 01100100-01010110-10110101-01010101
+// CHECK-INST: fmaxqv  v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0xb5,0x56,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6456b555 <unknown>
+
+fmaxqv  v23.8h, p3, z13.h  // 01100100-01010110-10101101-10110111
+// CHECK-INST: fmaxqv  v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0xad,0x56,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6456adb7 <unknown>
+
+fmaxqv  v31.8h, p7, z31.h  // 01100100-01010110-10111111-11111111
+// CHECK-INST: fmaxqv  v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x56,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6456bfff <unknown>
+
+
+fmaxqv  v0.4s, p0, z0.s  // 01100100-10010110-10100000-00000000
+// CHECK-INST: fmaxqv  v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x96,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6496a000 <unknown>
+
+fmaxqv  v21.4s, p5, z10.s  // 01100100-10010110-10110101-01010101
+// CHECK-INST: fmaxqv  v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0xb5,0x96,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6496b555 <unknown>
+
+fmaxqv  v23.4s, p3, z13.s  // 01100100-10010110-10101101-10110111
+// CHECK-INST: fmaxqv  v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0xad,0x96,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6496adb7 <unknown>
+
+fmaxqv  v31.4s, p7, z31.s  // 01100100-10010110-10111111-11111111
+// CHECK-INST: fmaxqv  v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x96,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6496bfff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/fminnmqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/fminnmqv-diagnostics.s
new file mode 100644
index 0000000..4e76a56
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/fminnmqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+fminnmqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fminnmqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+fminnmqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminnmqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminnmqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminnmqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+fminnmqv v0.2d, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fminnmqv v0.2d, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/fminnmqv.s b/llvm/test/MC/AArch64/SVE2p1/fminnmqv.s
new file mode 100644
index 0000000..f239ac0
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/fminnmqv.s
@@ -0,0 +1,90 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fminnmqv v0.2d, p0, z0.d  // 01100100-11010101-10100000-00000000
+// CHECK-INST: fminnmqv v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd5,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d5a000 <unknown>
+
+fminnmqv v21.2d, p5, z10.d  // 01100100-11010101-10110101-01010101
+// CHECK-INST: fminnmqv v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0xb5,0xd5,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d5b555 <unknown>
+
+fminnmqv v23.2d, p3, z13.d  // 01100100-11010101-10101101-10110111
+// CHECK-INST: fminnmqv v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0xad,0xd5,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d5adb7 <unknown>
+
+fminnmqv v31.2d, p7, z31.d  // 01100100-11010101-10111111-11111111
+// CHECK-INST: fminnmqv v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xd5,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d5bfff <unknown>
+
+
+fminnmqv v0.8h, p0, z0.h  // 01100100-01010101-10100000-00000000
+// CHECK-INST: fminnmqv v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x55,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6455a000 <unknown>
+
+fminnmqv v21.8h, p5, z10.h  // 01100100-01010101-10110101-01010101
+// CHECK-INST: fminnmqv v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0xb5,0x55,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6455b555 <unknown>
+
+fminnmqv v23.8h, p3, z13.h  // 01100100-01010101-10101101-10110111
+// CHECK-INST: fminnmqv v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0xad,0x55,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6455adb7 <unknown>
+
+fminnmqv v31.8h, p7, z31.h  // 01100100-01010101-10111111-11111111
+// CHECK-INST: fminnmqv v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x55,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6455bfff <unknown>
+
+
+fminnmqv v0.4s, p0, z0.s  // 01100100-10010101-10100000-00000000
+// CHECK-INST: fminnmqv v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x95,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6495a000 <unknown>
+
+fminnmqv v21.4s, p5, z10.s  // 01100100-10010101-10110101-01010101
+// CHECK-INST: fminnmqv v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0xb5,0x95,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6495b555 <unknown>
+
+fminnmqv v23.4s, p3, z13.s  // 01100100-10010101-10101101-10110111
+// CHECK-INST: fminnmqv v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0xad,0x95,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6495adb7 <unknown>
+
+fminnmqv v31.4s, p7, z31.s  // 01100100-10010101-10111111-11111111
+// CHECK-INST: fminnmqv v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x95,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6495bfff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/fminqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/fminqv-diagnostics.s
new file mode 100644
index 0000000..787529e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/fminqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+fminqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fminqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+fminqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+fminqv v0.2d, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fminqv v0.2d, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/fminqv.s b/llvm/test/MC/AArch64/SVE2p1/fminqv.s
new file mode 100644
index 0000000..480f496b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/fminqv.s
@@ -0,0 +1,90 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+fminqv  v0.2d, p0, z0.d  // 01100100-11010111-10100000-00000000
+// CHECK-INST: fminqv  v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xd7,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d7a000 <unknown>
+
+fminqv  v21.2d, p5, z10.d  // 01100100-11010111-10110101-01010101
+// CHECK-INST: fminqv  v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0xb5,0xd7,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d7b555 <unknown>
+
+fminqv  v23.2d, p3, z13.d  // 01100100-11010111-10101101-10110111
+// CHECK-INST: fminqv  v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0xad,0xd7,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d7adb7 <unknown>
+
+fminqv  v31.2d, p7, z31.d  // 01100100-11010111-10111111-11111111
+// CHECK-INST: fminqv  v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xd7,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64d7bfff <unknown>
+
+
+fminqv  v0.8h, p0, z0.h  // 01100100-01010111-10100000-00000000
+// CHECK-INST: fminqv  v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x57,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6457a000 <unknown>
+
+fminqv  v21.8h, p5, z10.h  // 01100100-01010111-10110101-01010101
+// CHECK-INST: fminqv  v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0xb5,0x57,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6457b555 <unknown>
+
+fminqv  v23.8h, p3, z13.h  // 01100100-01010111-10101101-10110111
+// CHECK-INST: fminqv  v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0xad,0x57,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6457adb7 <unknown>
+
+fminqv  v31.8h, p7, z31.h  // 01100100-01010111-10111111-11111111
+// CHECK-INST: fminqv  v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x57,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6457bfff <unknown>
+
+
+fminqv  v0.4s, p0, z0.s  // 01100100-10010111-10100000-00000000
+// CHECK-INST: fminqv  v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x97,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6497a000 <unknown>
+
+fminqv  v21.4s, p5, z10.s  // 01100100-10010111-10110101-01010101
+// CHECK-INST: fminqv  v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0xb5,0x97,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6497b555 <unknown>
+
+fminqv  v23.4s, p3, z13.s  // 01100100-10010111-10101101-10110111
+// CHECK-INST: fminqv  v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0xad,0x97,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6497adb7 <unknown>
+
+fminqv  v31.4s, p7, z31.s  // 01100100-10010111-10111111-11111111
+// CHECK-INST: fminqv  v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x97,0x64]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 6497bfff <unknown>
+