From: Jaehoon Chung Date: Tue, 12 Mar 2024 10:33:31 +0000 (+0900) Subject: RISCV: configs: tizen_visoinfive2: Disable RISCV_ISA_V config X-Git-Tag: accepted/tizen/unified/x/20240313.092112~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=163de2e4bc2cd939bb937d3ff12ff685b0cb32f7;p=platform%2Fkernel%2Flinux-starfive.git RISCV: configs: tizen_visoinfive2: Disable RISCV_ISA_V config Visionfive2 doesn't support V extenstion. It needs to disable its configuration. Change-Id: I6b6ddc5b7027cdd6bd411f53df787e22e48993af Signed-off-by: Jaehoon Chung --- diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index ec813e2ecc3e..26460ddfc6e2 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -29,6 +29,7 @@ CONFIG_PROFILING=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_SMP=y +# CONFIG_RISCV_ISA_V is not set CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y