From: Vidya Sagar Date: Thu, 5 Sep 2019 10:45:48 +0000 (+0530) Subject: dt-bindings: PCI: tegra: Add sideband pins configuration entries X-Git-Tag: v5.4-rc1~63^2~2^2~5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=151481ef5e360af4ca68835943a036339d3c7826;p=platform%2Fkernel%2Flinux-rpi.git dt-bindings: PCI: tegra: Add sideband pins configuration entries Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin configuration information of a particular PCIe controller. Signed-off-by: Vidya Sagar Signed-off-by: Lorenzo Pieralisi Reviewed-by: Andrew Murray Reviewed-by: Rob Herring Acked-by: Thierry Reding --- diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt index 674e5ad..0ac1b86 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -83,6 +83,11 @@ Required properties: - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals Optional properties: +- pinctrl-names: A list of pinctrl state names. + It is mandatory for C5 controller and optional for other controllers. + - "default": Configures PCIe I/O for proper operation. +- pinctrl-0: phandle for the 'default' state of pin configuration. + It is mandatory for C5 controller and optional for other controllers. - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt - nvidia,update-fc-fixup: This is a boolean property and needs to be present to improve performance when a platform is designed in such a way that it @@ -120,6 +125,9 @@ Tegra194: num-lanes = <8>; linux,pci-domain = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; clock-names = "core";