From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 12 Aug 2019 12:13:08 +0000 (+0000)
Subject: [X86][SSE] Add test showing missing compute known bits PSADBW handling
X-Git-Tag: llvmorg-11-init~12152
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=143a2b88ba66cf70ab667b90bc2a846f14464bd6;p=platform%2Fupstream%2Fllvm.git

[X86][SSE] Add test showing missing compute known bits PSADBW handling

The upper 48-bits of each i64 element is guaranteed to be zero.

llvm-svn: 368557
---

diff --git a/llvm/test/CodeGen/X86/psadbw.ll b/llvm/test/CodeGen/X86/psadbw.ll
new file mode 100644
index 0000000..ea0ac22
--- /dev/null
+++ b/llvm/test/CodeGen/X86/psadbw.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
+
+; Only bottom 16 bits are set - upper 48 bits are zero.
+define <2 x i64> @combine_psadbw_shift(<16 x i8> %0, <16 x i8> %1) {
+; CHECK-LABEL: combine_psadbw_shift:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    psadbw %xmm1, %xmm0
+; CHECK-NEXT:    psrlq $48, %xmm0
+; CHECK-NEXT:    ret{{[l|q]}}
+  %3 = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %0, <16 x i8> %1)
+  %4 = lshr <2 x i64> %3, <i64 48, i64 48>
+  ret <2 x i64> %4
+}
+
+declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>)
+