From: Steve Wise <swise@opengridcomputing.com>
Date: Fri, 10 Sep 2010 16:14:53 +0000 (-0500)
Subject: RDMA/cxgb4: Zero out ISGL padding
X-Git-Tag: v2.6.37-rc1~95^2^4~16
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=13fecb83b410b147343e6c7b0427d244ef77b526;p=profile%2Fivi%2Fkernel-x86-ivi.git

RDMA/cxgb4: Zero out ISGL padding

The HW design requires zeroing any pad in SGLs.

Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
---

diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c
index 4f5dd66..bdbf54d 100644
--- a/drivers/infiniband/hw/cxgb4/qp.c
+++ b/drivers/infiniband/hw/cxgb4/qp.c
@@ -263,6 +263,9 @@ static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 			rem -= len;
 		}
 	}
+	len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
+	if (len)
+		memset(dstp, 0, len);
 	immdp->op = FW_RI_DATA_IMMD;
 	immdp->r1 = 0;
 	immdp->r2 = 0;
@@ -292,6 +295,7 @@ static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 		if (++flitp == queue_end)
 			flitp = queue_start;
 	}
+	*flitp = (__force __be64)0;
 	isglp->op = FW_RI_DATA_ISGL;
 	isglp->r1 = 0;
 	isglp->nsge = cpu_to_be16(num_sge);