From: Craig Topper Date: Mon, 1 May 2023 19:05:16 +0000 (-0700) Subject: [RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp. X-Git-Tag: upstream/17.0.6~9876 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=13fe6733019a9b597ac4b938c5500fa6531d614d;p=platform%2Fupstream%2Fllvm.git [RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp. Rather than having a separate pass to add the hint instructions, emit them directly into the streamer during asm printing. Reviewed By: BeMg, kito-cheng Differential Revision: https://reviews.llvm.org/D149511 --- diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt index a005a2f..d2f952c 100644 --- a/llvm/lib/Target/RISCV/CMakeLists.txt +++ b/llvm/lib/Target/RISCV/CMakeLists.txt @@ -26,7 +26,6 @@ add_llvm_target(RISCVCodeGen RISCVExpandPseudoInsts.cpp RISCVFrameLowering.cpp RISCVGatherScatterLowering.cpp - RISCVInsertNTLHInsts.cpp RISCVInsertVSETVLI.cpp RISCVInstrInfo.cpp RISCVISelDAGToDAG.cpp diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h index e0cf1cd..f4f378e 100644 --- a/llvm/lib/Target/RISCV/RISCV.h +++ b/llvm/lib/Target/RISCV/RISCV.h @@ -62,9 +62,6 @@ void initializeRISCVPreRAExpandPseudoPass(PassRegistry &); FunctionPass *createRISCVExpandAtomicPseudoPass(); void initializeRISCVExpandAtomicPseudoPass(PassRegistry &); -FunctionPass *createRISCVInsertNTLHInstsPass(); -void initializeRISCVInsertNTLHInstsPass(PassRegistry &); - FunctionPass *createRISCVInsertVSETVLIPass(); void initializeRISCVInsertVSETVLIPass(PassRegistry &); diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index efb45ea..30aed87 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -85,6 +85,8 @@ public: private: void emitAttributes(); + + void emitNTLHint(const MachineInstr *MI); }; } @@ -100,10 +102,44 @@ void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { // instructions) auto-generated. #include "RISCVGenMCPseudoLowering.inc" +// If the target supports Zihintnthl and the instruction has a nontemporal +// MachineMemOperand, emit an NTLH hint instruction before it. +void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) { + if (!STI->hasStdExtZihintntl()) + return; + + if (MI->memoperands_empty()) + return; + + MachineMemOperand *MMO = *(MI->memoperands_begin()); + if (!MMO->isNonTemporal()) + return; + + unsigned NontemporalMode = 0; + if (MMO->getFlags() & MONontemporalBit0) + NontemporalMode += 0b1; + if (MMO->getFlags() & MONontemporalBit1) + NontemporalMode += 0b10; + + MCInst Hint; + if (STI->hasStdExtCOrZca() && STI->enableRVCHintInstrs()) + Hint.setOpcode(RISCV::C_ADD_HINT); + else + Hint.setOpcode(RISCV::ADD); + + Hint.addOperand(MCOperand::createReg(RISCV::X0)); + Hint.addOperand(MCOperand::createReg(RISCV::X0)); + Hint.addOperand(MCOperand::createReg(RISCV::X2 + NontemporalMode)); + + EmitToStreamer(*OutStreamer, Hint); +} + void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) { RISCV_MC::verifyInstructionPredicates(MI->getOpcode(), getSubtargetInfo().getFeatureBits()); + emitNTLHint(MI); + // Do any auto-generated pseudo lowerings. if (emitPseudoExpansionLowering(*OutStreamer, MI)) return; diff --git a/llvm/lib/Target/RISCV/RISCVInsertNTLHInsts.cpp b/llvm/lib/Target/RISCV/RISCVInsertNTLHInsts.cpp deleted file mode 100644 index 30f74b6..0000000 --- a/llvm/lib/Target/RISCV/RISCVInsertNTLHInsts.cpp +++ /dev/null @@ -1,108 +0,0 @@ -//===-- RISCVInsertNTLHInsts.cpp - Insert NTLH extension instrution -------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file implements a function pass that inserts non-temporal hint -// instructions where needed. -// -// It checks the MachineMemOperand of all MachineInstr. -// If the instruction has a MachineMemOperand and isNontemporal is true, -// then ntlh instruction is inserted before it. -// -//===----------------------------------------------------------------------===// - -#include "RISCV.h" -#include "RISCVInstrInfo.h" -#include "RISCVTargetMachine.h" - -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" - -using namespace llvm; - -#define RISCV_INSERT_NTLH_INSTS_NAME "RISC-V insert NTLH instruction pass" - -namespace { - -class RISCVInsertNTLHInsts : public MachineFunctionPass { -public: - const RISCVInstrInfo *TII; - static char ID; - - RISCVInsertNTLHInsts() : MachineFunctionPass(ID) { - initializeRISCVInsertNTLHInstsPass(*PassRegistry::getPassRegistry()); - } - - bool runOnMachineFunction(MachineFunction &MF) override; - - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesCFG(); - MachineFunctionPass::getAnalysisUsage(AU); - } - - StringRef getPassName() const override { - return RISCV_INSERT_NTLH_INSTS_NAME; - } -}; - -} // end of anonymous namespace - -char RISCVInsertNTLHInsts::ID = 0; - -bool RISCVInsertNTLHInsts::runOnMachineFunction(MachineFunction &MF) { - const auto &ST = MF.getSubtarget(); - TII = ST.getInstrInfo(); - - if (!ST.hasStdExtZihintntl()) - return false; - - bool Changed = false; - for (auto &MBB : MF) { - for (auto &MBBI : MBB) { - if (MBBI.memoperands_empty()) - continue; - MachineMemOperand *MMO = *(MBBI.memoperands_begin()); - if (MMO->isNonTemporal()) { - uint64_t NontemporalMode = 0; - if (MMO->getFlags() & MONontemporalBit0) - NontemporalMode += 0b1; - if (MMO->getFlags() & MONontemporalBit1) - NontemporalMode += 0b10; - - static const uint16_t NTLOpc[] = { - RISCV::PseudoNTLP1, RISCV::PseudoNTLPALL, RISCV::PseudoNTLS1, - RISCV::PseudoNTLALL}; - static const uint16_t CNTLOpc[] = { - RISCV::PseudoCNTLP1, RISCV::PseudoCNTLPALL, RISCV::PseudoCNTLS1, - RISCV::PseudoCNTLALL}; - - unsigned CurrNTLOpc; - DebugLoc DL = MBBI.getDebugLoc(); - if (ST.hasStdExtCOrZca() && ST.enableRVCHintInstrs()) - CurrNTLOpc = CNTLOpc[NontemporalMode]; - else - CurrNTLOpc = NTLOpc[NontemporalMode]; - - BuildMI(MBB, MBBI, DL, TII->get(CurrNTLOpc)); - Changed = true; - } - } - } - - return Changed; -} - -INITIALIZE_PASS(RISCVInsertNTLHInsts, "riscv-insert-ntlh-insts", - RISCV_INSERT_NTLH_INSTS_NAME, false, false) - -namespace llvm { - -FunctionPass *createRISCVInsertNTLHInstsPass() { - return new RISCVInsertNTLHInsts(); -} - -} // end of namespace llvm diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 5e1131a..6a34a21 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1911,7 +1911,6 @@ include "RISCVInstrInfoZfa.td" include "RISCVInstrInfoZfh.td" include "RISCVInstrInfoZicbo.td" include "RISCVInstrInfoZicond.td" -include "RISCVInstrInfoZihintntl.td" //===----------------------------------------------------------------------===// // Vendor extensions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZihintntl.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintntl.td deleted file mode 100644 index b8adaf4..0000000 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZihintntl.td +++ /dev/null @@ -1,34 +0,0 @@ -//===RISCVInstrInfoZihintntl.td - 'Zihintntl' instructions -*- tablegen -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -/// -/// This file describes the RISC-V instructions from Non-Temporal Locality -/// Hints extension document (zihintntl). -/// -//===----------------------------------------------------------------------===// - -let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 4 in { - def PseudoNTLP1 : Pseudo<(outs), (ins), [], "ntl.p1">, - PseudoInstExpansion<(ADD X0, X0, X2)>; - def PseudoNTLPALL : Pseudo<(outs), (ins), [], "ntl.pall">, - PseudoInstExpansion<(ADD X0, X0, X3)>; - def PseudoNTLS1 : Pseudo<(outs), (ins), [], "ntl.s1">, - PseudoInstExpansion<(ADD X0, X0, X4)>; - def PseudoNTLALL : Pseudo<(outs), (ins), [], "ntl.all">, - PseudoInstExpansion<(ADD X0, X0, X5)>; -} - -let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 2 in { - def PseudoCNTLP1 : Pseudo<(outs), (ins), [], "c.ntl.p1">, - PseudoInstExpansion<(C_ADD_HINT X0, X0, X2)>; - def PseudoCNTLPALL : Pseudo<(outs), (ins), [], "c.ntl.pall">, - PseudoInstExpansion<(C_ADD_HINT X0, X0, X3)>; - def PseudoCNTLS1 : Pseudo<(outs), (ins), [], "c.ntl.s1">, - PseudoInstExpansion<(C_ADD_HINT X0, X0, X4)>; - def PseudoCNTLALL : Pseudo<(outs), (ins), [], "c.ntl.all">, - PseudoInstExpansion<(C_ADD_HINT X0, X0, X5)>; -} diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 75a9ed7..5943847 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -83,7 +83,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { initializeRISCVOptWInstrsPass(*PR); initializeRISCVPreRAExpandPseudoPass(*PR); initializeRISCVExpandPseudoPass(*PR); - initializeRISCVInsertNTLHInstsPass(*PR); initializeRISCVInsertVSETVLIPass(*PR); initializeRISCVDAGToDAGISelPass(*PR); initializeRISCVInitUndefPass(*PR); @@ -349,7 +348,6 @@ void RISCVPassConfig::addPreEmitPass() { void RISCVPassConfig::addPreEmitPass2() { addPass(createRISCVExpandPseudoPass()); - addPass(createRISCVInsertNTLHInstsPass()); // Schedule the expansion of AMOs at the last possible moment, avoiding the // possibility for other passes to break the requirements for forward diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll index 779abf8..f18e6a34 100644 --- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll @@ -64,7 +64,6 @@ ; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Stack Frame Layout Analysis ; CHECK-NEXT: RISC-V pseudo instruction expansion pass -; CHECK-NEXT: RISC-V insert NTLH instruction pass ; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index 539e91f..9179c8c 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -177,7 +177,6 @@ ; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Stack Frame Layout Analysis ; CHECK-NEXT: RISC-V pseudo instruction expansion pass -; CHECK-NEXT: RISC-V insert NTLH instruction pass ; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter