From: Craig Topper <craig.topper@gmail.com>
Date: Fri, 15 Apr 2016 06:20:14 +0000 (+0000)
Subject: [X86] AND, OR, and XOR of vectors are always legal no need to set them legal explicitly.
X-Git-Tag: llvmorg-3.9.0-rc1~9012
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=13e9dc66e4046c36138a0e138d97d684aeeb6e6e;p=platform%2Fupstream%2Fllvm.git

[X86] AND, OR, and XOR of vectors are always legal no need to set them legal explicitly.

llvm-svn: 266412
---

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index eb9e31c..61e4846 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1465,11 +1465,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
     // Custom lower several nodes.
     for (MVT VT : MVT::vector_valuetypes()) {
       unsigned EltSize = VT.getVectorElementType().getSizeInBits();
-      if (EltSize == 1) {
-        setOperationAction(ISD::AND, VT, Legal);
-        setOperationAction(ISD::OR,  VT, Legal);
-        setOperationAction(ISD::XOR,  VT, Legal);
-      }
       if ((VT.is128BitVector() || VT.is256BitVector()) && EltSize >= 32) {
         setOperationAction(ISD::MGATHER,  VT, Custom);
         setOperationAction(ISD::MSCATTER, VT, Custom);