From: Thomas Bogendoerfer Date: Thu, 15 Jun 2023 09:39:33 +0000 (+0200) Subject: MIPS: mm: Remove special handling for OCTEON CPUs X-Git-Tag: v6.6.17~4398^2~34 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=13e6b8122d448b07d16a3d9c0d0ab41d00a3f284;p=platform%2Fkernel%2Flinux-rpi.git MIPS: mm: Remove special handling for OCTEON CPUs Macro cpu_has_mips_r2_exec_hazard correctly handles OCTEON CPUs, so we don't need the extra switch cases for them. Signed-off-by: Thomas Bogendoerfer --- diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 80e05ee..8d514a9 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2123,16 +2123,8 @@ static void build_r4000_tlb_load_handler(void) uasm_i_tlbr(&p); - switch (current_cpu_type()) { - case CPU_CAVIUM_OCTEON: - case CPU_CAVIUM_OCTEON_PLUS: - case CPU_CAVIUM_OCTEON2: - break; - default: - if (cpu_has_mips_r2_exec_hazard) - uasm_i_ehb(&p); - break; - } + if (cpu_has_mips_r2_exec_hazard) + uasm_i_ehb(&p); /* Examine entrylo 0 or 1 based on ptr. */ if (use_bbit_insns()) { @@ -2197,16 +2189,8 @@ static void build_r4000_tlb_load_handler(void) uasm_i_tlbr(&p); - switch (current_cpu_type()) { - case CPU_CAVIUM_OCTEON: - case CPU_CAVIUM_OCTEON_PLUS: - case CPU_CAVIUM_OCTEON2: - break; - default: - if (cpu_has_mips_r2_exec_hazard) - uasm_i_ehb(&p); - break; - } + if (cpu_has_mips_r2_exec_hazard) + uasm_i_ehb(&p); /* Examine entrylo 0 or 1 based on ptr. */ if (use_bbit_insns()) {