From: Ben Skeggs Date: Sun, 17 Jan 2010 22:33:04 +0000 (+1000) Subject: drm/nv50: fix alignment of per-channel fifo cache X-Git-Tag: upstream/snapshot3+hdmi~14679^2~84^2~68 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=134f248bea4bf5c3169b4950eb49c6651b09eb0e;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git drm/nv50: fix alignment of per-channel fifo cache GPU pointer to the structure is shifted right by 10 bits, so we need to align to 1024 bytes, not 256. Reported-by: Maarten Maathuis Signed-off-by: Ben Skeggs --- diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c index 39caf16..32b244b 100644 --- a/drivers/gpu/drm/nouveau/nv50_fifo.c +++ b/drivers/gpu/drm/nouveau/nv50_fifo.c @@ -272,7 +272,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan) return ret; ramfc = chan->ramfc->gpuobj; - ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 256, + ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 1024, 0, &chan->cache); if (ret) return ret;