From: Colin LeMahieu Date: Thu, 19 Feb 2015 21:10:50 +0000 (+0000) Subject: [Hexagon] Moving remaining methods off of HexagonMCInst in to HexagonMCInstrInfo... X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1174fea31c85219563798784024a0637bb470309;p=platform%2Fupstream%2Fllvm.git [Hexagon] Moving remaining methods off of HexagonMCInst in to HexagonMCInstrInfo and eliminating HexagonMCInst class. llvm-svn: 229914 --- diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 88f633f..669af8c 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/HexagonBaseInfo.h" -#include "MCTargetDesc/HexagonMCInst.h" +#include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDisassembler.h" @@ -202,6 +202,6 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, // Remove parse bits. insn &= ~static_cast(HexagonII::InstParseBits::INST_PARSE_MASK); DecodeStatus Result = decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); - HexagonMCInst::AppendImplicitOperands(MI); + HexagonMCInstrInfo::AppendImplicitOperands(MI); return Result; } diff --git a/llvm/lib/Target/Hexagon/Hexagon.h b/llvm/lib/Target/Hexagon/Hexagon.h index 1c81f4d..e0a3b2f 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.h +++ b/llvm/lib/Target/Hexagon/Hexagon.h @@ -21,13 +21,13 @@ namespace llvm { class FunctionPass; - class ModulePass; - class TargetMachine; - class MachineInstr; - class HexagonMCInst; class HexagonAsmPrinter; class HexagonTargetMachine; + class MachineInstr; + class MCInst; + class ModulePass; class raw_ostream; + class TargetMachine; FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel); @@ -56,7 +56,7 @@ namespace llvm { TargetAsmBackend *createHexagonAsmBackend(const Target &, const std::string &); */ - void HexagonLowerToMC(const MachineInstr *MI, HexagonMCInst &MCI, + void HexagonLowerToMC(MachineInstr const *MI, MCInst &MCI, HexagonAsmPrinter &AP); } // end namespace llvm; diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp index dd4bf15..180762f 100644 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -19,7 +19,7 @@ #include "HexagonSubtarget.h" #include "HexagonTargetMachine.h" #include "MCTargetDesc/HexagonInstPrinter.h" -#include "MCTargetDesc/HexagonMCInst.h" +#include "MCTargetDesc/HexagonMCInstrInfo.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" @@ -199,22 +199,22 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned Size = BundleMIs.size(); assert((Size + IgnoreCount) == MI->getBundleSize() && "Corrupt Bundle!"); for (unsigned Index = 0; Index < Size; Index++) { - HexagonMCInst MCI; + MCInst MCI; HexagonLowerToMC(BundleMIs[Index], MCI, *this); - HexagonMCInst::AppendImplicitOperands(MCI); - MCI.setPacketBegin(Index == 0); - MCI.setPacketEnd(Index == (Size - 1)); + HexagonMCInstrInfo::AppendImplicitOperands(MCI); + HexagonMCInstrInfo::setPacketBegin(MCI, Index == 0); + HexagonMCInstrInfo::setPacketEnd(MCI, Index == (Size - 1)); EmitToStreamer(OutStreamer, MCI); } } else { - HexagonMCInst MCI; + MCInst MCI; HexagonLowerToMC(MI, MCI, *this); - HexagonMCInst::AppendImplicitOperands(MCI); + HexagonMCInstrInfo::AppendImplicitOperands(MCI); if (MI->getOpcode() == Hexagon::ENDLOOP0) { - MCI.setPacketBegin(true); - MCI.setPacketEnd(true); + HexagonMCInstrInfo::setPacketBegin(MCI, true); + HexagonMCInstrInfo::setPacketEnd(MCI, true); } EmitToStreamer(OutStreamer, MCI); } diff --git a/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp b/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp index 3f5d6d8..9c9f3af 100644 --- a/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -15,7 +15,6 @@ #include "Hexagon.h" #include "HexagonAsmPrinter.h" #include "HexagonMachineFunctionInfo.h" -#include "MCTargetDesc/HexagonMCInst.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Mangler.h" @@ -39,7 +38,7 @@ static MCOperand GetSymbolRef(const MachineOperand& MO, const MCSymbol* Symbol, } // Create an MCInst from a MachineInstr -void llvm::HexagonLowerToMC(const MachineInstr* MI, HexagonMCInst& MCI, +void llvm::HexagonLowerToMC(MachineInstr const* MI, MCInst& MCI, HexagonAsmPrinter& AP) { MCI.setOpcode(MI->getOpcode()); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt index b4afc50..4c987ed 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt @@ -4,7 +4,6 @@ add_llvm_library(LLVMHexagonDesc HexagonInstPrinter.cpp HexagonMCAsmInfo.cpp HexagonMCCodeEmitter.cpp - HexagonMCInst.cpp HexagonMCInstrInfo.cpp HexagonMCTargetDesc.cpp ) diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp index 5c6f036..6c87c9f 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp @@ -14,7 +14,7 @@ #include "HexagonAsmPrinter.h" #include "Hexagon.h" #include "HexagonInstPrinter.h" -#include "MCTargetDesc/HexagonMCInst.h" +#include "MCTargetDesc/HexagonMCInstrInfo.h" #include "llvm/ADT/StringExtras.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" @@ -77,46 +77,41 @@ StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const { return getRegisterName(RegNo); } -void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot) { - printInst((const HexagonMCInst*)(MI), O, Annot); -} - -void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O, +void HexagonInstPrinter::printInst(MCInst const *MI, raw_ostream &O, StringRef Annot) { const char startPacket = '{', endPacket = '}'; // TODO: add outer HW loop when it's supported too. if (MI->getOpcode() == Hexagon::ENDLOOP0) { // Ending a harware loop is different from ending an regular packet. - assert(MI->isPacketEnd() && "Loop-end must also end the packet"); + assert(HexagonMCInstrInfo::isPacketEnd(*MI) && "Loop-end must also end the packet"); - if (MI->isPacketBegin()) { + if (HexagonMCInstrInfo::isPacketBegin(*MI)) { // There must be a packet to end a loop. // FIXME: when shuffling is always run, this shouldn't be needed. - HexagonMCInst Nop; + MCInst Nop; StringRef NoAnnot; Nop.setOpcode (Hexagon::A2_nop); - Nop.setPacketBegin (MI->isPacketBegin()); + HexagonMCInstrInfo::setPacketBegin (Nop, HexagonMCInstrInfo::isPacketBegin(*MI)); printInst (&Nop, O, NoAnnot); } // Close the packet. - if (MI->isPacketEnd()) + if (HexagonMCInstrInfo::isPacketEnd(*MI)) O << PacketPadding << endPacket; printInstruction(MI, O); } else { // Prefix the insn opening the packet. - if (MI->isPacketBegin()) + if (HexagonMCInstrInfo::isPacketBegin(*MI)) O << PacketPadding << startPacket << '\n'; printInstruction(MI, O); // Suffix the insn closing the packet. - if (MI->isPacketEnd()) + if (HexagonMCInstrInfo::isPacketEnd(*MI)) // Suffix the packet in a new line always, since the GNU assembler has // issues with a closing brace on the same line as CONST{32,64}. O << '\n' << PacketPadding << endPacket; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h index 55ae95c..d02243b 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h @@ -18,17 +18,14 @@ #include "llvm/MC/MCInstrInfo.h" namespace llvm { - class HexagonMCInst; - class HexagonInstPrinter : public MCInstPrinter { public: - explicit HexagonInstPrinter(const MCAsmInfo &MAI, - const MCInstrInfo &MII, - const MCRegisterInfo &MRI) + explicit HexagonInstPrinter(MCAsmInfo const &MAI, + MCInstrInfo const &MII, + MCRegisterInfo const &MRI) : MCInstPrinter(MAI, MII, MRI), MII(MII) {} - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; - void printInst(const HexagonMCInst *MI, raw_ostream &O, StringRef Annot); + void printInst(MCInst const *MI, raw_ostream &O, StringRef Annot) override; virtual StringRef getOpcodeName(unsigned Opcode) const; void printInstruction(const MCInst *MI, raw_ostream &O); StringRef getRegName(unsigned RegNo) const; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 3138081..153d9d8 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -10,7 +10,6 @@ #include "Hexagon.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonMCCodeEmitter.h" -#include "MCTargetDesc/HexagonMCInst.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/ADT/Statistic.h" @@ -36,9 +35,9 @@ namespace { /// Possible values for instruction packet parse field. enum class ParseField { duplex = 0x0, last0 = 0x1, last1 = 0x2, end = 0x3 }; /// \brief Returns the packet bits based on instruction position. -uint32_t getPacketBits(HexagonMCInst const &HMI) { +uint32_t getPacketBits(MCInst const &HMI) { unsigned const ParseFieldOffset = 14; - ParseField Field = HMI.isPacketEnd() ? ParseField::end : ParseField::last0; + ParseField Field = HexagonMCInstrInfo::isPacketEnd(HMI) ? ParseField::end : ParseField::last0; return static_cast (Field) << ParseFieldOffset; } void emitLittleEndian(uint64_t Binary, raw_ostream &OS) { @@ -57,9 +56,8 @@ HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII, void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl &Fixups, MCSubtargetInfo const &STI) const { - HexagonMCInst const &HMB = static_cast(MI); - uint64_t Binary = getBinaryCodeForInstr(HMB, Fixups, STI) | getPacketBits(HMB); - assert(HexagonMCInstrInfo::getDesc(MCII, HMB).getSize() == 4 && + uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI) | getPacketBits(MI); + assert(HexagonMCInstrInfo::getDesc(MCII, MI).getSize() == 4 && "All instructions should be 32bit"); emitLittleEndian(Binary, OS); ++MCNumEmitted; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp deleted file mode 100644 index 0fded45..0000000 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp +++ /dev/null @@ -1,66 +0,0 @@ -//===- HexagonMCInst.cpp - Hexagon sub-class of MCInst --------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This class extends MCInst to allow some Hexagon VLIW annotations. -// -//===----------------------------------------------------------------------===// - -#include "MCTargetDesc/HexagonBaseInfo.h" -#include "MCTargetDesc/HexagonMCInst.h" -#include "MCTargetDesc/HexagonMCInstrInfo.h" -#include "MCTargetDesc/HexagonMCTargetDesc.h" - -using namespace llvm; - -HexagonMCInst::HexagonMCInst() : MCII (createHexagonMCInstrInfo ()) {} -HexagonMCInst::HexagonMCInst(MCInstrDesc const &mcid) : - MCII (createHexagonMCInstrInfo ()){} - -void HexagonMCInst::AppendImplicitOperands(MCInst &MCI) { - MCI.addOperand(MCOperand::CreateImm(0)); - MCI.addOperand(MCOperand::CreateInst(nullptr)); -} - -std::bitset<16> HexagonMCInst::GetImplicitBits(MCInst const &MCI) { - SanityCheckImplicitOperands(MCI); - std::bitset<16> Bits(MCI.getOperand(MCI.getNumOperands() - 2).getImm()); - return Bits; -} - -void HexagonMCInst::SetImplicitBits(MCInst &MCI, std::bitset<16> Bits) { - SanityCheckImplicitOperands(MCI); - MCI.getOperand(MCI.getNumOperands() - 2).setImm(Bits.to_ulong()); -} - -void HexagonMCInst::setPacketBegin(bool f) { - std::bitset<16> Bits(GetImplicitBits(*this)); - Bits.set(packetBeginIndex, f); - SetImplicitBits(*this, Bits); -} - -bool HexagonMCInst::isPacketBegin() const { - std::bitset<16> Bits(GetImplicitBits(*this)); - return Bits.test(packetBeginIndex); -} - -void HexagonMCInst::setPacketEnd(bool f) { - std::bitset<16> Bits(GetImplicitBits(*this)); - Bits.set(packetEndIndex, f); - SetImplicitBits(*this, Bits); -} - -bool HexagonMCInst::isPacketEnd() const { - std::bitset<16> Bits(GetImplicitBits(*this)); - return Bits.test(packetEndIndex); -} - -void HexagonMCInst::resetPacket() { - setPacketBegin(false); - setPacketEnd(false); -} diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h deleted file mode 100644 index 71cbdd1..0000000 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h +++ /dev/null @@ -1,54 +0,0 @@ -//===- HexagonMCInst.h - Hexagon sub-class of MCInst ----------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This class extends MCInst to allow some VLIW annotations. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINST_H -#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINST_H - -#include "HexagonTargetMachine.h" -#include "llvm/MC/MCInst.h" -#include - -extern "C" void LLVMInitializeHexagonTargetMC(); -namespace llvm { -class MCOperand; - -class HexagonMCInst : public MCInst { - // Used to access TSFlags - std::unique_ptr MCII; - -public: - explicit HexagonMCInst(); - HexagonMCInst(const MCInstrDesc &mcid); - - static void AppendImplicitOperands(MCInst &MCI); - static std::bitset<16> GetImplicitBits(MCInst const &MCI); - static void SetImplicitBits(MCInst &MCI, std::bitset<16> Bits); - static void SanityCheckImplicitOperands(MCInst const &MCI) { - assert(MCI.getNumOperands() >= 2 && "At least the two implicit operands"); - assert(MCI.getOperand(MCI.getNumOperands() - 1).isInst() && - "Implicit bits and flags"); - assert(MCI.getOperand(MCI.getNumOperands() - 2).isImm() && - "Parent pointer"); - } - - void setPacketBegin(bool Y); - bool isPacketBegin() const; - static const size_t packetBeginIndex = 0; - void setPacketEnd(bool Y); - bool isPacketEnd() const; - static const size_t packetEndIndex = 1; - void resetPacket(); -}; -} - -#endif diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp index 39e881b..33e7c81 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -13,20 +13,19 @@ #include "HexagonMCInstrInfo.h" #include "HexagonBaseInfo.h" -#include "llvm/MC/MCInstrInfo.h" namespace llvm { +void HexagonMCInstrInfo::AppendImplicitOperands(MCInst &MCI) { + MCI.addOperand(MCOperand::CreateImm(0)); + MCI.addOperand(MCOperand::CreateInst(nullptr)); +} + unsigned HexagonMCInstrInfo::getBitCount(MCInstrInfo const &MCII, MCInst const &MCI) { uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask); } -MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, - MCInst const &MCI) { - return (MCII.get(MCI.getOpcode())); -} - // Return constant extended operand number. unsigned short HexagonMCInstrInfo::getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI) { @@ -34,6 +33,17 @@ unsigned short HexagonMCInstrInfo::getCExtOpNum(MCInstrInfo const &MCII, return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask); } +MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, + MCInst const &MCI) { + return (MCII.get(MCI.getOpcode())); +} + +std::bitset<16> HexagonMCInstrInfo::GetImplicitBits(MCInst const &MCI) { + SanityCheckImplicitOperands(MCI); + std::bitset<16> Bits(MCI.getOperand(MCI.getNumOperands() - 2).getImm()); + return Bits; +} + // Return the max value that a constant extendable operand can have // without being extended. int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII, @@ -168,6 +178,16 @@ bool HexagonMCInstrInfo::isOperandExtended(MCInstrInfo const &MCII, OperandNum; } +bool HexagonMCInstrInfo::isPacketBegin(MCInst const &MCI) { + std::bitset<16> Bits(GetImplicitBits(MCI)); + return Bits.test(packetBeginIndex); +} + +bool HexagonMCInstrInfo::isPacketEnd(MCInst const &MCI) { + std::bitset<16> Bits(GetImplicitBits(MCI)); + return Bits.test(packetEndIndex); +} + // Return whether the insn is a prefix. bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) { return (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypePREFIX); @@ -178,4 +198,26 @@ bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) { const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask); } + +void HexagonMCInstrInfo::resetPacket(MCInst &MCI) { + setPacketBegin(MCI, false); + setPacketEnd(MCI, false); +} + +void HexagonMCInstrInfo::SetImplicitBits(MCInst &MCI, std::bitset<16> Bits) { + SanityCheckImplicitOperands(MCI); + MCI.getOperand(MCI.getNumOperands() - 2).setImm(Bits.to_ulong()); +} + +void HexagonMCInstrInfo::setPacketBegin(MCInst &MCI, bool f) { + std::bitset<16> Bits(GetImplicitBits(MCI)); + Bits.set(packetBeginIndex, f); + SetImplicitBits(MCI, Bits); +} + +void HexagonMCInstrInfo::setPacketEnd(MCInst &MCI, bool f) { + std::bitset<16> Bits(GetImplicitBits(MCI)); + Bits.set(packetEndIndex, f); + SetImplicitBits(MCI, Bits); +} } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h index d5c2a47..10fc0f3 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h @@ -14,12 +14,18 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H +#include "llvm/MC/MCInstrInfo.h" + +#include + namespace llvm { class MCInstrDesc; class MCInstrInfo; class MCInst; class MCOperand; namespace HexagonMCInstrInfo { +void AppendImplicitOperands(MCInst &MCI); + // Return number of bits in the constant extended operand. unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI); @@ -28,6 +34,8 @@ unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI); MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI); +std::bitset<16> GetImplicitBits(MCInst const &MCI); + // Return the max value that a constant extendable operand can have // without being extended. int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI); @@ -64,11 +72,34 @@ bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI); bool isOperandExtended(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short OperandNum); +bool isPacketBegin(MCInst const &MCI); + +bool isPacketEnd(MCInst const &MCI); + // Return whether the insn is a prefix. bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI); // Return whether the insn is solo, i.e., cannot be in a packet. bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI); + +static const size_t packetBeginIndex = 0; +static const size_t packetEndIndex = 1; + +void resetPacket(MCInst &MCI); + +inline void SanityCheckImplicitOperands(MCInst const &MCI) { + assert(MCI.getNumOperands() >= 2 && "At least the two implicit operands"); + assert(MCI.getOperand(MCI.getNumOperands() - 1).isInst() && + "Implicit bits and flags"); + assert(MCI.getOperand(MCI.getNumOperands() - 2).isImm() && + "Parent pointer"); +} + +void SetImplicitBits(MCInst &MCI, std::bitset<16> Bits); + +void setPacketBegin(MCInst &MCI, bool Y); + +void setPacketEnd(MCInst &MCI, bool Y); } } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 0c911fd..09a305b 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -14,7 +14,6 @@ #include "HexagonMCTargetDesc.h" #include "HexagonMCAsmInfo.h" #include "MCTargetDesc/HexagonInstPrinter.h" -#include "MCTargetDesc/HexagonMCInst.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCInstrInfo.h"