From: qianqian.cai <qianqian.cai@amlogic.com>
Date: Wed, 16 Oct 2019 09:24:29 +0000 (+0800)
Subject: deintlace: PQ revert the set of di_belend_ctrl [1/2]
X-Git-Tag: hardkernel-4.9.236-104~521
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=114854aac27e1e96d83d36dd55bf5b706e98276f;p=platform%2Fkernel%2Flinux-amlogic.git

deintlace: PQ revert the set of di_belend_ctrl [1/2]

PD#SWPL-14508

Problem:
HDMI480I/AV IN some issue you can see at the subtitle

Solution:
revert the setting of 85992 di_blend_ctrl ,bit16
from vlsi feijun

Verify:
verfy it on the marconi

Change-Id: I78f6abd104d0953b6db7387900425175a436386b
Signed-off-by: qianqian.cai <qianqian.cai@amlogic.com>
---

diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
index 26d0b6c..a946912 100644
--- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
@@ -3840,7 +3840,8 @@ void pulldown_vof_win_config(struct pulldown_detected_s *wins)
 	/* revert the setting of top two lines do weave for */
 	/* interlace video, suggest by vlsi-feijun */
 	DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
-		0, 16, 1);
+		(wins->regs[0].win_ve > wins->regs[0].win_vs)
+		? 1 : 0, 16, 1);
 	DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
 		/*wins->regs[0].blend_mode*/
 				  0x03, 8, 2);