From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
Date: Fri, 6 May 2022 10:34:19 +0000 (+0900)
Subject: xtensa: Reflect the 32-bit Integer Divide Option
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=112447f8564c0307c5da99a4094a3a99f204239f;p=platform%2Fupstream%2Fgcc.git

xtensa: Reflect the 32-bit Integer Divide Option

On Espressif's ESP8266 (based on Tensilica LX106, no hardware divider),
this patch reduces the size of each:

  __moddi3() @ libgcc.a :  969 -> 301 (saves 668)
  __divmoddi4()         : 1111 -> 426 (saves 685)
  __udivmoddi4()        : 1043 -> 319 (saves 724)

in bytes, respectively.

gcc/ChangeLog:

	* config/xtensa/xtensa.h (TARGET_HAS_NO_HW_DIVIDE): New macro
	definition.
---

diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index 00e2930..d25594f 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -75,6 +75,11 @@ along with GCC; see the file COPYING3.  If not see
 #define HAVE_AS_TLS 0
 #endif
 
+/* Define this if the target has no hardware divide instructions.  */
+#if !TARGET_DIV32
+#define TARGET_HAS_NO_HW_DIVIDE
+#endif
+
 
 /* Target CPU builtins.  */
 #define TARGET_CPU_CPP_BUILTINS()					\