From: Pat Haugen <pthaugen@us.ibm.com>
Date: Fri, 5 Feb 2016 15:25:39 +0000 (+0000)
Subject: crypto.md (crypto_vpermxor_<mode>): Correct insn type.
X-Git-Tag: upstream/12.2.0~48955
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=10ecae7407552a200b5485d342be8baf6256f8f6;p=platform%2Fupstream%2Fgcc.git

crypto.md (crypto_vpermxor_<mode>): Correct insn type.

	* config/rs6000/crypto.md (crypto_vpermxor_<mode>): Correct insn type.
	* config/rs6000/rs6000.md (mov<mode>_hardfloat): Likewise.
	(*ieee128_mfvsrd_64bit): Likewise.
	(*ieee128_mfvsrd_32bit): Likewise.

From-SVN: r233179
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3357d85..1e166ae 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-02-05  Pat Haugen  <pthaugen@us.ibm.com>
+
+	* config/rs6000/crypto.md (crypto_vpermxor_<mode>): Correct insn type.
+	* config/rs6000/rs6000.md (mov<mode>_hardfloat): Likewise.
+	(*ieee128_mfvsrd_64bit): Likewise.
+	(*ieee128_mfvsrd_32bit): Likewise.
+
 2016-02-05  Ilya Enkovich  <enkovich.gnu@gmail.com>
 
 	PR target/69369
diff --git a/gcc/config/rs6000/crypto.md b/gcc/config/rs6000/crypto.md
index 43015f0..5957abb 100644
--- a/gcc/config/rs6000/crypto.md
+++ b/gcc/config/rs6000/crypto.md
@@ -87,7 +87,7 @@
 			UNSPEC_VPERMXOR))]
   "TARGET_P8_VECTOR"
   "vpermxor %0,%1,%2,%3"
-  [(set_attr "type" "crypto")])
+  [(set_attr "type" "vecperm")])
 
 ;; 1 operand crypto instruction
 (define_insn "crypto_vsbox"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5614695..6786342 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6521,7 +6521,7 @@
    mt%0 %1
    mf%1 %0
    nop"
-  [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*")
+  [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*")
    (set_attr "length" "4")])
 
 (define_insn "*mov<mode>_softfloat"
@@ -13524,7 +13524,7 @@
    mfvsrd %0,%x1
    stxsdx %x1,%y0
    xxlor %x0,%x1,%x1"
-  [(set_attr "type" "mftgpr,vecsimple,fpstore")])
+  [(set_attr "type" "mftgpr,fpstore,vecsimple")])
 
 
 (define_insn "*ieee128_mfvsrd_32bit"
@@ -13535,7 +13535,7 @@
   "@
    stxsdx %x1,%y0
    xxlor %x0,%x1,%x1"
-  [(set_attr "type" "vecsimple,fpstore")])
+  [(set_attr "type" "fpstore,vecsimple")])
 
 (define_insn "*ieee128_mfvsrwz"
   [(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z")