From: Alexey Bataev <a.bataev@outlook.com>
Date: Wed, 31 Mar 2021 18:21:54 +0000 (-0700)
Subject: [SLP]Add a test for the bug in `getVectorElementSize()`, NFC.
X-Git-Tag: llvmorg-14-init~10780
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=10847f6217b159e01b72a34eb366a543ca612aa6;p=platform%2Fupstream%2Fllvm.git

[SLP]Add a test for the bug in `getVectorElementSize()`, NFC.
---

diff --git a/llvm/test/Transforms/SLPVectorizer/X86/inst_size_bug.ll b/llvm/test/Transforms/SLPVectorizer/X86/inst_size_bug.ll
new file mode 100644
index 0000000..54724df
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/inst_size_bug.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 -slp-max-reg-size=128 | FileCheck %s
+
+define void @inst_size(i64* %a, <2 x i64> %b) {
+; CHECK-LABEL: @inst_size(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[VAL:%.*]] = extractelement <2 x i64> [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMPL1:%.*]] = load i64, i64* [[A:%.*]], align 4
+; CHECK-NEXT:    [[PTR2:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 1
+; CHECK-NEXT:    [[TMPL2:%.*]] = load i64, i64* [[PTR2]], align 4
+; CHECK-NEXT:    [[PTR3:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 2
+; CHECK-NEXT:    [[TMPL3:%.*]] = load i64, i64* [[PTR3]], align 4
+; CHECK-NEXT:    [[PTR4:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 3
+; CHECK-NEXT:    [[TMPL4:%.*]] = load i64, i64* [[PTR4]], align 4
+; CHECK-NEXT:    [[T41:%.*]] = icmp sgt i64 0, [[VAL]]
+; CHECK-NEXT:    [[T42:%.*]] = icmp sgt i64 0, [[TMPL1]]
+; CHECK-NEXT:    [[T43:%.*]] = icmp sgt i64 0, [[TMPL2]]
+; CHECK-NEXT:    [[T44:%.*]] = icmp sgt i64 0, [[TMPL3]]
+; CHECK-NEXT:    [[T45:%.*]] = icmp sgt i64 0, [[TMPL4]]
+; CHECK-NEXT:    br label [[BLOCK:%.*]]
+; CHECK:       block:
+; CHECK-NEXT:    [[PHI1:%.*]] = phi i1 [ [[T41]], [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[PHI2:%.*]] = phi i1 [ [[T42]], [[ENTRY]] ]
+; CHECK-NEXT:    [[PHI3:%.*]] = phi i1 [ [[T43]], [[ENTRY]] ]
+; CHECK-NEXT:    [[PHI4:%.*]] = phi i1 [ [[T44]], [[ENTRY]] ]
+; CHECK-NEXT:    [[PHI5:%.*]] = phi i1 [ [[T45]], [[ENTRY]] ]
+; CHECK-NEXT:    ret void
+;
+entry:
+  %val = extractelement <2 x i64> %b, i32 0
+  %tmpl1 = load i64, i64* %a, align 4
+  %ptr2 = getelementptr inbounds i64, i64* %a, i64 1
+  %tmpl2 = load i64, i64* %ptr2, align 4
+  %ptr3 = getelementptr inbounds i64, i64* %a, i64 2
+  %tmpl3 = load i64, i64* %ptr3, align 4
+  %ptr4 = getelementptr inbounds i64, i64* %a, i64 3
+  %tmpl4 = load i64, i64* %ptr4, align 4
+  %t41 = icmp sgt i64 0, %val
+  %t42 = icmp sgt i64 0, %tmpl1
+  %t43 = icmp sgt i64 0, %tmpl2
+  %t44 = icmp sgt i64 0, %tmpl3
+  %t45 = icmp sgt i64 0, %tmpl4
+  br label %block
+block:
+  %phi1 = phi i1 [ %t41, %entry]
+  %phi2 = phi i1 [ %t42, %entry]
+  %phi3 = phi i1 [ %t43, %entry]
+  %phi4 = phi i1 [ %t44, %entry]
+  %phi5 = phi i1 [ %t45, %entry]
+  ret void
+}