From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Thu, 11 Dec 2014 23:37:34 +0000 (+0000)
Subject: R600/SI: Handle physical registers in getOpRegClass
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=102a70409e54960225da99cb515e0dde911d605e;p=platform%2Fupstream%2Fllvm.git

R600/SI: Handle physical registers in getOpRegClass

llvm-svn: 224079
---

diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp
index 4aa5ac8..9328c2c 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.cpp
+++ b/llvm/lib/Target/R600/SIInstrInfo.cpp
@@ -1242,8 +1242,13 @@ const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   const MCInstrDesc &Desc = get(MI.getOpcode());
   if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
-      Desc.OpInfo[OpNo].RegClass == -1)
-    return MRI.getRegClass(MI.getOperand(OpNo).getReg());
+      Desc.OpInfo[OpNo].RegClass == -1) {
+    unsigned Reg = MI.getOperand(OpNo).getReg();
+
+    if (TargetRegisterInfo::isVirtualRegister(Reg))
+      return MRI.getRegClass(Reg);
+    return RI.getRegClass(Reg);
+  }
 
   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
   return RI.getRegClass(RCID);