From: Axel Lin <axel.lin@gmail.com>
Date: Fri, 1 Oct 2010 05:56:27 +0000 (+0800)
Subject: regulator: max8649 - fix setting extclk_freq
X-Git-Tag: upstream/snapshot3+hdmi~12839^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0f69c897f378bf975c519b1d2455c03d06477dfa;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git

regulator: max8649 - fix setting extclk_freq

The SYNC bits are BIT6 and BIT7 of MAX8649_SYNC register.
pdata->extclk_freq could be [0|1|2].
(MAX8649_EXTCLK_26MHZ|MAX8649_EXTCLK_13MHZ|MAX8649_EXTCLK_19MHZ)
It requires to left shift 6 bits to properly set extclk_freq.

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
---

diff --git a/drivers/regulator/max8649.c b/drivers/regulator/max8649.c
index 4520ace..6b60a9c 100644
--- a/drivers/regulator/max8649.c
+++ b/drivers/regulator/max8649.c
@@ -330,7 +330,7 @@ static int __devinit max8649_regulator_probe(struct i2c_client *client,
 		/* set external clock frequency */
 		info->extclk_freq = pdata->extclk_freq;
 		max8649_set_bits(info->i2c, MAX8649_SYNC, MAX8649_EXT_MASK,
-				 info->extclk_freq);
+				 info->extclk_freq << 6);
 	}
 
 	if (pdata->ramp_timing) {