From: Ronald Wahl <rwahl@gmx.de>
Date: Wed, 10 Oct 2018 13:54:54 +0000 (+0200)
Subject: clk: at91: Fix division by zero in PLL recalc_rate()
X-Git-Tag: v5.4-rc1~2301^2~7^4
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0f5cb0e6225cae2f029944cb8c74617aab6ddd49;p=platform%2Fkernel%2Flinux-rpi.git

clk: at91: Fix division by zero in PLL recalc_rate()

Commit a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL
and DIV values") removed a check that prevents a division by zero. This
now causes a stacktrace when booting the kernel on a at91 platform if
the PLL DIV register contains zero. This commit reintroduces this check.

Fixes: a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...")
Cc: <stable@vger.kernel.org>
Signed-off-by: Ronald Wahl <rwahl@gmx.de>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---

diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 72b6091..dc7fbc7 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -133,6 +133,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 {
 	struct clk_pll *pll = to_clk_pll(hw);
 
+	if (!pll->div || !pll->mul)
+		return 0;
+
 	return (parent_rate / pll->div) * (pll->mul + 1);
 }