From: Maxime Coquelin Date: Wed, 23 Jan 2013 10:27:58 +0000 (+0100) Subject: ARM: mach-ux500: enable 128KB way L2 cache on DB8540 X-Git-Tag: v3.10-rc1~123^2~23^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0f2fa40e464c955e928979331625b5485c292bf0;p=platform%2Fkernel%2Flinux-exynos.git ARM: mach-ux500: enable 128KB way L2 cache on DB8540 DB8540 L2 was configured with 64KB way size, but it has 128KB as AP9540. Fix this by modifying ux500_l2x0_init() to use 128KB way size for all cpus in the x540 family. Signed-off-by: Maxime Coquelin Acked-by: Linus Walleij Signed-off-by: Fabio Baltieri Signed-off-by: Linus Walleij --- diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 1c1609d..f815efe 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -47,8 +47,8 @@ static int __init ux500_l2x0_init(void) /* Unlock before init */ ux500_l2x0_unlock(); - /* DB9540's L2 has 128KB way size */ - if (cpu_is_u9540()) + /* DBx540's L2 has 128KB way size */ + if (cpu_is_ux540_family()) /* 128KB way size */ aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); else