From: Hanjun Guo <hanjun.guo@linaro.org>
Date: Tue, 5 Mar 2019 13:40:58 +0000 (+0800)
Subject: arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs
X-Git-Tag: v5.4-rc1~1357^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0ecc471a2cb7d4d386089445a727f47b59dc9b6e;p=platform%2Fkernel%2Flinux-rpi.git

arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs

HiSilicon Taishan v110 CPUs didn't implement CSV3 field of the
ID_AA64PFR0_EL1 and are not susceptible to Meltdown, so whitelist
the MIDR in kpti_safe_list[] table.

Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangshaokun <zhangshaokun@hisilicon.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index e24e94d..4061de1 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -963,6 +963,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
+		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 		{ /* sentinel */ }
 	};
 	char const *str = "command line option";