From: Eugeni Dodonov Date: Thu, 29 Mar 2012 15:32:24 +0000 (-0300) Subject: drm/i915: add DP_TP_CTL registers X-Git-Tag: v3.12-rc1~2641^2~115^2~24 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0e87f6679807a60efd3280c99544b6997916e987;p=kernel%2Fkernel-generic.git drm/i915: add DP_TP_CTL registers This is one set of those registers for each pipe. v2: use port enum to access individual registers Signed-off-by: Eugeni Dodonov Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 61eca8b..b497753 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4062,4 +4062,20 @@ #define PIPE_DDI_PORT_WIDTH_X2 (1<<1) #define PIPE_DDI_PORT_WIDTH_X4 (3<<1) +/* DisplayPort Transport Control */ +#define DP_TP_CTL_A 0x64040 +#define DP_TP_CTL_B 0x64140 +#define DP_TP_CTL(port) _PORT(port, \ + DP_TP_CTL_A, \ + DP_TP_CTL_B) +#define DP_TP_CTL_ENABLE (1<<31) +#define DP_TP_CTL_MODE_SST (0<<27) +#define DP_TP_CTL_MODE_MST (1<<27) +#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) +#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) +#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) +#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) +#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) +#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) + #endif /* _I915_REG_H_ */