From: Samuel Pitoiset Date: Mon, 27 Mar 2023 17:05:06 +0000 (+0200) Subject: radv: move user_data_0 to the shader info pass X-Git-Tag: upstream/23.3.3~10917 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0e81ec98ce9e52af6f445b4a0c9942857e332cd5;p=platform%2Fupstream%2Fmesa.git radv: move user_data_0 to the shader info pass Using the next stage is enough to determine the base reg. Signed-off-by: Samuel Pitoiset Part-of: --- diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index e1cd7f8..6516db5 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1838,7 +1838,7 @@ radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader struct radv_userdata_info *loc = &ps_shader->info.user_sgprs_locs.shader_data[AC_UD_PS_EPILOG_PC]; - uint32_t base_reg = pipeline->base.user_data_0[MESA_SHADER_FRAGMENT]; + uint32_t base_reg = ps_shader->info.user_data_0; assert(loc->sgpr_idx != -1); assert(loc->num_sgprs == 1); radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, @@ -2167,7 +2167,7 @@ radv_emit_provoking_vertex_mode(struct radv_cmd_buffer *cmd_buffer) } } - base_reg = pipeline->base.user_data_0[stage]; + base_reg = last_vgt_shader->info.user_data_0; radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, provoking_vtx); } @@ -2179,7 +2179,6 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer) const struct radv_userdata_info *loc = radv_get_user_sgpr(last_vgt_shader, AC_UD_NUM_VERTS_PER_PRIM); const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; - const unsigned stage = last_vgt_shader->info.stage; uint32_t base_reg; assert(!cmd_buffer->state.mesh_shading); @@ -2195,7 +2194,7 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer) if (loc->sgpr_idx == -1) return; - base_reg = pipeline->base.user_data_0[stage]; + base_reg = last_vgt_shader->info.user_data_0; radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, si_conv_prim_to_gs_out(d->vk.ia.primitive_topology, pipeline->is_ngg) + 1); } @@ -2420,7 +2419,6 @@ static void radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer) { const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device; - const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; const struct radv_shader *tcs = cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL]; const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; unsigned ls_hs_config, base_reg; @@ -2459,7 +2457,7 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer) return; assert(offchip->num_sgprs == 1); - base_reg = pipeline->base.user_data_0[MESA_SHADER_TESS_CTRL]; + base_reg = cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL]->info.user_data_0; radeon_set_sh_reg(cmd_buffer->cs, base_reg + offchip->sgpr_idx * 4, (cmd_buffer->state.tess_num_patches << 6) | d->vk.ts.patch_control_points); @@ -2467,7 +2465,8 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer) radv_get_shader(cmd_buffer->state.shaders, MESA_SHADER_TESS_EVAL), AC_UD_TES_NUM_PATCHES); assert(num_patches->sgpr_idx != -1 && num_patches->num_sgprs == 1); - base_reg = pipeline->base.user_data_0[MESA_SHADER_TESS_EVAL]; + const struct radv_shader *tes = radv_get_shader(cmd_buffer->state.shaders, MESA_SHADER_TESS_EVAL); + base_reg = tes->info.user_data_0; radeon_set_sh_reg(cmd_buffer->cs, base_reg + num_patches->sgpr_idx * 4, cmd_buffer->state.tess_num_patches); } @@ -2574,7 +2573,7 @@ radv_emit_rasterization_samples(struct radv_cmd_buffer *cmd_buffer) const struct radv_userdata_info *loc = radv_get_user_sgpr(cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT], AC_UD_PS_NUM_SAMPLES); if (loc->sgpr_idx != -1) { - uint32_t base_reg = pipeline->base.user_data_0[MESA_SHADER_FRAGMENT]; + uint32_t base_reg = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]->info.user_data_0; radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, rasterization_samples); } } @@ -3893,7 +3892,7 @@ emit_prolog_inputs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader const struct radv_userdata_info *loc = &vs_shader->info.user_sgprs_locs.shader_data[AC_UD_VS_PROLOG_INPUTS]; - uint32_t base_reg = cmd_buffer->state.graphics_pipeline->base.user_data_0[MESA_SHADER_VERTEX]; + uint32_t base_reg = vs_shader->info.user_data_0; assert(loc->sgpr_idx != -1); assert(loc->num_sgprs == 2); radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, @@ -4485,22 +4484,23 @@ radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer, if (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS) { for (unsigned s = MESA_SHADER_VERTEX; s <= MESA_SHADER_FRAGMENT; s++) if (radv_cmdbuf_has_stage(cmd_buffer, s)) - radv_emit_userdata_address(device, cs, cmd_buffer->state.shaders[s], pipeline->user_data_0[s], + radv_emit_userdata_address(device, cs, cmd_buffer->state.shaders[s], + cmd_buffer->state.shaders[s]->info.user_data_0, AC_UD_INDIRECT_DESCRIPTOR_SETS, va); if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_MESH)) radv_emit_userdata_address(device, cs, cmd_buffer->state.shaders[MESA_SHADER_MESH], - pipeline->user_data_0[MESA_SHADER_MESH], + cmd_buffer->state.shaders[MESA_SHADER_MESH]->info.user_data_0, AC_UD_INDIRECT_DESCRIPTOR_SETS, va); if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TASK)) radv_emit_userdata_address(device, cmd_buffer->ace_internal.cs, cmd_buffer->state.shaders[MESA_SHADER_TASK], - pipeline->user_data_0[MESA_SHADER_TASK], + cmd_buffer->state.shaders[MESA_SHADER_TASK]->info.user_data_0, AC_UD_INDIRECT_DESCRIPTOR_SETS, va); } else { radv_emit_userdata_address(device, cs, cmd_buffer->state.shaders[MESA_SHADER_COMPUTE], - pipeline->user_data_0[MESA_SHADER_COMPUTE], + cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]->info.user_data_0, AC_UD_INDIRECT_DESCRIPTOR_SETS, va); } } @@ -4528,7 +4528,8 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags st if (stages & VK_SHADER_STAGE_COMPUTE_BIT) { radv_emit_descriptor_pointers(device, cs, cmd_buffer->state.shaders[MESA_SHADER_COMPUTE], - pipeline->user_data_0[MESA_SHADER_COMPUTE], descriptors_state); + cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]->info.user_data_0, + descriptors_state); } else { radv_foreach_stage(stage, stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) { @@ -4536,13 +4537,14 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags st continue; radv_emit_descriptor_pointers(device, cs, cmd_buffer->state.shaders[stage], - pipeline->user_data_0[stage], descriptors_state); + cmd_buffer->state.shaders[stage]->info.user_data_0, + descriptors_state); } if (stages & VK_SHADER_STAGE_TASK_BIT_EXT) { radv_emit_descriptor_pointers(device, cmd_buffer->ace_internal.cs, cmd_buffer->state.shaders[MESA_SHADER_TASK], - pipeline->user_data_0[MESA_SHADER_TASK], + cmd_buffer->state.shaders[MESA_SHADER_TASK]->info.user_data_0, descriptors_state); } } @@ -4625,7 +4627,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag if (internal_stages & VK_SHADER_STAGE_COMPUTE_BIT) { radv_emit_all_inline_push_consts(device, cs, cmd_buffer->state.shaders[MESA_SHADER_COMPUTE], - pipeline->user_data_0[MESA_SHADER_COMPUTE], + cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]->info.user_data_0, (uint32_t *)cmd_buffer->push_constants, &need_push_constants); } else { @@ -4635,7 +4637,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag if (!shader) continue; - radv_emit_all_inline_push_consts(device, cs, shader, pipeline->user_data_0[stage], + radv_emit_all_inline_push_consts(device, cs, shader, shader->info.user_data_0, (uint32_t *)cmd_buffer->push_constants, &need_push_constants); } @@ -4643,7 +4645,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag if (internal_stages & VK_SHADER_STAGE_TASK_BIT_EXT) { radv_emit_all_inline_push_consts(device, cmd_buffer->ace_internal.cs, cmd_buffer->state.shaders[MESA_SHADER_TASK], - pipeline->user_data_0[MESA_SHADER_TASK], + cmd_buffer->state.shaders[MESA_SHADER_TASK]->info.user_data_0, (uint32_t *)cmd_buffer->push_constants, &need_push_constants); } @@ -4667,7 +4669,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag if (internal_stages & VK_SHADER_STAGE_COMPUTE_BIT) { radv_emit_userdata_address(device, cs, cmd_buffer->state.shaders[MESA_SHADER_COMPUTE], - pipeline->user_data_0[MESA_SHADER_COMPUTE], + cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]->info.user_data_0, AC_UD_PUSH_CONSTANTS, va); } else { prev_shader = NULL; @@ -4677,7 +4679,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag /* Avoid redundantly emitting the address for merged stages. */ if (shader && shader != prev_shader) { - radv_emit_userdata_address(device, cs, shader, pipeline->user_data_0[stage], + radv_emit_userdata_address(device, cs, shader, shader->info.user_data_0, AC_UD_PUSH_CONSTANTS, va); prev_shader = shader; @@ -4687,7 +4689,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag if (internal_stages & VK_SHADER_STAGE_TASK_BIT_EXT) { radv_emit_userdata_address(device, cmd_buffer->ace_internal.cs, cmd_buffer->state.shaders[MESA_SHADER_TASK], - pipeline->user_data_0[MESA_SHADER_TASK], + cmd_buffer->state.shaders[MESA_SHADER_TASK]->info.user_data_0, AC_UD_PUSH_CONSTANTS, va); } } @@ -4878,6 +4880,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer) assert(!cmd_buffer->state.mesh_shading); struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; + struct radv_shader *vs = radv_get_shader(cmd_buffer->state.shaders, MESA_SHADER_VERTEX); unsigned vb_offset; void *vb_ptr; uint64_t va; @@ -4892,9 +4895,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer) va = radv_buffer_get_va(cmd_buffer->upload.upload_bo); va += vb_offset; - radv_emit_userdata_address(cmd_buffer->device, cmd_buffer->cs, - radv_get_shader(cmd_buffer->state.shaders, MESA_SHADER_VERTEX), - pipeline->base.user_data_0[MESA_SHADER_VERTEX], + radv_emit_userdata_address(cmd_buffer->device, cmd_buffer->cs, vs, vs->info.user_data_0, AC_UD_VS_VERTEX_BUFFERS, va); cmd_buffer->state.vb_va = va; @@ -4909,9 +4910,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer) static void radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va) { - struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; const struct radv_shader *last_vgt_shader = cmd_buffer->state.last_vgt_shader; - const unsigned stage = last_vgt_shader->info.stage; const struct radv_userdata_info *loc = radv_get_user_sgpr(last_vgt_shader, AC_UD_STREAMOUT_BUFFERS); uint32_t base_reg; @@ -4919,7 +4918,7 @@ radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va) if (loc->sgpr_idx == -1) return; - base_reg = pipeline->base.user_data_0[stage]; + base_reg = last_vgt_shader->info.user_data_0; radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, va, false); @@ -5010,7 +5009,6 @@ radv_flush_ngg_query_state(struct radv_cmd_buffer *cmd_buffer) { struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; const struct radv_shader *last_vgt_shader = cmd_buffer->state.last_vgt_shader; - const unsigned stage = last_vgt_shader->info.stage; const struct radv_userdata_info *loc = radv_get_user_sgpr(last_vgt_shader, AC_UD_NGG_QUERY_STATE); enum radv_ngg_query_state ngg_query_state = radv_ngg_query_none; @@ -5037,7 +5035,7 @@ radv_flush_ngg_query_state(struct radv_cmd_buffer *cmd_buffer) ngg_query_state |= radv_ngg_query_prim_xfb | radv_ngg_query_prim_gen; } - base_reg = pipeline->base.user_data_0[stage]; + base_reg = last_vgt_shader->info.user_data_0; assert(loc->sgpr_idx != -1); radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, ngg_query_state); @@ -5064,7 +5062,7 @@ radv_flush_force_vrs_state(struct radv_cmd_buffer *cmd_buffer) const struct radv_shader *last_vgt_shader = cmd_buffer->state.last_vgt_shader; loc = radv_get_user_sgpr(last_vgt_shader, AC_UD_FORCE_VRS_RATES); - base_reg = pipeline->base.user_data_0[last_vgt_shader->info.stage]; + base_reg = last_vgt_shader->info.user_data_0; } assert(loc->sgpr_idx != -1); @@ -7723,12 +7721,12 @@ radv_emit_view_index_per_stage(struct radeon_cmdbuf *cs, const struct radv_shade static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index) { - struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; struct radeon_cmdbuf *cs = cmd_buffer->cs; radv_foreach_stage(stage, cmd_buffer->state.active_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) { - radv_emit_view_index_per_stage(cs, radv_get_shader(cmd_buffer->state.shaders, stage), - pipeline->base.user_data_0[stage], index); + const struct radv_shader *shader = radv_get_shader(cmd_buffer->state.shaders, stage); + + radv_emit_view_index_per_stage(cs, shader, shader->info.user_data_0, index); } if (cmd_buffer->state.gs_copy_shader) { @@ -7739,7 +7737,8 @@ radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index) if (cmd_buffer->state.active_stages & VK_SHADER_STAGE_TASK_BIT_EXT) { radv_emit_view_index_per_stage(cmd_buffer->ace_internal.cs, cmd_buffer->state.shaders[MESA_SHADER_TASK], - pipeline->base.user_data_0[MESA_SHADER_TASK], index); + cmd_buffer->state.shaders[MESA_SHADER_TASK]->info.user_data_0, + index); } } @@ -8714,10 +8713,8 @@ radv_get_ngg_culling_settings(struct radv_cmd_buffer *cmd_buffer, bool vp_y_inve static void radv_emit_ngg_culling_state(struct radv_cmd_buffer *cmd_buffer) { - const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; const struct radv_shader *last_vgt_shader = cmd_buffer->state.last_vgt_shader; - const unsigned stage = last_vgt_shader->info.stage; - const uint32_t base_reg = pipeline->base.user_data_0[stage]; + const uint32_t base_reg = last_vgt_shader->info.user_data_0; /* Get viewport transform. */ float vp_scale[2], vp_translate[2]; @@ -10035,11 +10032,11 @@ radv_trace_rays(struct radv_cmd_buffer *cmd_buffer, const VkTraceRaysIndirectCom uint64_t indirect_va, enum radv_rt_mode mode) { struct radv_compute_pipeline *pipeline = &cmd_buffer->state.rt_pipeline->base; - uint32_t base_reg = pipeline->base.user_data_0[MESA_SHADER_COMPUTE]; + const struct radv_shader *compute_shader = cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]; + uint32_t base_reg = compute_shader->info.user_data_0; /* Reserve scratch for stacks manually since it is not handled by the compute path. */ uint32_t scratch_bytes_per_wave = pipeline->base.scratch_bytes_per_wave; - const struct radv_shader *compute_shader = cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]; uint32_t wave_size = compute_shader->info.wave_size; /* The hardware register is specified as a multiple of 256 DWORDS. */ diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index 7780cb6..8cb4391 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -1155,7 +1155,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *vertex_shader = radv_get_shader(graphics_pipeline->base.shaders, MESA_SHADER_VERTEX); uint16_t vbo_sgpr = ((radv_get_user_sgpr(vertex_shader, AC_UD_VS_VERTEX_BUFFERS)->sgpr_idx * 4 + - graphics_pipeline->base.user_data_0[MESA_SHADER_VERTEX]) - + vertex_shader->info.user_data_0) - SI_SH_REG_OFFSET) >> 2; struct radv_dgc_params params = { @@ -1212,7 +1212,8 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, if (!graphics_pipeline->base.shaders[i]) continue; - struct radv_userdata_locations *locs = &graphics_pipeline->base.shaders[i]->info.user_sgprs_locs; + const struct radv_shader *shader = graphics_pipeline->base.shaders[i]; + const struct radv_userdata_locations *locs = &shader->info.user_sgprs_locs; if (locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx >= 0) params.const_copy = 1; @@ -1223,13 +1224,13 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, if (locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx >= 0) { upload_sgpr = - (graphics_pipeline->base.user_data_0[i] + 4 * locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx - + (shader->info.user_data_0 + 4 * locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx - SI_SH_REG_OFFSET) >> 2; } if (locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx >= 0) { - inline_sgpr = (graphics_pipeline->base.user_data_0[i] + + inline_sgpr = (shader->info.user_data_0 + 4 * locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx - SI_SH_REG_OFFSET) >> 2; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 7715818..fbb8698 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3579,66 +3579,6 @@ done: return result; } -static uint32_t -radv_pipeline_stage_to_user_data_0(struct radv_graphics_pipeline *pipeline, gl_shader_stage stage, - enum amd_gfx_level gfx_level) -{ - bool has_gs = radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY); - bool has_tess = radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL); - bool has_ngg = radv_pipeline_has_ngg(pipeline); - - switch (stage) { - case MESA_SHADER_FRAGMENT: - return R_00B030_SPI_SHADER_USER_DATA_PS_0; - case MESA_SHADER_VERTEX: - if (has_tess) { - if (gfx_level >= GFX10) { - return R_00B430_SPI_SHADER_USER_DATA_HS_0; - } else if (gfx_level == GFX9) { - return R_00B430_SPI_SHADER_USER_DATA_LS_0; - } else { - return R_00B530_SPI_SHADER_USER_DATA_LS_0; - } - } - - if (has_gs) { - if (gfx_level >= GFX10) { - return R_00B230_SPI_SHADER_USER_DATA_GS_0; - } else { - return R_00B330_SPI_SHADER_USER_DATA_ES_0; - } - } - - if (has_ngg) - return R_00B230_SPI_SHADER_USER_DATA_GS_0; - - return R_00B130_SPI_SHADER_USER_DATA_VS_0; - case MESA_SHADER_GEOMETRY: - return gfx_level == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 - : R_00B230_SPI_SHADER_USER_DATA_GS_0; - case MESA_SHADER_COMPUTE: - case MESA_SHADER_TASK: - return R_00B900_COMPUTE_USER_DATA_0; - case MESA_SHADER_TESS_CTRL: - return gfx_level == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 - : R_00B430_SPI_SHADER_USER_DATA_HS_0; - case MESA_SHADER_TESS_EVAL: - if (has_gs) { - return gfx_level >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 - : R_00B330_SPI_SHADER_USER_DATA_ES_0; - } else if (has_ngg) { - return R_00B230_SPI_SHADER_USER_DATA_GS_0; - } else { - return R_00B130_SPI_SHADER_USER_DATA_VS_0; - } - case MESA_SHADER_MESH: - assert(has_ngg); - return R_00B230_SPI_SHADER_USER_DATA_GS_0; - default: - unreachable("unknown shader"); - } -} - static void radv_pipeline_emit_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, const struct radv_depth_stencil_state *ds_state) @@ -4712,10 +4652,6 @@ radv_pipeline_init_shader_stages_state(const struct radv_device *device, for (unsigned i = 0; i < MESA_VULKAN_SHADER_STAGES; i++) { bool shader_exists = !!pipeline->base.shaders[i]; if (shader_exists || i < MESA_SHADER_COMPUTE) { - /* We need this info for some stages even when the shader doesn't exist. */ - pipeline->base.user_data_0[i] = radv_pipeline_stage_to_user_data_0( - pipeline, i, device->physical_device->rad_info.gfx_level); - if (shader_exists) pipeline->base.need_indirect_descriptor_sets |= radv_shader_need_indirect_descriptor_sets(pipeline->base.shaders[i]); @@ -4725,11 +4661,12 @@ radv_pipeline_init_shader_stages_state(const struct radv_device *device, gl_shader_stage first_stage = radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH) ? MESA_SHADER_MESH : MESA_SHADER_VERTEX; + const struct radv_shader *shader = radv_get_shader(pipeline->base.shaders, first_stage); const struct radv_userdata_info *loc = - radv_get_user_sgpr(radv_get_shader(pipeline->base.shaders, first_stage), - AC_UD_VS_BASE_VERTEX_START_INSTANCE); + radv_get_user_sgpr(shader, AC_UD_VS_BASE_VERTEX_START_INSTANCE); + if (loc->sgpr_idx != -1) { - pipeline->vtx_base_sgpr = pipeline->base.user_data_0[first_stage]; + pipeline->vtx_base_sgpr = shader->info.user_data_0; pipeline->vtx_base_sgpr += loc->sgpr_idx * 4; pipeline->vtx_emit_num = loc->num_sgprs; pipeline->uses_drawid = @@ -5274,7 +5211,6 @@ radv_compute_pipeline_init(const struct radv_device *device, struct radv_compute_pipeline *pipeline, const struct radv_pipeline_layout *layout) { - pipeline->base.user_data_0[MESA_SHADER_COMPUTE] = R_00B900_COMPUTE_USER_DATA_0; pipeline->base.need_indirect_descriptor_sets |= radv_shader_need_indirect_descriptor_sets(pipeline->base.shaders[MESA_SHADER_COMPUTE]); radv_pipeline_init_scratch(device, &pipeline->base); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 3d4430d..5447fb5 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -266,6 +266,7 @@ struct radv_shader_info { bool force_vrs_per_vertex; gl_shader_stage stage; gl_shader_stage next_stage; + uint32_t user_data_0; struct { uint8_t input_usage_mask[RADV_VERT_ATTRIB_MAX]; diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index dcd3daf..9d645a0 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -725,6 +725,58 @@ gather_shader_info_task(const nir_shader *nir, struct radv_shader_info *info) info->cs.uses_local_invocation_idx = true; } +static uint32_t +radv_get_user_data_0(const struct radv_device *device, struct radv_shader_info *info) +{ + const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; + + switch (info->stage) { + case MESA_SHADER_VERTEX: + case MESA_SHADER_TESS_EVAL: + case MESA_SHADER_MESH: + if (info->next_stage == MESA_SHADER_TESS_CTRL) { + assert(info->stage == MESA_SHADER_VERTEX); + + if (gfx_level >= GFX10) { + return R_00B430_SPI_SHADER_USER_DATA_HS_0; + } else if (gfx_level == GFX9) { + return R_00B430_SPI_SHADER_USER_DATA_LS_0; + } else { + return R_00B530_SPI_SHADER_USER_DATA_LS_0; + } + } + + if (info->next_stage == MESA_SHADER_GEOMETRY) { + assert(info->stage == MESA_SHADER_VERTEX || info->stage == MESA_SHADER_TESS_EVAL); + + if (gfx_level >= GFX10) { + return R_00B230_SPI_SHADER_USER_DATA_GS_0; + } else { + return R_00B330_SPI_SHADER_USER_DATA_ES_0; + } + } + + if (info->is_ngg) + return R_00B230_SPI_SHADER_USER_DATA_GS_0; + + assert(info->stage != MESA_SHADER_MESH); + return R_00B130_SPI_SHADER_USER_DATA_VS_0; + case MESA_SHADER_TESS_CTRL: + return gfx_level == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 + : R_00B430_SPI_SHADER_USER_DATA_HS_0; + case MESA_SHADER_GEOMETRY: + return gfx_level == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 + : R_00B230_SPI_SHADER_USER_DATA_GS_0; + case MESA_SHADER_FRAGMENT: + return R_00B030_SPI_SHADER_USER_DATA_PS_0; + case MESA_SHADER_COMPUTE: + case MESA_SHADER_TASK: + return R_00B900_COMPUTE_USER_DATA_0; + default: + unreachable("invalid shader stage"); + } +} + void radv_nir_shader_info_init(struct radv_shader_info *info) { @@ -854,6 +906,8 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n info->cs.block_size[i] = nir->info.workgroup_size[i]; } + info->user_data_0 = radv_get_user_data_0(device, info); + switch (nir->info.stage) { case MESA_SHADER_COMPUTE: gather_shader_info_cs(device, nir, pipeline_key, info);