From: Marek Szulc Date: Fri, 19 Aug 2022 10:29:48 +0000 (+0200) Subject: riscv: fix riscv64 unrecognized opcode build error X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0e36f76896c16cab69416a9a28a0080f122fe413;p=platform%2Fkernel%2Flinux-starfive.git riscv: fix riscv64 unrecognized opcode build error Considering older gcc version, "imafd" has to be changed to "g", in order for asm to handle "zicsr" and "zifencei" extensions. Support for the mentioned extensions has been added in GCC 11.1, hence this commit may be removed after GCC update. The lack of this causes following errors: Error: unrecognized opcode `csrr a5,0xc01' Error: unrecognized opcode `csrr a2,0xc01' Change-Id: I0768a7b1255c828c4fc319f74f2783bc7e1581bf Signed-off-by: Marek Szulc Signed-off-by: Łukasz Stelmach --- diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0d13b59..9551509 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -51,6 +51,7 @@ endif riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd +riscv-march-y := $(subst imafd,g,$(riscv-march-y)) riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c # Newer binutils versions default to ISA spec version 20191213 which moves some