From: Chris Wilson Date: Sat, 9 Apr 2016 09:57:56 +0000 (+0100) Subject: drm/i915: Use simplest form for flushing the single cacheline in the HWS X-Git-Tag: v5.15~13124^2~45^2~351 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0d317ce99e226a338fe0962e711795c6a8ed2cb2;p=platform%2Fkernel%2Flinux-starfive.git drm/i915: Use simplest form for flushing the single cacheline in the HWS Rather than call a function to compute the matching cachelines and clflush them, just call the clflush *instruction* directly. We also know that we can use the unpatched plain clflush rather than the clflushopt alternative. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Imre Deak Reviewed-by: Mika Kuoppala Link: http://patchwork.freedesktop.org/patch/msgid/1460195877-20520-4-git-send-email-chris@chris-wilson.co.uk --- diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 29c54cc..9d7b7bf9 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -385,8 +385,9 @@ intel_ring_sync_index(struct intel_engine_cs *engine, static inline void intel_flush_status_page(struct intel_engine_cs *engine, int reg) { - drm_clflush_virt_range(&engine->status_page.page_addr[reg], - sizeof(uint32_t)); + mb(); + clflush(&engine->status_page.page_addr[reg]); + mb(); } static inline u32