From: Nick Clifton <nickc@redhat.com>
Date: Thu, 11 Jan 2001 21:20:20 +0000 (+0000)
Subject: Updated ARC assembler from arccores.com
X-Git-Tag: newlib-1_9_0~116
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0d2bcfafbfc1ede123ec9d61813745d775c5251c;p=external%2Fbinutils.git

Updated ARC assembler from arccores.com
---

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 613de19..7988d77 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,16 @@
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* bfd-in2.h (bfd_architecture): Add bfd_mach_arc_5,
+	bfd_mach_arc_6, bfd_mach_arc_7, bfd_mach_arc_8 for ARC variants.
+	* cpu-arc.c (arch_info_struct): Add entries for variants.
+	(bfd_arc_arch) Set default to bfd_mach_arc_5.
+	(arc_get_mach) Don't assume machine names prefixed arc- before
+	testing.
+	* elf32-arc.c (arc_elf_object_p): Set machine number based on new
+	selections.
+	(arc_elf_final_write_processing) Likewise.
+	(ELF_MACHINE_CODE) Use EM_ARC.
+
 2001-01-10  Nick Clifton  <nickc@redhat.com>
 
 	* coff-arm.c (LOCAL_LABEL_PREFIX): Change definition to "".
diff --git a/bfd/archures.c b/bfd/archures.c
index 5bc744a..84b7744 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -222,8 +222,11 @@ DESCRIPTION
 .#define bfd_mach_v850          0
 .#define bfd_mach_v850e 	'E'
 .#define bfd_mach_v850ea	'A'
-.  bfd_arch_arc,       {* Argonaut RISC Core *}
-.#define bfd_mach_arc_base 0
+.  bfd_arch_arc,       {* ARC Cores *}
+.#define bfd_mach_arc_5         0
+.#define bfd_mach_arc_6         1
+.#define bfd_mach_arc_7         2
+.#define bfd_mach_arc_8         3
 .  bfd_arch_m32r,      {* Mitsubishi M32R/D *}
 .#define bfd_mach_m32r		0 {* backwards compatibility *}
 .#define bfd_mach_m32rx		'x'
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 5fe2b47..37d1914 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -813,13 +813,13 @@ bfd_make_readable PARAMS ((bfd *abfd));
 /* Byte swapping macros for user section data.  */
 
 #define bfd_put_8(abfd, val, ptr) \
-                ((void) (*((unsigned char *)(ptr)) = (unsigned char)(val)))
+                ((void) (*((unsigned char *) (ptr)) = (unsigned char) (val)))
 #define bfd_put_signed_8 \
                bfd_put_8
 #define bfd_get_8(abfd, ptr) \
-                (*(unsigned char *)(ptr))
+                (*(unsigned char *) (ptr))
 #define bfd_get_signed_8(abfd, ptr) \
-               ((*(unsigned char *)(ptr) ^ 0x80) - 0x80)
+               ((*(unsigned char *) (ptr) ^ 0x80) - 0x80)
 
 #define bfd_put_16(abfd, val, ptr) \
                 BFD_SEND(abfd, bfd_putx16, ((val),(ptr)))
@@ -1495,8 +1495,11 @@ enum bfd_architecture
 #define bfd_mach_v850          0
 #define bfd_mach_v850e         'E'
 #define bfd_mach_v850ea        'A'
-  bfd_arch_arc,       /* Argonaut RISC Core */
-#define bfd_mach_arc_base 0
+  bfd_arch_arc,       /* ARC Cores */
+#define bfd_mach_arc_5         0
+#define bfd_mach_arc_6         1
+#define bfd_mach_arc_7         2
+#define bfd_mach_arc_8         3
   bfd_arch_m32r,      /* Mitsubishi M32R/D */
 #define bfd_mach_m32r          0 /* backwards compatibility */
 #define bfd_mach_m32rx         'x'
@@ -2218,7 +2221,7 @@ be zero and is not stored in the instruction. */
   BFD_RELOC_THUMB_PCREL_BRANCH12,
   BFD_RELOC_THUMB_PCREL_BRANCH23,
 
-/* Argonaut RISC Core (ARC) relocs.
+/* ARC Cores relocs.
 ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
 not stored in the instruction.  The high 20 bits are installed in bits 26
 through 7 of the instruction. */
@@ -2407,13 +2410,13 @@ significant 9 bits of the opcode. */
 /* This is an extended address 23-bit reloc for the tms320c54x. */
   BFD_RELOC_TIC54X_23,
 
-/* This is a 16-bit reloc for the tms320c54x, where the least 
-significant 16 bits of a 23-bit extended address are placed into 
+/* This is a 16-bit reloc for the tms320c54x, where the least
+significant 16 bits of a 23-bit extended address are placed into
 the opcode. */
   BFD_RELOC_TIC54X_16_OF_23,
 
 /* This is a reloc for the tms320c54x, where the most
-significant 7 bits of a 23-bit extended address are placed into 
+significant 7 bits of a 23-bit extended address are placed into
 the opcode. */
   BFD_RELOC_TIC54X_MS7_OF_23,
 
diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c
index bce59d4..dbd7fb1 100644
--- a/bfd/cpu-arc.c
+++ b/bfd/cpu-arc.c
@@ -24,31 +24,31 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #define ARC(mach, print_name, default_p, next) \
 {					\
-    32,	/* 32 bits in a word */		\
-    32,	/* 32 bits in an address */	\
-    8,	/* 8 bits in a byte */		\
+    32,	/* 32 bits in a word  */	\
+    32,	/* 32 bits in an address  */	\
+    8,	/* 8 bits in a byte  */		\
     bfd_arch_arc,			\
     mach,				\
     "arc",				\
     print_name,				\
-    4, /* section alignment power */	\
+    4, /* section alignment power  */	\
     default_p,				\
     bfd_default_compatible, 		\
     bfd_default_scan,			\
     next,				\
   }
 
-#if 0 /* ??? Not currently needed, but keep in for future reference.  */
 static const bfd_arch_info_type arch_info_struct[] =
 {
-  ARC (bfd_mach_arc_foo, "arc-foo", false, &arch_info_struct[1]),
-  ARC (bfd_mach_arc_bar, "arc-bar", false, 0),
+  ARC ( bfd_mach_arc_5, "arc5", false, &arch_info_struct[1] ),
+  ARC ( bfd_mach_arc_6, "arc6", false, &arch_info_struct[2] ),
+  ARC ( bfd_mach_arc_7, "arc7", false, &arch_info_struct[3] ),
+  ARC ( bfd_mach_arc_8, "arc8", false, NULL ),
 };
-#endif
 
 const bfd_arch_info_type bfd_arc_arch =
-  ARC (bfd_mach_arc_base, "arc-base", true, 0 /*&arch_info_struct[0]*/);
-
+  ARC ( bfd_mach_arc_5, "arc", true, &arch_info_struct[0] );
+
 /* Utility routines.  */
 
 /* Given cpu type NAME, return its bfd_mach_arc_xxx value.
@@ -61,10 +61,7 @@ arc_get_mach (name)
   const bfd_arch_info_type *p;
 
   for (p = &bfd_arc_arch; p != NULL; p = p->next)
-    {
-      /* +4: skip over "arc-" */
-      if (strcmp (name, p->printable_name + 4) == 0)
-	return p->mach;
-    }
+    if (strcmp (name, p->printable_name) == 0)
+      return p->mach;
   return -1;
 }
diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index 318dc70..254b346 100644
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -1,22 +1,22 @@
 /* ARC-specific support for 32-bit ELF
-   Copyright (C) 1994, 1995, 1997, 1999 Free Software Foundation, Inc.
+   Copyright (C) 1994, 1995, 1997, 1999, 2000 Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
 
-This file is part of BFD, the Binary File Descriptor library.
+   This file is part of BFD, the Binary File Descriptor library.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include "bfd.h"
 #include "sysdep.h"
@@ -25,77 +25,80 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #include "elf/arc.h"
 
 static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
- PARAMS ((bfd *abfd, bfd_reloc_code_real_type code));
+  PARAMS ((bfd *abfd, bfd_reloc_code_real_type code));
 static void arc_info_to_howto_rel
   PARAMS ((bfd *, arelent *, Elf32_Internal_Rel *));
-static boolean arc_elf_object_p PARAMS ((bfd *));
-static void arc_elf_final_write_processing PARAMS ((bfd *, boolean));
+static boolean arc_elf_object_p
+  PARAMS ((bfd *));
+static void arc_elf_final_write_processing
+  PARAMS ((bfd *, boolean));
 
 /* Try to minimize the amount of space occupied by relocation tables
    on the ROM (not that the ROM won't be swamped by other ELF overhead).  */
+
 #define USE_REL
 
 static reloc_howto_type elf_arc_howto_table[] =
 {
   /* This reloc does nothing.  */
-  HOWTO (R_ARC_NONE,		/* type */
-	 0,			/* rightshift */
-	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-	 32,			/* bitsize */
-	 false,			/* pc_relative */
-	 0,			/* bitpos */
-	 complain_overflow_bitfield, /* complain_on_overflow */
-	 bfd_elf_generic_reloc,	/* special_function */
-	 "R_ARC_NONE",		/* name */
-	 false,			/* partial_inplace */
-	 0,			/* src_mask */
-	 0,			/* dst_mask */
-	 false),		/* pcrel_offset */
+  HOWTO (R_ARC_NONE,		/* type  */
+	 0,			/* rightshift  */
+	 2,			/* size (0 = byte, 1 = short, 2 = long)  */
+	 32,			/* bitsize  */
+	 false,			/* pc_relative  */
+	 0,			/* bitpos  */
+	 complain_overflow_bitfield, /* complain_on_overflow  */
+	 bfd_elf_generic_reloc,	/* special_function  */
+	 "R_ARC_NONE",		/* name  */
+	 false,			/* partial_inplace  */
+	 0,			/* src_mask  */
+	 0,			/* dst_mask  */
+	 false),		/* pcrel_offset  */
 
   /* A standard 32 bit relocation.  */
-  HOWTO (R_ARC_32,		/* type */
-	 0,	                /* rightshift */
-	 2,	                /* size (0 = byte, 1 = short, 2 = long) */
-	 32,	                /* bitsize */
-	 false,	                /* pc_relative */
-	 0,	                /* bitpos */
-	 complain_overflow_bitfield, /* complain_on_overflow */
-	 bfd_elf_generic_reloc, /* special_function */
-	 "R_ARC_32",		/* name */
-	 false,	                /* partial_inplace */
-	 0xffffffff,	        /* src_mask */
-	 0xffffffff,   		/* dst_mask */
-	 false),                /* pcrel_offset */
+  HOWTO (R_ARC_32,		/* type  */
+	 0,	                /* rightshift  */
+	 2,	                /* size (0 = byte, 1 = short, 2 = long)  */
+	 32,	                /* bitsize  */
+	 false,	                /* pc_relative  */
+	 0,	                /* bitpos  */
+	 complain_overflow_bitfield, /* complain_on_overflow  */
+	 bfd_elf_generic_reloc, /* special_function  */
+	 "R_ARC_32",		/* name  */
+	 false,	                /* partial_inplace  */
+	 0xffffffff,	        /* src_mask  */
+	 0xffffffff,   		/* dst_mask  */
+	 false),                /* pcrel_offset  */
 
   /* A 26 bit absolute branch, right shifted by 2.  */
-  HOWTO (R_ARC_B26,		/* type */
-	 2,			/* rightshift */
-	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-	 26,			/* bitsize */
-	 false,			/* pc_relative */
-	 0,			/* bitpos */
-	 complain_overflow_bitfield, /* complain_on_overflow */
-	 bfd_elf_generic_reloc,	/* special_function */
-	 "R_ARC_B26",		/* name */
-	 false,			/* partial_inplace */
-	 0x00ffffff,		/* src_mask */
-	 0x00ffffff,		/* dst_mask */
-	 false),		/* pcrel_offset */
+  HOWTO (R_ARC_B26,		/* type  */
+	 2,			/* rightshift  */
+	 2,			/* size (0 = byte, 1 = short, 2 = long)  */
+	 26,			/* bitsize  */
+	 false,			/* pc_relative  */
+	 0,			/* bitpos  */
+	 complain_overflow_bitfield, /* complain_on_overflow  */
+	 bfd_elf_generic_reloc,	/* special_function  */
+	 "R_ARC_B26",		/* name  */
+	 false,			/* partial_inplace  */
+	 0x00ffffff,		/* src_mask  */
+	 0x00ffffff,		/* dst_mask  */
+	 false),		/* pcrel_offset  */
 
   /* A relative 22 bit branch; bits 21-2 are stored in bits 26-7.  */
-  HOWTO (R_ARC_B22_PCREL,	/* type */
-	 2,			/* rightshift */
-	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-	 22,			/* bitsize */
-	 true,			/* pc_relative */
-	 7,			/* bitpos */
-	 complain_overflow_signed, /* complain_on_overflow */
-	 bfd_elf_generic_reloc,	/* special_function */
-	 "R_ARC_B22_PCREL",	/* name */
-	 false,			/* partial_inplace */
-	 0x07ffff80,		/* src_mask */
-	 0x07ffff80,		/* dst_mask */
-	 true),			/* pcrel_offset */
+  HOWTO (R_ARC_B22_PCREL,	/* type  */
+	 2,			/* rightshift  */
+	 2,			/* size (0 = byte, 1 = short, 2 = long)  */
+	 22,			/* bitsize  */
+	 true,			/* pc_relative  */
+	 7,			/* bitpos  */
+	 complain_overflow_signed, /* complain_on_overflow  */
+	 bfd_elf_generic_reloc,	/* special_function  */
+	 "R_ARC_B22_PCREL",	/* name  */
+	 false,			/* partial_inplace  */
+	 0x07ffff80,		/* src_mask  */
+	 0x07ffff80,		/* dst_mask  */
+	 true),			/* pcrel_offset  */
 
 };
 
@@ -123,14 +126,11 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, code)
 {
   unsigned int i;
 
-  for (i = 0;
-       i < sizeof (arc_reloc_map) / sizeof (struct arc_reloc_map);
-       i++)
+  for (i = 0; i < sizeof (arc_reloc_map) / sizeof (struct arc_reloc_map); i++)
     {
       if (arc_reloc_map[i].bfd_reloc_val == code)
 	return &elf_arc_howto_table[arc_reloc_map[i].elf_reloc_val];
     }
-
   return NULL;
 }
 
@@ -155,21 +155,30 @@ static boolean
 arc_elf_object_p (abfd)
      bfd *abfd;
 {
-  int mach;
-  unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH;
+  int mach = bfd_mach_arc_5;
 
-  switch (arch)
+  if (elf_elfheader(abfd)->e_machine == EM_ARC)
     {
-    case E_ARC_MACH_BASE:
-      mach = bfd_mach_arc_base;
-      break;
-    default:
-      /* Unknown cpu type.  ??? What to do?  */
-      return false;
+      unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH;
+
+      switch (arch)
+	{
+	default:
+	case E_ARC_MACH_ARC5:
+	  mach = bfd_mach_arc_5;
+	  break;
+	case E_ARC_MACH_ARC6:
+	  mach = bfd_mach_arc_6;
+	  break;
+	case E_ARC_MACH_ARC7:
+	  mach = bfd_mach_arc_7;
+	  break;
+	case E_ARC_MACH_ARC8:
+	  mach = bfd_mach_arc_8;
+	  break;
+	}
     }
-
-  (void) bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach);
-  return true;
+  return bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach);
 }
 
 /* The final processing done just before writing out an ARC ELF object file.
@@ -180,34 +189,40 @@ arc_elf_final_write_processing (abfd, linker)
      bfd *abfd;
      boolean linker ATTRIBUTE_UNUSED;
 {
-  int mach;
   unsigned long val;
 
-  switch (mach = bfd_get_mach (abfd))
+  switch (bfd_get_mach (abfd))
     {
-    case bfd_mach_arc_base:
-      val = E_ARC_MACH_BASE;
-      break;
     default:
-      return;
+    case bfd_mach_arc_5:
+      val = E_ARC_MACH_ARC5;
+      break;
+    case bfd_mach_arc_6:
+      val = E_ARC_MACH_ARC6;
+      break;
+    case bfd_mach_arc_7:
+      val = E_ARC_MACH_ARC7;
+      break;
+    case bfd_mach_arc_8:
+      val = E_ARC_MACH_ARC8;
+      break;
     }
-
+  elf_elfheader (abfd)->e_machine = EM_ARC;
   elf_elfheader (abfd)->e_flags &=~ EF_ARC_MACH;
   elf_elfheader (abfd)->e_flags |= val;
 }
 
-#define TARGET_LITTLE_SYM	bfd_elf32_littlearc_vec
-#define TARGET_LITTLE_NAME	"elf32-littlearc"
-#define TARGET_BIG_SYM		bfd_elf32_bigarc_vec
-#define TARGET_BIG_NAME		"elf32-bigarc"
-#define ELF_ARCH		bfd_arch_arc
-#define ELF_MACHINE_CODE	EM_CYGNUS_ARC
-#define ELF_MAXPAGESIZE		0x1000
-
-#define elf_info_to_howto	0
-#define elf_info_to_howto_rel	arc_info_to_howto_rel
-#define elf_backend_object_p	arc_elf_object_p
-#define elf_backend_final_write_processing \
-				arc_elf_final_write_processing
+#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec
+#define TARGET_LITTLE_NAME "elf32-littlearc"
+#define TARGET_BIG_SYM bfd_elf32_bigarc_vec
+#define TARGET_BIG_NAME	"elf32-bigarc"
+#define ELF_ARCH bfd_arch_arc
+#define ELF_MACHINE_CODE EM_ARC
+#define ELF_MAXPAGESIZE	0x1000
+
+#define elf_info_to_howto 0
+#define elf_info_to_howto_rel arc_info_to_howto_rel
+#define elf_backend_object_p arc_elf_object_p
+#define elf_backend_final_write_processing arc_elf_final_write_processing
 
 #include "elf32-target.h"
diff --git a/bfd/po/bfd.pot b/bfd/po/bfd.pot
index bf17e1d..e77b05d 100644
--- a/bfd/po/bfd.pot
+++ b/bfd/po/bfd.pot
@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2000-12-21 10:38-0800\n"
+"POT-Creation-Date: 2001-01-11 11:54-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -375,7 +375,7 @@ msgstr ""
 msgid "uncertain calling convention for non-COFF symbol"
 msgstr ""
 
-#: cofflink.c:526 elflink.h:1649
+#: cofflink.c:526 elflink.h:1648
 #, c-format
 msgid "Warning: type of symbol `%s' changed from %d to %d in %s"
 msgstr ""
@@ -1276,7 +1276,7 @@ msgstr ""
 msgid "%s: unsupported relocation type %s"
 msgstr ""
 
-#: elfcode.h:1076
+#: elfcode.h:1084
 #, c-format
 msgid "%s: version count (%ld) does not match symbol count (%ld)"
 msgstr ""
@@ -1286,37 +1286,37 @@ msgstr ""
 msgid "%s: Section %s is already to large to put hole of %ld bytes in"
 msgstr ""
 
-#: elflink.h:1466
+#: elflink.h:1465
 #, c-format
 msgid "%s: %s: invalid version %u (max %d)"
 msgstr ""
 
-#: elflink.h:1507
+#: elflink.h:1506
 #, c-format
 msgid "%s: %s: invalid needed version %d"
 msgstr ""
 
-#: elflink.h:1627
+#: elflink.h:1626
 #, c-format
 msgid "Warning: size of symbol `%s' changed from %lu to %lu in %s"
 msgstr ""
 
-#: elflink.h:1873
+#: elflink.h:1872
 #, c-format
 msgid "%s: warning: unexpected redefinition of `%s'"
 msgstr ""
 
-#: elflink.h:3660
+#: elflink.h:3659
 #, c-format
 msgid "warning: type and size of dynamic symbol `%s' are not defined"
 msgstr ""
 
-#: elflink.h:3932
+#: elflink.h:3931
 #, c-format
 msgid "%s: undefined versioned symbol name %s"
 msgstr ""
 
-#: elflink.h:5181
+#: elflink.h:5180
 #, c-format
 msgid "%s: could not find output section %s for input section %s"
 msgstr ""
@@ -1416,26 +1416,26 @@ msgstr ""
 msgid "%s: address 0x%s out of range for Intex Hex file"
 msgstr ""
 
-#: libbfd.c:484
+#: libbfd.c:471
 #, c-format
 msgid "not mapping: data=%lx mapped=%d\n"
 msgstr ""
 
-#: libbfd.c:487
+#: libbfd.c:474
 msgid "not mapping: env var not set\n"
 msgstr ""
 
-#: libbfd.c:1383
+#: libbfd.c:1370
 #, c-format
 msgid "%s: compiled for a big endian system and target is little endian"
 msgstr ""
 
-#: libbfd.c:1385
+#: libbfd.c:1372
 #, c-format
 msgid "%s: compiled for a little endian system and target is big endian"
 msgstr ""
 
-#: linker.c:2679
+#: linker.c:2678
 #, c-format
 msgid "Attempt to do relocateable link with %s input and %s output"
 msgstr ""
@@ -1451,39 +1451,39 @@ msgid "Unhandled OSF/1 core file section type %d\n"
 msgstr ""
 
 #. XXX code yet to be written.
-#: peicode.h:809
+#: peicode.h:807
 #, c-format
 msgid "%s: Unhandled import type; %x"
 msgstr ""
 
-#: peicode.h:814
+#: peicode.h:812
 #, c-format
 msgid "%s: Unrecognised import type; %x"
 msgstr ""
 
-#: peicode.h:828
+#: peicode.h:826
 #, c-format
 msgid "%s: Unrecognised import name type; %x"
 msgstr ""
 
-#: peicode.h:1185
+#: peicode.h:1183
 #, c-format
 msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive"
 msgstr ""
 
-#: peicode.h:1197
+#: peicode.h:1195
 #, c-format
 msgid ""
 "%s: Recognised but unhandled machine type (0x%x) in Import Library Format "
 "archive"
 msgstr ""
 
-#: peicode.h:1214
+#: peicode.h:1212
 #, c-format
 msgid "%s: size field is zero in Import Library Format header"
 msgstr ""
 
-#: peicode.h:1242
+#: peicode.h:1240
 #, c-format
 msgid "%s: string not null terminated in ILF object file."
 msgstr ""
@@ -1787,7 +1787,7 @@ msgid ""
 "Characteristics 0x%x\n"
 msgstr ""
 
-#: pe-mips.c:657
+#: pe-mips.c:653
 #, c-format
 msgid "%s: `ld -r' not supported with PE MIPS objects\n"
 msgstr ""
@@ -1797,17 +1797,17 @@ msgstr ""
 #. mem = pointer to memory we're fixing up
 #. val = VMA of what we need to refer to
 #.
-#: pe-mips.c:794
+#: pe-mips.c:789
 #, c-format
 msgid "%s: unimplemented %s\n"
 msgstr ""
 
-#: pe-mips.c:820
+#: pe-mips.c:815
 #, c-format
 msgid "%s: jump too far away\n"
 msgstr ""
 
-#: pe-mips.c:847
+#: pe-mips.c:842
 #, c-format
 msgid "%s: bad pair/reflo after refhi\n"
 msgstr ""
@@ -1860,7 +1860,7 @@ msgstr ""
 msgid "Partition[%d] length = 0x%.8lx (%ld)\n"
 msgstr ""
 
-#: som.c:5365
+#: som.c:5355
 msgid "som_sizeof_headers unimplemented"
 msgstr ""
 
@@ -1873,149 +1873,149 @@ msgstr ""
 msgid "Unsupported .stab relocation"
 msgstr ""
 
-#: vms-gsd.c:357
+#: vms-gsd.c:354
 #, c-format
 msgid "bfd_make_section (%s) failed"
 msgstr ""
 
-#: vms-gsd.c:371
+#: vms-gsd.c:368
 #, c-format
 msgid "bfd_set_section_flags (%s, %x) failed"
 msgstr ""
 
-#: vms-gsd.c:407
+#: vms-gsd.c:404
 #, c-format
 msgid "Size mismatch section %s=%lx, %s=%lx"
 msgstr ""
 
-#: vms-gsd.c:702
+#: vms-gsd.c:699
 #, c-format
 msgid "unknown gsd/egsd subtype %d"
 msgstr ""
 
-#: vms-hdr.c:408
+#: vms-hdr.c:403
 msgid "Object module NOT error-free !\n"
 msgstr ""
 
-#: vms-misc.c:545
+#: vms-misc.c:539
 #, c-format
 msgid "Stack overflow (%d) in _bfd_vms_push"
 msgstr ""
 
-#: vms-misc.c:564
+#: vms-misc.c:557
 msgid "Stack underflow in _bfd_vms_pop"
 msgstr ""
 
-#: vms-misc.c:935
+#: vms-misc.c:915
 msgid "_bfd_vms_output_counted called with zero bytes"
 msgstr ""
 
-#: vms-misc.c:940
+#: vms-misc.c:920
 msgid "_bfd_vms_output_counted called with too many bytes"
 msgstr ""
 
-#: vms-misc.c:1073
+#: vms-misc.c:1051
 #, c-format
 msgid "Symbol %s replaced by %s\n"
 msgstr ""
 
-#: vms-misc.c:1137
+#: vms-misc.c:1113
 #, c-format
 msgid "failed to enter %s"
 msgstr ""
 
-#: vms-tir.c:69
+#: vms-tir.c:68
 msgid "No Mem !"
 msgstr ""
 
-#: vms-tir.c:309
+#: vms-tir.c:302
 msgid "Bad section index in ETIR_S_C_STA_PQ"
 msgstr ""
 
-#: vms-tir.c:324
+#: vms-tir.c:317
 #, c-format
 msgid "Unsupported STA cmd %d"
 msgstr ""
 
-#: vms-tir.c:329 vms-tir.c:1287
+#: vms-tir.c:322 vms-tir.c:1274
 #, c-format
 msgid "Reserved STA cmd %d"
 msgstr ""
 
-#: vms-tir.c:436
+#: vms-tir.c:428
 #, c-format
 msgid "ETIR_S_C_STO_GBL: no symbol \"%s\""
 msgstr ""
 
-#: vms-tir.c:457
+#: vms-tir.c:449
 #, c-format
 msgid "ETIR_S_C_STO_CA: no symbol \"%s\""
 msgstr ""
 
-#: vms-tir.c:470
+#: vms-tir.c:462
 msgid "ETIR_S_C_STO_RB/AB: Not supported"
 msgstr ""
 
-#: vms-tir.c:528
+#: vms-tir.c:520
 msgid "ETIR_S_C_STO_LP_PSB: Not supported"
 msgstr ""
 
-#: vms-tir.c:534
+#: vms-tir.c:526
 msgid "ETIR_S_C_STO_HINT_GBL: not implemented"
 msgstr ""
 
-#: vms-tir.c:540
+#: vms-tir.c:532
 msgid "ETIR_S_C_STO_HINT_PS: not implemented"
 msgstr ""
 
-#: vms-tir.c:544 vms-tir.c:1460
+#: vms-tir.c:536 vms-tir.c:1446
 #, c-format
 msgid "Reserved STO cmd %d"
 msgstr ""
 
-#: vms-tir.c:657
+#: vms-tir.c:649
 msgid "ETIR_S_C_OPR_INSV: Not supported"
 msgstr ""
 
-#: vms-tir.c:675
+#: vms-tir.c:667
 msgid "ETIR_S_C_OPR_USH: Not supported"
 msgstr ""
 
-#: vms-tir.c:681
+#: vms-tir.c:673
 msgid "ETIR_S_C_OPR_ROT: Not supported"
 msgstr ""
 
-#: vms-tir.c:700
+#: vms-tir.c:692
 msgid "ETIR_S_C_OPR_REDEF: Not supported"
 msgstr ""
 
-#: vms-tir.c:706
+#: vms-tir.c:698
 msgid "ETIR_S_C_OPR_DFLIT: Not supported"
 msgstr ""
 
-#: vms-tir.c:710 vms-tir.c:1656
+#: vms-tir.c:702 vms-tir.c:1641
 #, c-format
 msgid "Reserved OPR cmd %d"
 msgstr ""
 
-#: vms-tir.c:779 vms-tir.c:1726
+#: vms-tir.c:770 vms-tir.c:1710
 #, c-format
 msgid "Reserved CTL cmd %d"
 msgstr ""
 
-#: vms-tir.c:808
+#: vms-tir.c:798
 msgid "ETIR_S_C_STC_LP: not supported"
 msgstr ""
 
-#: vms-tir.c:826
+#: vms-tir.c:816
 msgid "ETIR_S_C_STC_GBL: not supported"
 msgstr ""
 
-#: vms-tir.c:834
+#: vms-tir.c:824
 msgid "ETIR_S_C_STC_GCA: not supported"
 msgstr ""
 
-#: vms-tir.c:843
+#: vms-tir.c:833
 msgid "ETIR_S_C_STC_PS: not supported"
 msgstr ""
 
@@ -2024,11 +2024,11 @@ msgstr ""
 #. * arg: -
 #. *
 #.
-#: vms-tir.c:1187
+#: vms-tir.c:1174
 msgid "Stack-from-image not implemented"
 msgstr ""
 
-#: vms-tir.c:1207
+#: vms-tir.c:1194
 msgid "Stack-entry-mask not fully implemented"
 msgstr ""
 
@@ -2041,76 +2041,76 @@ msgstr ""
 #. * compare argument descriptor with symbol argument (ARG$V_PASSMECH)
 #. * and stack TRUE (args match) or FALSE (args dont match) value
 #.
-#: vms-tir.c:1223
+#: vms-tir.c:1210
 msgid "PASSMECH not fully implemented"
 msgstr ""
 
-#: vms-tir.c:1243
+#: vms-tir.c:1230
 msgid "Stack-local-symbol not fully implemented"
 msgstr ""
 
-#: vms-tir.c:1258
+#: vms-tir.c:1245
 msgid "Stack-literal not fully implemented"
 msgstr ""
 
-#: vms-tir.c:1280
+#: vms-tir.c:1267
 msgid "Stack-local-symbol-entry-point-mask not fully implemented"
 msgstr ""
 
-#: vms-tir.c:1456
+#: vms-tir.c:1442
 #, c-format
 msgid "Unimplemented STO cmd %d"
 msgstr ""
 
-#: vms-tir.c:1596
+#: vms-tir.c:1581
 msgid "TIR_S_C_OPR_ASH incomplete"
 msgstr ""
 
-#: vms-tir.c:1610
+#: vms-tir.c:1595
 msgid "TIR_S_C_OPR_USH incomplete"
 msgstr ""
 
-#: vms-tir.c:1624
+#: vms-tir.c:1609
 msgid "TIR_S_C_OPR_ROT incomplete"
 msgstr ""
 
 #.
 #. * redefine symbol to current location
 #.
-#: vms-tir.c:1645
+#: vms-tir.c:1630
 msgid "TIR_S_C_OPR_REDEF not supported"
 msgstr ""
 
 #.
 #. * define a literal
 #.
-#: vms-tir.c:1652
+#: vms-tir.c:1637
 msgid "TIR_S_C_OPR_DFLIT not supported"
 msgstr ""
 
-#: vms-tir.c:1707
+#: vms-tir.c:1691
 msgid "TIR_S_C_CTL_DFLOC not fully implemented"
 msgstr ""
 
-#: vms-tir.c:1715
+#: vms-tir.c:1699
 msgid "TIR_S_C_CTL_STLOC not fully implemented"
 msgstr ""
 
-#: vms-tir.c:1723
+#: vms-tir.c:1707
 msgid "TIR_S_C_CTL_STKDL not fully implemented"
 msgstr ""
 
-#: vms-tir.c:1778
+#: vms-tir.c:1761
 #, c-format
 msgid "Obj code %d not found"
 msgstr ""
 
-#: vms-tir.c:2127
+#: vms-tir.c:2102
 #, c-format
 msgid "SEC_RELOC with no relocs in section %s"
 msgstr ""
 
-#: vms-tir.c:2401
+#: vms-tir.c:2376
 #, c-format
 msgid "Unhandled relocation %s"
 msgstr ""
diff --git a/bfd/reloc.c b/bfd/reloc.c
index f3ac667..f37a6a9 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -2336,7 +2336,7 @@ ENUMDOC
 ENUM
   BFD_RELOC_ARC_B22_PCREL
 ENUMDOC
-  Argonaut RISC Core (ARC) relocs.
+  ARC Cores relocs.
   ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
   not stored in the instruction.  The high 20 bits are installed in bits 26
   through 7 of the instruction.
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 3a8257e..bc8e674 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* readelf.c (dump_relocations): Include selection with EM_ARC.
+	(get_machine_name) Update name to "ARC".
+
 2001-01-09  Nick Clifton  <nickc@redhat.com>
 
 	* Makefile.am: Add rule to build objdump.o from objdump.c and
diff --git a/binutils/po/binutils.pot b/binutils/po/binutils.pot
index 7c50f2d..b497a04 100644
--- a/binutils/po/binutils.pot
+++ b/binutils/po/binutils.pot
@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2001-01-09 12:08-0800\n"
+"POT-Creation-Date: 2001-01-11 12:02-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 96df47a..f3b8069 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,31 @@
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* as.h (TC_ARC): Ensure struc-symbol.h included.
+	* as.c (dwarf2dbg.h): Include to remove implicit declaration
+	warnings.
+	* struc-symbol.h (SYMBOLS_NEED_BACKPOINTERS): Define.
+	(TARGET_SYMBOL_FIELDS) added.
+
+	* doc/Makefile.am (CPU_DOCS): Added c-arc.texi.
+	* doc/c-arc.texi: New file.
+	Some sections to be expanded.
+	* doc/as.texinfo: Update command-line options.
+	Removed outdated text for ARC dependant features, instead include
+	text from above file.
+
+	* config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Define local flag.
+	(TARGET_SYMBOL_FIELDS): Alias to previous definition.
+	(targ-cpu.h) header.
+	* config/tc-arc.h:
+	* config/tc-arc.c: New updated configuration for
+	ARC, including selection of core variants, and extensibility of
+	instructions, registers etc. through directives.
+
+	* config/tc-arc.c (arc_extinst): Minor corrections for
+	error messages.
+	(arc_common) Likewise. Make alignment argument optional for local
+	symbols also, with default of zero.
+
 2001-01-11  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
 
 	* config/tc-m68hc11.c (md_estimate_size_before_relax): Fix
diff --git a/gas/as.h b/gas/as.h
index fe64988..a98acfe 100644
--- a/gas/as.h
+++ b/gas/as.h
@@ -622,6 +622,10 @@ void eh_frame_convert_frag PARAMS ((fragS *));
 /* this one starts the chain of target dependant headers */
 #include "targ-env.h"
 
+#ifdef TC_ARC
+#include "struc-symbol.h"
+#endif
+
 #include "write.h"
 #include "frags.h"
 #include "hash.h"
diff --git a/gas/config/obj-elf.h b/gas/config/obj-elf.h
index ce93be5..43daf64 100644
--- a/gas/config/obj-elf.h
+++ b/gas/config/obj-elf.h
@@ -85,6 +85,14 @@ struct elf_obj_sy
 
 #define OBJ_SYMFIELD_TYPE struct elf_obj_sy
 
+/* Symbol fields used by the ELF back end.  */
+#define ELF_TARGET_SYMBOL_FIELDS int local:1;
+
+/* Don't change this; change ELF_TARGET_SYMBOL_FIELDS instead.  */
+#define TARGET_SYMBOL_FIELDS ELF_TARGET_SYMBOL_FIELDS
+
+/* #include "targ-cpu.h" */
+
 #ifndef FALSE
 #define FALSE 0
 #define TRUE  !FALSE
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 819be45..754829f 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -1,6 +1,5 @@
 /* tc-arc.c -- Assembler for the ARC
-   Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000
-   Free Software Foundation, Inc.
+   Copyright (C) 1994, 1995, 1997, 2000 Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
 
    This file is part of GAS, the GNU Assembler.
@@ -16,38 +15,83 @@
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include <stdio.h>
 #include <ctype.h>
+#include "libiberty.h"
 #include "as.h"
 #include "subsegs.h"
 #include "opcode/arc.h"
+#include "../opcodes/arc-ext.h"
 #include "elf/arc.h"
 
 extern int arc_get_mach PARAMS ((char *));
+extern int arc_operand_type PARAMS ((int));
+extern int arc_insn_not_jl PARAMS ((arc_insn));
+extern int arc_limm_fixup_adjust PARAMS ((arc_insn));
+extern int arc_get_noshortcut_flag PARAMS ((void));
+extern int arc_set_ext_seg PARAMS ((void));
+extern void arc_code_symbol PARAMS((expressionS *));
 
 static arc_insn arc_insert_operand PARAMS ((arc_insn,
 					    const struct arc_operand *, int,
 					    const struct arc_operand_value *,
 					    offsetT, char *, unsigned int));
 static void arc_common PARAMS ((int));
-static void arc_cpu PARAMS ((int));
-/*static void arc_rename PARAMS ((int));*/
+static void arc_extinst PARAMS ((int));
+static void arc_extoper PARAMS ((int));
+static void arc_option PARAMS ((int));
 static int get_arc_exp_reloc_type PARAMS ((int, int, expressionS *,
 					   expressionS *));
 
+const struct suffix_classes {
+  char *name;
+  int  len;
+} suffixclass[] = {
+  { "SUFFIX_COND|SUFFIX_FLAG",23 },
+  { "SUFFIX_FLAG", 11 },
+  { "SUFFIX_COND", 11 },
+  { "SUFFIX_NONE", 11 }
+};
+
+#define MAXSUFFIXCLASS (sizeof(suffixclass) / sizeof(struct suffix_classes))
+
+const struct syntax_classes {
+  char *name;
+  int  len;
+  int  class;
+} syntaxclass[] = {
+  { "SYNTAX_3OP|OP1_MUST_BE_IMM", 26, SYNTAX_3OP|OP1_MUST_BE_IMM|SYNTAX_VALID },
+  { "OP1_MUST_BE_IMM|SYNTAX_3OP", 26, OP1_MUST_BE_IMM|SYNTAX_3OP|SYNTAX_VALID },
+  { "SYNTAX_2OP|OP1_IMM_IMPLIED", 26, SYNTAX_2OP|OP1_IMM_IMPLIED|SYNTAX_VALID },
+  { "OP1_IMM_IMPLIED|SYNTAX_2OP", 26, OP1_IMM_IMPLIED|SYNTAX_2OP|SYNTAX_VALID },
+  { "SYNTAX_3OP",                 10, SYNTAX_3OP|SYNTAX_VALID },
+  { "SYNTAX_2OP",                 10, SYNTAX_2OP|SYNTAX_VALID }
+};
+
+#define MAXSYNTAXCLASS (sizeof(syntaxclass) / sizeof(struct syntax_classes))
+
 const pseudo_typeS md_pseudo_table[] =
 {
-  { "align", s_align_bytes, 0 },	/* Defaulting is invalid (0) */
+  { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0) */
+  { "comm", arc_common, 0 },
   { "common", arc_common, 0 },
-/*{ "hword", cons, 2 }, - already exists */
+  { "lcomm", arc_common, 1 },
+  { "lcommon", arc_common, 1 },
+  { "2byte", cons, 2 },
+  { "half", cons, 2 },
+  { "short", cons, 2 },
+  { "3byte", cons, 3 },
+  { "4byte", cons, 4 },
   { "word", cons, 4 },
-/*{ "xword", cons, 8 },*/
-  { "cpu", arc_cpu, 0 },
-/*{ "rename", arc_rename, 0 },*/
+  { "option", arc_option, 0 },
+  { "block", s_space, 0 },
+  { "extcondcode", arc_extoper, 0 },
+  { "extcoreregister", arc_extoper, 1 },
+  { "extauxregister", arc_extoper, 2 },
+  { "extinstruction", arc_extinst, 0 },
   { NULL, 0, 0 },
 };
 
@@ -60,9 +104,9 @@ const char comment_chars[] = "#;";
    .line and .file directives will appear in the pre-processed output */
 /* Note that input_file.c hand checks for '#' at the beginning of the
    first line of the input file.  This is because the compiler outputs
-   #NO_APP at the beginning of its output.  */
+   #NO_APP at the beginning of its output. */
 /* Also note that comments started like this one will always
-   work if '/' isn't otherwise defined.  */
+   work if '/' isn't otherwise defined. */
 const char line_comment_chars[] = "#";
 
 const char line_separator_chars[] = "";
@@ -80,8 +124,10 @@ extern int target_big_endian;
 const char *arc_target_format = DEFAULT_TARGET_FORMAT;
 static int byte_order = DEFAULT_BYTE_ORDER;
 
-/* One of bfd_mach_arc_xxx.  */
-static int arc_mach_type = bfd_mach_arc_base;
+static segT arcext_section;
+
+/* One of bfd_mach_arc_n.  */
+static int arc_mach_type = bfd_mach_arc_5;
 
 /* Non-zero if the cpu type has been explicitly specified.  */
 static int mach_type_specified_p = 0;
@@ -99,10 +145,25 @@ struct option md_longopts[] =
   {"EB", no_argument, NULL, OPTION_EB},
 #define OPTION_EL (OPTION_MD_BASE + 1)
   {"EL", no_argument, NULL, OPTION_EL},
+#define OPTION_ARC5 (OPTION_MD_BASE + 2)
+  {"marc5", no_argument, NULL, OPTION_ARC5},
+#define OPTION_ARC6 (OPTION_MD_BASE + 3)
+  {"marc6", no_argument, NULL, OPTION_ARC6},
+#define OPTION_ARC7 (OPTION_MD_BASE + 4)
+  {"marc7", no_argument, NULL, OPTION_ARC7},
+#define OPTION_ARC8 (OPTION_MD_BASE + 5)
+  {"marc8", no_argument, NULL, OPTION_ARC8},
+#define OPTION_ARC (OPTION_MD_BASE + 6)
+  {"marc", no_argument, NULL, OPTION_ARC},
   { NULL, no_argument, NULL, 0 }
 };
 size_t md_longopts_size = sizeof (md_longopts);
 
+#define IS_SYMBOL_OPERAND(o) \
+ ((o) == 'b' || (o) == 'c' || (o) == 's' || (o) == 'o' || (o) == 'O')
+
+struct arc_operand_value *get_ext_suffix(char *s);
+
 /*
  * md_parse_option
  *
@@ -116,7 +177,20 @@ md_parse_option (c, arg)
      char *arg ATTRIBUTE_UNUSED;
 {
   switch (c)
-    {
+  {
+    case OPTION_ARC:
+    case OPTION_ARC5:
+      arc_mach_type = bfd_mach_arc_5;
+      break;
+    case OPTION_ARC6:
+      arc_mach_type = bfd_mach_arc_6;
+      break;
+    case OPTION_ARC7:
+      arc_mach_type = bfd_mach_arc_7;
+      break;
+    case OPTION_ARC8:
+      arc_mach_type = bfd_mach_arc_8;
+      break;
     case OPTION_EB:
       byte_order = BIG_ENDIAN;
       arc_target_format = "elf32-bigarc";
@@ -127,7 +201,7 @@ md_parse_option (c, arg)
       break;
     default:
       return 0;
-    }
+  }
   return 1;
 }
 
@@ -135,10 +209,11 @@ void
 md_show_usage (stream)
      FILE *stream;
 {
-  fprintf (stream, _("\
-ARC options:\n\
--EB			generate big endian output\n\
--EL			generate little endian output\n"));
+  fprintf (stream, "\
+ARC Options:\n\
+  -marc[5|6|7|8]          select processor variant (default arc%d)\n\
+  -EB                     assemble code for a big endian cpu\n\
+  -EL                     assemble code for a little endian cpu\n", arc_mach_type + 5);
 }
 
 /* This function is called once, at assembler startup time.  It should
@@ -153,12 +228,12 @@ md_begin ()
   target_big_endian = byte_order == BIG_ENDIAN;
 
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
-    as_warn (_("could not set architecture and machine"));
+    as_warn ("could not set architecture and machine");
 
-  /* Assume the base cpu.  This call is necessary because we need to
+  /* This call is necessary because we need to
      initialize `arc_operand_map' which may be needed before we see the
      first insn.  */
-  arc_opcode_init_tables (arc_get_opcode_mach (bfd_mach_arc_base,
+  arc_opcode_init_tables (arc_get_opcode_mach (arc_mach_type,
 					       target_big_endian));
 }
 
@@ -173,10 +248,10 @@ init_opcode_tables (mach)
   char *last;
 
   if ((arc_suffix_hash = hash_new ()) == NULL)
-    as_fatal (_("virtual memory exhausted"));
+    as_fatal ("virtual memory exhausted");
 
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
-    as_warn (_("could not set architecture and machine"));
+    as_warn ("could not set architecture and machine");
 
   /* This initializes a few things in arc-opc.c that we need.
      This must be called before the various arc_xxx_supported fns.  */
@@ -187,8 +262,6 @@ init_opcode_tables (mach)
   last = "";
   for (i = 0; i < arc_suffixes_count; i++)
     {
-      if (! arc_opval_supported (&arc_suffixes[i]))
-	continue;
       if (strcmp (arc_suffixes[i].name, last) != 0)
 	hash_insert (arc_suffix_hash, arc_suffixes[i].name, (PTR) (arc_suffixes + i));
       last = arc_suffixes[i].name;
@@ -197,18 +270,22 @@ init_opcode_tables (mach)
   /* Since registers don't have a prefix, we put them in the symbol table so
      they can't be used as symbols.  This also simplifies argument parsing as
      we can let gas parse registers for us.  The recorded register number is
-     the index in `arc_reg_names'.  */
+     the address of the register's entry in arc_reg_names.
+
+     If the register name is already in the table, then the existing
+     definition is assumed to be from an .ExtCoreRegister pseudo-op.  */
+
   for (i = 0; i < arc_reg_names_count; i++)
     {
-      if (! arc_opval_supported (&arc_reg_names[i]))
+      if (symbol_find(arc_reg_names[i].name))
 	continue;
       /* Use symbol_create here instead of symbol_new so we don't try to
 	 output registers into the object file's symbol table.  */
       symbol_table_insert (symbol_create (arc_reg_names[i].name, reg_section,
-					  i, &zero_address_frag));
+                           (int) &arc_reg_names[i], &zero_address_frag));
     }
 
-  /* Tell `s_cpu' it's too late.  */
+  /* Tell `.option' it's too late.  */
   cpu_tables_init_p = 1;
 }
 
@@ -252,7 +329,7 @@ arc_insert_operand (insn, operand, mods, reg, val, file, line)
       if (test < (offsetT) min || test > (offsetT) max)
 	{
 	  const char *err =
-	    _("operand out of range (%s not between %ld and %ld)");
+	    "operand out of range (%s not between %ld and %ld)";
 	  char buf[100];
 
 	  sprint_value (buf, test);
@@ -301,7 +378,10 @@ md_assemble (str)
      char *str;
 {
   const struct arc_opcode *opcode;
+  const struct arc_opcode *std_opcode;
+  struct arc_opcode *ext_opcode;
   char *start;
+  const char *last_errmsg = 0;
   arc_insn insn;
   static int init_tables_p = 0;
 
@@ -320,19 +400,26 @@ md_assemble (str)
   /* The instructions are stored in lists hashed by the first letter (though
      we needn't care how they're hashed).  Get the first in the list.  */
 
-  opcode = arc_opcode_lookup_asm (str);
+  ext_opcode = arc_ext_opcodes;
+  std_opcode = arc_opcode_lookup_asm (str);
 
   /* Keep looking until we find a match.  */
 
   start = str;
-  for ( ; opcode != NULL; opcode = ARC_OPCODE_NEXT_ASM (opcode))
+  for (opcode = (ext_opcode ? ext_opcode : std_opcode) ;
+       opcode != NULL;
+       opcode = (ARC_OPCODE_NEXT_ASM (opcode)
+         ? ARC_OPCODE_NEXT_ASM (opcode)
+         : (ext_opcode ? ext_opcode = NULL, std_opcode : NULL)))
     {
       int past_opcode_p, fc, num_suffixes;
+      int fix_up_at = 0;
       char *syn;
       struct arc_fixup fixups[MAX_FIXUPS];
       /* Used as a sanity check.  If we need a limm reloc, make sure we ask
 	 for an extra 4 bytes from frag_more.  */
       int limm_reloc_p;
+      int ext_suffix_p;
       const struct arc_operand_value *insn_suffixes[MAX_SUFFIXES];
 
       /* Is this opcode supported by the selected cpu?  */
@@ -347,6 +434,7 @@ md_assemble (str)
       past_opcode_p = 0;
       num_suffixes = 0;
       limm_reloc_p = 0;
+      ext_suffix_p = 0;
 
       /* We don't check for (*str != '\0') here because we want to parse
 	 any trailing fake arguments in the syntax string.  */
@@ -387,7 +475,7 @@ md_assemble (str)
 	    }
 	  operand = arc_operands + arc_operand_map[(int) *syn];
 	  if (operand->fmt == 0)
-	    as_fatal (_("unknown syntax format character `%c'"), *syn);
+	    as_fatal ("unknown syntax format character `%c'", *syn);
 
 	  if (operand->flags & ARC_OPERAND_FAKE)
 	    {
@@ -395,9 +483,25 @@ md_assemble (str)
 	      if (operand->insert)
 		{
 		  insn = (*operand->insert) (insn, operand, mods, NULL, 0, &errmsg);
-		  /* If we get an error, go on to try the next insn.  */
-		  if (errmsg)
-		    break;
+                  if (errmsg != (const char *) NULL)
+                    {
+                    last_errmsg = errmsg;
+                    if (operand->flags & ARC_OPERAND_ERROR)
+                      {
+                      as_bad (errmsg);
+                      return;
+                      }
+                    else if (operand->flags & ARC_OPERAND_WARN)
+                      as_warn (errmsg);
+                    break;
+                    }
+		  if(limm_reloc_p
+                   && (operand->flags && operand->flags & ARC_OPERAND_LIMM)
+                   && (operand->flags &
+                        (ARC_OPERAND_ABSOLUTE_BRANCH | ARC_OPERAND_ADDRESS)))
+                    {
+		    fixups[fix_up_at].opindex = arc_operand_map[operand->fmt];
+                    }
 		}
 	      ++syn;
 	    }
@@ -407,7 +511,8 @@ md_assemble (str)
 	      int found;
 	      char c;
 	      char *s,*t;
-	      const struct arc_operand_value *suf,*suffix,*suffix_end;
+	      const struct arc_operand_value *suf,*suffix_end;
+	      const struct arc_operand_value *suffix = NULL;
 
 	      if (!(operand->flags & ARC_OPERAND_SUFFIX))
 		abort ();
@@ -440,17 +545,20 @@ md_assemble (str)
 		}
 
 	      /* Pick the suffix out and look it up via the hash table.  */
-	      for (t = s; *t && isalpha (*t); ++t)
+	      for (t = s; *t && isalnum (*t); ++t)
 		continue;
 	      c = *t;
 	      *t = '\0';
-	      suf = hash_find (arc_suffix_hash, s);
-	      *t = c;
+              if ((suf = get_ext_suffix(s)))
+                ext_suffix_p = 1;
+              else
+	        suf = hash_find (arc_suffix_hash, s);
 	      if (!suf)
 		{
 		  /* This can happen in "blle foo" and we're currently using
 		     the template "b%q%.n %j".  The "bl" insn occurs later in
 		     the table so "lle" isn't an illegal suffix.  */
+	          *t = c;
 		  break;
 		}
 
@@ -460,33 +568,51 @@ md_assemble (str)
 		 together.  If it's not the right type, don't increment `str'
 		 so we try the next one in the series.  */
 	      found = 0;
-	      suffix_end = arc_suffixes + arc_suffixes_count;
-	      for (suffix = suf;
-		   suffix < suffix_end && strcmp (suffix->name, suf->name) == 0;
-		   ++suffix)
-		{
-		  if (arc_operands[suffix->type].fmt == *syn)
-		    {
-		      /* Insert the suffix's value into the insn.  */
-		      if (operand->insert)
-			insn = (*operand->insert) (insn, operand,
-						   mods, NULL, suffix->value,
-						   NULL);
-		      else
-			insn |= suffix->value << operand->shift;
-
-		      str = t;
-		      found = 1;
-		      break;
-		    }
-		}
+              if (ext_suffix_p && arc_operands[suf->type].fmt == *syn)
+                {
+                  /* Insert the suffix's value into the insn.  */
+	          *t = c;
+                  if (operand->insert)
+                    insn = (*operand->insert) (insn, operand,
+                                               mods, NULL, suf->value,
+                                               NULL);
+                  else
+                    insn |= suf->value << operand->shift;
+
+                  str = t;
+                  found = 1;
+                }
+              else
+                {
+	          *t = c;
+	          suffix_end = arc_suffixes + arc_suffixes_count;
+	          for (suffix = suf;
+		     suffix < suffix_end && strcmp (suffix->name, suf->name) == 0;
+		     ++suffix)
+		     {
+		       if (arc_operands[suffix->type].fmt == *syn)
+		         {
+		           /* Insert the suffix's value into the insn.  */
+		           if (operand->insert)
+			     insn = (*operand->insert) (insn, operand,
+						    mods, NULL, suffix->value,
+						    NULL);
+		           else
+			     insn |= suffix->value << operand->shift;
+ 
+		           str = t;
+		           found = 1;
+		           break;
+		         }
+		      }
+                 }
 	      ++syn;
 	      if (!found)
 		; /* Wrong type.  Just go on to try next insn entry.  */
 	      else
 		{
 		  if (num_suffixes == MAX_SUFFIXES)
-		    as_bad (_("too many suffixes"));
+		    as_bad ("too many suffixes");
 		  else
 		    insn_suffixes[num_suffixes++] = suffix;
 		}
@@ -507,20 +633,6 @@ md_assemble (str)
 		 any trailing fake arguments in the syntax string.  */
 	      if (*str == '\0')
 		break;
-#if 0
-	      /* Is this a syntax character?  Eg: is there a '[' present when
-		 there shouldn't be?  */
-	      if (!isalnum (*str)
-		  /* '.' as in ".LLC0" */
-		  && *str != '.'
-		  /* '_' as in "_print" */
-		  && *str != '_'
-		  /* '-' as in "[fp,-4]" */
-		  && *str != '-'
-		  /* '%' as in "%ia(_func)" */
-		  && *str != '%')
-		break;
-#endif
 
 	      /* Parse the operand.  */
 	      hold = input_line_pointer;
@@ -530,37 +642,48 @@ md_assemble (str)
 	      input_line_pointer = hold;
 
 	      if (exp.X_op == O_illegal)
-		as_bad (_("illegal operand"));
+		as_bad ("illegal operand");
 	      else if (exp.X_op == O_absent)
-		as_bad (_("missing operand"));
+		as_bad ("missing operand");
 	      else if (exp.X_op == O_constant)
 		{
 		  value = exp.X_add_number;
 		}
 	      else if (exp.X_op == O_register)
 		{
-		  reg = arc_reg_names + exp.X_add_number;
+		  reg = (struct arc_operand_value *) exp.X_add_number;
 		}
-	      else
+#define IS_REG_DEST_OPERAND(o) ((o) == 'a')
+	      else if (IS_REG_DEST_OPERAND (*syn))
+                as_bad("symbol as destination register");
+              else
 		{
+                  if(!strncmp(str,"@h30",4))
+                    {
+                    arc_code_symbol(&exp);
+                    str += 4;
+                    }
 		  /* We need to generate a fixup for this expression.  */
 		  if (fc >= MAX_FIXUPS)
-		    as_fatal (_("too many fixups"));
+		    as_fatal ("too many fixups");
 		  fixups[fc].exp = exp;
-
+                  /* We don't support shimm relocs. break here to force
+                     the assembler to output a limm  */
+#define IS_REG_SHIMM_OFFSET(o) ((o) == 'd')
+                  if(IS_REG_SHIMM_OFFSET(*syn))
+                    break;
 		  /* If this is a register constant (IE: one whose
 		     register value gets stored as 61-63) then this
-		     must be a limm.  We don't support shimm relocs.  */
+		     must be a limm. */
 		  /* ??? This bit could use some cleaning up.
 		     Referencing the format chars like this goes
 		     against style.  */
-#define IS_REG_OPERAND(o) ((o) == 'a' || (o) == 'b' || (o) == 'c')
-		  if (IS_REG_OPERAND (*syn))
+		  if (IS_SYMBOL_OPERAND (*syn))
 		    {
 		      const char *junk;
-
-		      fixups[fc].opindex = arc_operand_map['L'];
 		      limm_reloc_p = 1;
+                      /* save this, we don't yet know what reloc to use */ 
+                      fix_up_at = fc;
 		      /* Tell insert_reg we need a limm.  This is
 			 needed because the value at this point is
 			 zero, a shimm.  */
@@ -580,18 +703,18 @@ md_assemble (str)
 		  const char *errmsg = NULL;
 		  insn = (*operand->insert) (insn, operand, mods,
 					     reg, (long) value, &errmsg);
-#if 0
-		  if (errmsg != (const char *) NULL)
-		    as_warn (errmsg);
-#endif
-		  /* FIXME: We want to try shimm insns for limm ones.  But if
-		     the constant won't fit, we must go on to try the next
-		     possibility.  Where do we issue warnings for constants
-		     that are too big then?  At present, we'll flag the insn
-		     as unrecognizable!  Maybe have the "bad instruction"
-		     error message include our `errmsg'?  */
-		  if (errmsg != (const char *) NULL)
-		    break;
+                  if (errmsg != (const char *) NULL)
+                    {
+                    last_errmsg = errmsg;
+                    if (operand->flags & ARC_OPERAND_ERROR)
+                      {
+                      as_bad (errmsg);
+                      return;
+                      }
+                    else if (operand->flags & ARC_OPERAND_WARN)
+                      as_warn (errmsg);
+                    break;
+                    }
 		}
 	      else
 		insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
@@ -617,7 +740,7 @@ md_assemble (str)
 	    ++str;
 
 	  if (*str != '\0')
-	    as_bad (_("junk at end of line: `%s'"), str);
+	    as_bad ("junk at end of line: `%s'", str);
 
 	  /* Is there a limm value?  */
 	  limm_p = arc_opcode_limm_p (&limm);
@@ -656,18 +779,22 @@ md_assemble (str)
 	       be legal, but let's warn the user anyway.  Ditto for 8 byte
 	       jumps with delay slots.  */
 	    if (in_delay_slot_p && limm_p)
-	      as_warn (_("8 byte instruction in delay slot"));
-	    if (delay_slot_type != ARC_DELAY_NONE && limm_p)
-	      as_warn (_("8 byte jump instruction with delay slot"));
+		as_warn ("8 byte instruction in delay slot");
+	    if (delay_slot_type != ARC_DELAY_NONE
+		&& limm_p && arc_insn_not_jl(insn)) /* except for jl  addr */
+		as_warn ("8 byte jump instruction with delay slot");
 	    in_delay_slot_p = (delay_slot_type != ARC_DELAY_NONE) && !limm_p;
 
 	    /* Warn when a conditional branch immediately follows a set of
 	       the condition codes.  Note that this needn't be done if the
 	       insn that sets the condition codes uses a limm.  */
 	    if (cond_branch_p && conditional != 0 /* 0 = "always" */
-		&& prev_insn_needs_cc_nop_p)
-	      as_warn (_("conditional branch follows set of flags"));
-	    prev_insn_needs_cc_nop_p = cc_set_p && !limm_p;
+		&& prev_insn_needs_cc_nop_p && arc_mach_type == bfd_mach_arc_5)
+		as_warn ("conditional branch follows set of flags");
+	    prev_insn_needs_cc_nop_p =
+	    /* FIXME: ??? not required:
+	       (delay_slot_type != ARC_DELAY_NONE) &&  */
+		cc_set_p && !limm_p;
 	  }
 
 	  /* Write out the instruction.
@@ -711,9 +838,14 @@ md_assemble (str)
 
 	      if (arc_operands[fixups[i].opindex].flags & ARC_OPERAND_LIMM)
 		{
+                /* modify the fixup addend as required by the cpu */
+                  fixups[i].exp.X_add_number += arc_limm_fixup_adjust(insn);
 		  op_type = fixups[i].opindex;
 		  /* FIXME: can we add this data to the operand table?  */
-		  if (op_type == arc_operand_map['L'])
+		  if (op_type == arc_operand_map['L']
+                   || op_type == arc_operand_map['s']
+                   || op_type == arc_operand_map['o']
+                   || op_type == arc_operand_map['O'])
 		    reloc_type = BFD_RELOC_32;
 		  else if (op_type == arc_operand_map['J'])
 		    reloc_type = BFD_RELOC_ARC_B26;
@@ -745,246 +877,673 @@ md_assemble (str)
       /* Try the next entry.  */
     }
 
-  as_bad (_("bad instruction `%s'"), start);
+  if(NULL == last_errmsg)
+    as_bad ("bad instruction `%s'", start);
+  else
+    as_bad (last_errmsg);
 }
+
 
-/* ??? This was copied from tc-sparc.c, I think.  Is it necessary?  */
 
 static void
-arc_common (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+arc_extoper (opertype)
+     int opertype;
 {
   char *name;
+  char *mode;
   char c;
   char *p;
-  int temp;
-  unsigned int size;
+  int imode = 0;
+  int number;
+  struct arc_ext_operand_value *ext_oper;
   symbolS *symbolP;
 
+  segT old_sec;
+  int old_subsec;
+
   name = input_line_pointer;
   c = get_symbol_end ();
+  name = xstrdup(name);
+  if (NULL == name)
+    {
+    ignore_rest_of_line();
+    return;
+    }
+
+  p = name;
+  while (*p)
+    {
+    if (isupper(*p))
+      *p = tolower(*p);
+    p++;
+    }
+
   /* just after name is now '\0' */
   p = input_line_pointer;
   *p = c;
   SKIP_WHITESPACE ();
+
   if (*input_line_pointer != ',')
     {
-      as_bad (_("expected comma after symbol-name"));
+      as_bad ("expected comma after operand name");
       ignore_rest_of_line ();
+      free(name);
       return;
     }
+
   input_line_pointer++;		/* skip ',' */
-  if ((temp = get_absolute_expression ()) < 0)
+  number = get_absolute_expression ();
+
+  if(number < 0)
+    {
+    as_bad ("negative operand number %d",number);
+    ignore_rest_of_line();
+    free(name);
+    return;
+    }
+
+  if (opertype)
+    {
+      SKIP_WHITESPACE();
+
+      if (*input_line_pointer != ',')
+        {
+          as_bad ("expected comma after register-number");
+          ignore_rest_of_line ();
+          free(name);
+          return;
+        }
+    
+      input_line_pointer++;		/* skip ',' */
+      mode = input_line_pointer;
+    
+      if (!strncmp(mode, "r|w",3))
+        {
+          imode = 0;
+          input_line_pointer += 3;
+        }
+      else
+        {
+          if (!strncmp(mode,"r",1))
+            {
+              imode = ARC_REGISTER_READONLY;
+              input_line_pointer += 1;
+            }
+          else
+            {
+              if (strncmp(mode,"w",1))
+                {
+                  as_bad ("invalid mode");
+                  ignore_rest_of_line();
+                  free(name);
+                  return;
+                }
+              else
+                {
+                  imode = ARC_REGISTER_WRITEONLY;
+                  input_line_pointer += 1;
+                }
+            }
+          }
+    SKIP_WHITESPACE();
+    if (1 == opertype)
+      {
+        if (*input_line_pointer != ',')
+          {
+            as_bad ("expected comma after register-mode");
+            ignore_rest_of_line ();
+            free(name);
+            return;
+          }
+
+        input_line_pointer++;             /* skip ',' */
+
+        if(!strncmp(input_line_pointer,"cannot_shortcut",15))
+          {
+          imode |= arc_get_noshortcut_flag();
+          input_line_pointer += 15;
+          }
+      else
+        {
+          if(strncmp(input_line_pointer,"can_shortcut",12))
+            {
+            as_bad ("shortcut designator invalid");
+            ignore_rest_of_line();
+            free(name);
+            return;
+            }
+          else
+           {
+             input_line_pointer += 12; 
+           }
+         }
+       }
+     }
+
+  if ((opertype == 1) && number > 60)
+   {
+   as_bad("core register value (%d) too large", number);
+   ignore_rest_of_line();
+   free(name);
+   return;
+   }
+
+  if ((opertype == 0) && number > 31)
+   {
+   as_bad("condition code value (%d) too large", number);
+   ignore_rest_of_line();
+   free(name);
+   return;
+   }
+
+  ext_oper = (struct arc_ext_operand_value *) \
+      xmalloc(sizeof(struct arc_ext_operand_value));
+
+  if(opertype)
+    {
+      /* if the symbol already exists, point it at the new definition */ 
+      if ((symbolP = symbol_find (name)))
+        {
+          if (S_GET_SEGMENT(symbolP) == reg_section)
+            S_SET_VALUE(symbolP,(int)&ext_oper->operand);
+          else
+            {
+              as_bad("attempt to override symbol: %s",name);
+              ignore_rest_of_line();
+              free(name);
+              free(ext_oper);
+              return;
+            }
+        }
+      else
+        {
+        /* If its not there, add it */
+        symbol_table_insert (symbol_create (name, reg_section,
+                           (int) &ext_oper->operand, &zero_address_frag));
+        }
+    }
+
+  ext_oper->operand.name  = name;
+  ext_oper->operand.value = number;
+  ext_oper->operand.type  = arc_operand_type(opertype);
+  ext_oper->operand.flags = imode;
+
+  ext_oper->next = arc_ext_operands;
+  arc_ext_operands = ext_oper;
+
+/* ok, now that we know what this operand is, put a description
+   in the arc extension section of the output file */
+
+  old_sec    = now_seg;
+  old_subsec = now_subseg;
+
+  arc_set_ext_seg();
+
+  switch (opertype)
+   {
+   case 0:
+    p = frag_more(1);
+    *p = 3 + strlen(name) + 1;
+    p = frag_more(1);
+    *p = EXT_COND_CODE;
+    p = frag_more(1);
+    *p = number;
+    p = frag_more(strlen(name) + 1);
+    strcpy(p,name);
+    break;
+   case 1:
+    p = frag_more(1);
+    *p = 3 + strlen(name) + 1;
+    p = frag_more(1);
+    *p = EXT_CORE_REGISTER;
+    p = frag_more(1);
+    *p = number;
+    p = frag_more(strlen(name) + 1);
+    strcpy(p,name);
+    break;
+   case 2:
+    p = frag_more(1);
+    *p = 6 + strlen(name) + 1;
+    p = frag_more(1);
+    *p = EXT_AUX_REGISTER;
+    p = frag_more(1);
+    *p = number >> 24 & 0xff;
+    p = frag_more(1);
+    *p = number >> 16 & 0xff;
+    p = frag_more(1);
+    *p = number >>  8 & 0xff;
+    p = frag_more(1);
+    *p = number       & 0xff;
+    p = frag_more(strlen(name) + 1);
+    strcpy(p,name);
+    break;
+   default:
+    as_bad("invalid opertype");
+    ignore_rest_of_line();
+    free(name);
+    return;
+    break;
+   }
+
+  subseg_set (old_sec, old_subsec);
+
+/* enter all registers into the symbol table */
+
+  demand_empty_rest_of_line();
+}
+
+static void
+arc_extinst (ignore)
+    int ignore ATTRIBUTE_UNUSED;
+{
+  unsigned char syntax[129];
+  char *name;
+  char *p;
+  char c;
+  int suffixcode = -1;
+  int opcode,subopcode;
+  int i;
+  int class = 0;
+  int name_len;
+  struct arc_opcode *ext_op;
+
+  segT old_sec;
+  int old_subsec;
+
+  name = input_line_pointer;
+  c = get_symbol_end ();
+  name = xstrdup(name);
+  if (NULL == name)
+    {
+    ignore_rest_of_line();
+    return;
+    }
+  strcpy(syntax,name);
+  name_len = strlen(name);
+
+  /* just after name is now '\0' */
+  p = input_line_pointer;
+  *p = c;
+
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer != ',')
     {
-      as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
+      as_bad ("expected comma after operand name");
       ignore_rest_of_line ();
       return;
     }
-  size = temp;
-  *p = 0;
-  symbolP = symbol_find_or_make (name);
-  *p = c;
-  if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
+
+  input_line_pointer++;		/* skip ',' */
+  opcode = get_absolute_expression ();
+
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer != ',')
     {
-      as_bad (_("ignoring attempt to re-define symbol"));
+      as_bad ("expected comma after opcode");
       ignore_rest_of_line ();
       return;
     }
-  if (S_GET_VALUE (symbolP) != 0)
+
+  input_line_pointer++;		/* skip ',' */
+  subopcode = get_absolute_expression ();
+
+  if(subopcode < 0)
     {
-      if (S_GET_VALUE (symbolP) != size)
-	{
-	  as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
-		   S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
-	}
+    as_bad ("negative subopcode %d",subopcode);
+    ignore_rest_of_line();
+    return;
     }
-  assert (symbol_get_frag (symbolP) == &zero_address_frag);
+
+  if(subopcode)
+    {
+    if(3 != opcode)
+      {
+        as_bad ("subcode value found when opcode not equal 0x03");
+        ignore_rest_of_line();
+        return;
+      }
+    else
+      {
+      if (subopcode < 0x09 || subopcode == 0x3f)
+        {
+          as_bad ("invalid subopcode %d", subopcode);
+          ignore_rest_of_line();
+          return;
+        }
+      }
+    }
+
+  SKIP_WHITESPACE ();
+
   if (*input_line_pointer != ',')
     {
-      as_bad (_("expected comma after common length"));
+      as_bad ("expected comma after subopcode");
       ignore_rest_of_line ();
       return;
     }
-  input_line_pointer++;
+
+  input_line_pointer++;         /* skip ',' */
+
+  for(i = 0; i < (int) MAXSUFFIXCLASS; i++)
+    {
+    if(!strncmp(suffixclass[i].name,input_line_pointer, suffixclass[i].len))
+      {
+      suffixcode = i;
+      input_line_pointer += suffixclass[i].len;
+      break;
+      }
+    }
+
+  if(-1 == suffixcode)
+    {
+      as_bad ("invalid suffix class");
+      ignore_rest_of_line ();
+      return;
+    }
+
   SKIP_WHITESPACE ();
-  if (*input_line_pointer != '"')
+
+  if (*input_line_pointer != ',')
     {
-      temp = get_absolute_expression ();
-      if (temp < 0)
-	{
-	  temp = 0;
-	  as_warn (_("Common alignment negative; 0 assumed"));
-	}
-      if (S_IS_LOCAL(symbolP))
-	{
-	  segT old_sec;
-	  int old_subsec;
-	  char *p;
-	  int align;
-
-	  old_sec = now_seg;
-	  old_subsec = now_subseg;
-	  align = temp;
-	  record_alignment (bss_section, align);
-	  subseg_set (bss_section, 0);
-	  if (align)
-	    frag_align (align, 0, 0);
-	  if (S_GET_SEGMENT (symbolP) == bss_section)
-	    symbol_get_frag (symbolP)->fr_symbol = 0;
-	  symbol_set_frag (symbolP, frag_now);
-	  p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
-			(offsetT) size, (char *) 0);
-	  *p = 0;
-	  S_SET_SEGMENT (symbolP, bss_section);
-	  S_CLEAR_EXTERNAL (symbolP);
-	  subseg_set (old_sec, old_subsec);
-	}
-      else
-	{
-	allocate_common:
-	  S_SET_VALUE (symbolP, (valueT) size);
-	  S_SET_ALIGN (symbolP, temp);
-	  S_SET_EXTERNAL (symbolP);
-	  S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
-	}
+      as_bad ("expected comma after suffix class");
+      ignore_rest_of_line ();
+      return;
     }
-  else
+
+  input_line_pointer++;         /* skip ',' */
+
+  for(i = 0; i < (int) MAXSYNTAXCLASS; i++)
     {
-      input_line_pointer++;
-      /* ??? Some say data, some say bss.  */
-      if (strncmp (input_line_pointer, ".bss\"", 5)
-	  && strncmp (input_line_pointer, ".data\"", 6))
-	{
-	  input_line_pointer--;
-	  goto bad_common_segment;
-	}
-      while (*input_line_pointer++ != '"')
-	;
-      goto allocate_common;
+    if(!strncmp(syntaxclass[i].name,input_line_pointer, syntaxclass[i].len))
+      {
+      class = syntaxclass[i].class;
+      input_line_pointer += syntaxclass[i].len;
+      break;
+      }
     }
-  demand_empty_rest_of_line ();
-  return;
 
-  {
-  bad_common_segment:
-    p = input_line_pointer;
-    while (*p && *p != '\n')
-      p++;
-    c = *p;
-    *p = '\0';
-    as_bad (_("bad .common segment %s"), input_line_pointer + 1);
-    *p = c;
-    input_line_pointer = p;
+  if(0 == (SYNTAX_VALID & class))
+    {
+      as_bad ("invalid syntax class");
+      ignore_rest_of_line ();
+      return;
+    }
+
+  if ((0x3 == opcode) & (class &  SYNTAX_3OP))
+    {
+      as_bad ("opcode 0x3 and SYNTAX_3OP invalid");
+      ignore_rest_of_line ();
+      return;
+    }
+
+  switch (suffixcode)
+   {
+   case 0:
+    strcat(syntax,"%.q%.f ");
+    break;
+   case 1:
+    strcat(syntax,"%.f ");
+    break;
+   case 2:
+    strcat(syntax,"%.q ");
+    break;
+   case 3:
+    strcat(syntax," ");
+    break;
+   default:
+    as_bad("unknown suffix class");
+    ignore_rest_of_line();
+    return;
+    break;
+   };
+
+  strcat(syntax,((opcode == 0x3) ? "%a,%b" : ((class & SYNTAX_3OP) ? "%a,%b,%c" : "%b,%c")));
+  if(suffixcode < 2)
+    strcat(syntax,"%F");
+  strcat(syntax,"%S%L");
+
+  ext_op = (struct arc_opcode *) xmalloc(sizeof(struct arc_opcode));
+  if(NULL == ext_op)
+    {
     ignore_rest_of_line ();
     return;
-  }
+    }
+
+  ext_op->syntax = xstrdup(syntax);
+  if (NULL == ext_op->syntax)
+    {
+    ignore_rest_of_line ();
+    return;
+    }
+
+  ext_op->mask  = I(-1) | ((0x3 == opcode) ? C(-1) : 0 );
+  ext_op->value = I(opcode) | ((0x3 == opcode) ? C(subopcode) : 0 );
+  ext_op->flags = class;
+  ext_op->next_asm = arc_ext_opcodes;
+  ext_op->next_dis = arc_ext_opcodes;
+  arc_ext_opcodes = ext_op;
+
+/* ok, now that we know what this inst is, put a description in
+  the arc extension section of the output file */
+
+  old_sec    = now_seg;
+  old_subsec = now_subseg;
+
+  arc_set_ext_seg();
+
+  p = frag_more(1);
+  *p = 5 + name_len +1;
+  p = frag_more(1);
+  *p = EXT_INSTRUCTION;
+  p = frag_more(1);
+  *p = opcode;
+  p = frag_more(1);
+  *p = subopcode;
+  p = frag_more(1);
+  *p = (class & (OP1_MUST_BE_IMM | OP1_IMM_IMPLIED) ? IGNORE_FIRST_OPD : 0);
+  p = frag_more(name_len);
+  strncpy(p,syntax,name_len);
+  p = frag_more(1);
+  *p = '\0';
+
+  subseg_set (old_sec, old_subsec);
+
+  demand_empty_rest_of_line();
 }
 
-/* Select the cpu we're assembling for.  */
+int
+arc_set_ext_seg()
+{
+  if (!arcext_section)
+    {
+      arcext_section = subseg_new (".arcextmap", 0);
+      bfd_set_section_flags (stdoutput, arcext_section,
+                             SEC_READONLY | SEC_HAS_CONTENTS);
+    }
+  else
+    subseg_set (arcext_section, 0);
+  return 1;
+}
 
 static void
-arc_cpu (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+arc_common (localScope)
+     int localScope;
 {
-  int mach;
+  char *name;
   char c;
-  char *cpu;
+  char *p;
+  int  align, size;
+  symbolS *symbolP;
 
-  /* If an instruction has already been seen, it's too late.  */
-  if (cpu_tables_init_p)
+  name = input_line_pointer;
+  c = get_symbol_end ();
+  /* just after name is now '\0' */
+  p = input_line_pointer;
+  *p = c;
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer != ',')
     {
-      as_bad (_(".cpu command must appear before any instructions"));
+      as_bad ("expected comma after symbol name");
       ignore_rest_of_line ();
       return;
     }
 
-  cpu = input_line_pointer;
-  c = get_symbol_end ();
-  mach = arc_get_mach (cpu);
-  *input_line_pointer = c;
-  if (mach == -1)
-    goto bad_cpu;
+  input_line_pointer++;		/* skip ',' */
+  size = get_absolute_expression ();
 
-  demand_empty_rest_of_line ();
+  if (size < 0)
+    {
+      as_bad ("negative symbol length");
+      ignore_rest_of_line ();
+      return;
+    }
 
-  /* The cpu may have been selected on the command line.
-     The choices must match.  */
-  /* ??? This was a command line option early on.  It's gone now, but
-     leave this in.  */
-  if (mach_type_specified_p && mach != arc_mach_type)
-    as_bad (_(".cpu conflicts with previous value"));
+  *p = 0;
+  symbolP = symbol_find_or_make (name);
+  *p = c;
+
+  if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
+    {
+      as_bad ("ignoring attempt to re-define symbol");
+      ignore_rest_of_line ();
+      return;
+    }
+  if ( ((int) S_GET_VALUE (symbolP) != 0) \
+       && ((int) S_GET_VALUE (symbolP) != size) )
+    {
+      as_warn ("length of symbol \"%s\" already %ld, ignoring %d",
+	       S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
+    }
+  assert (symbolP->sy_frag == &zero_address_frag);
+
+
+  /* Now parse the alignment field.  This field is optional for
+     local and global symbols. Default alignment is zero.  */
+  if (*input_line_pointer == ',')
+    {
+      input_line_pointer++;
+      align = get_absolute_expression ();
+      if (align < 0)
+	{
+	  align = 0;
+	  as_warn ("assuming symbol alignment of zero");
+	}
+    }
   else
+    align = 0;
+
+  if (localScope != 0)
     {
-      arc_mach_type = mach;
-      mach_type_specified_p = 1;
-      if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
-	as_warn (_("could not set architecture and machine"));
+      segT old_sec;
+      int old_subsec;
+      char *pfrag;
+
+      old_sec    = now_seg;
+      old_subsec = now_subseg;
+      record_alignment (bss_section, align);
+      subseg_set (bss_section, 0);  /* ??? subseg_set (bss_section, 1); ??? */
+
+      if (align)
+	frag_align (align, 0, 0); /* do alignment */
+
+      /* detach from old frag */
+      if (S_GET_SEGMENT (symbolP) == bss_section)
+	symbolP->sy_frag->fr_symbol = NULL;
+
+      symbolP->sy_frag = frag_now;
+      pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
+		        (offsetT) size, (char *) 0);
+      *pfrag = 0;
+
+      S_SET_SIZE       (symbolP, size);
+      S_SET_SEGMENT    (symbolP, bss_section);
+      S_CLEAR_EXTERNAL (symbolP);
+      symbolP->local = 1;
+      subseg_set (old_sec, old_subsec);
+    }
+  else
+    {
+      S_SET_VALUE    (symbolP, (valueT) size);
+      S_SET_ALIGN    (symbolP, align);
+      S_SET_EXTERNAL (symbolP);
+      S_SET_SEGMENT  (symbolP, bfd_com_section_ptr);
     }
-  return;
 
- bad_cpu:
-  as_bad (_("bad .cpu op"));
-  ignore_rest_of_line ();
+  symbolP->bsym->flags |= BSF_OBJECT;
+
+  demand_empty_rest_of_line ();
+  return;
 }
 
-#if 0
-/* The .rename pseudo-op.  This is used by gcc to implement
-   -mmangle-cpu-libgcc.  */
+
+
+/* Select the cpu we're assembling for.  */
 
 static void
-arc_rename (ignore)
-     int ignore;
+arc_option (ignore)
+    int ignore ATTRIBUTE_UNUSED;
 {
-  char *name,*new;
+  int mach;
   char c;
-  symbolS *sym;
-  int len;
+  char *cpu;
 
-  name = input_line_pointer;
+  cpu = input_line_pointer;
   c = get_symbol_end ();
-  sym = symbol_find_or_make (name);
+  mach = arc_get_mach (cpu);
   *input_line_pointer = c;
 
-  if (*input_line_pointer != ',')
+  /* If an instruction has already been seen, it's too late.  */
+  if (cpu_tables_init_p)
     {
-      as_bad (_("missing rename string"));
+      as_bad ("\".option\" directive must appear before any instructions");
       ignore_rest_of_line ();
       return;
     }
-  ++input_line_pointer;
-  SKIP_WHITESPACE ();
 
-  name = input_line_pointer;
-  c = get_symbol_end ();
-  if (*name == '\0')
+  if (mach == -1)
+    goto bad_cpu;
+
+  if (mach_type_specified_p && mach != arc_mach_type)
     {
-      *input_line_pointer = c;
-      as_bad (_("invalid symbol to rename to"));
+      as_bad ("\".option\" directive conflicts with initial definition");
       ignore_rest_of_line ();
       return;
     }
-  new = (char *) xmalloc (strlen (name) + 1);
-  strcpy (new, name);
-  *input_line_pointer = c;
-  symbol_get_tc (sym)->real_name = new;
-
+  else
+    {
+      /* The cpu may have been selected on the command line.  */
+      if (mach != arc_mach_type)
+	as_warn ("\".option\" directive overrides command-line (default) value");
+      arc_mach_type = mach;
+      if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
+	as_fatal ("could not set architecture and machine");
+      mach_type_specified_p = 1;
+    }
   demand_empty_rest_of_line ();
+  return;
+
+ bad_cpu:
+  as_bad ("invalid identifier for \".option\"");
+  ignore_rest_of_line ();
 }
-#endif
+
 
 /* Turn a string in input_line_pointer into a floating point constant of type
    type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
    emitted is stored in *sizeP.
    An error message is returned, or NULL on OK.  */
 
-/* Equal to MAX_PRECISION in atof-ieee.c */
+/* Equal to MAX_PRECISION in atof-ieee.c  */
 #define MAX_LITTLENUMS 6
 
 char *
 md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
+  char type;
+  char *litP;
+  int *sizeP;
 {
   int prec;
   LITTLENUM_TYPE words[MAX_LITTLENUMS];
@@ -1006,7 +1565,7 @@ md_atof (type, litP, sizeP)
 
     default:
       *sizeP = 0;
-      return _("bad call to md_atof");
+      return "bad call to md_atof";
     }
 
   t = atof_ieee (input_line_pointer, type, words);
@@ -1037,7 +1596,7 @@ md_number_to_chars (buf, val, n)
     number_to_chars_littleendian (buf, val, n);
 }
 
-/* Round up a section size to the appropriate boundary.  */
+/* Round up a section size to the appropriate boundary. */
 
 valueT
 md_section_align (segment, size)
@@ -1056,7 +1615,8 @@ md_estimate_size_before_relax (fragp, seg)
      fragS *fragp ATTRIBUTE_UNUSED;
      asection *seg ATTRIBUTE_UNUSED;
 {
-  abort ();
+  as_fatal (_("md_estimate_size_before_relax\n"));
+  return 1;
 }
 
 /* Convert a machine dependent frag.  We never generate these.  */
@@ -1067,7 +1627,41 @@ md_convert_frag (abfd, sec, fragp)
      asection *sec ATTRIBUTE_UNUSED;
      fragS *fragp ATTRIBUTE_UNUSED;
 {
-  abort ();
+  as_fatal (_("md_convert_frag\n"));
+}
+
+void
+arc_code_symbol(expressionP)
+     expressionS *expressionP;
+{
+  if (expressionP->X_op == O_symbol && expressionP->X_add_number == 0
+	  /* I think this test is unnecessary but just as a sanity check... */
+    && expressionP->X_op_symbol == NULL)
+    {
+    expressionS two;
+    expressionP->X_op = O_right_shift;
+    two.X_op = O_constant;
+    two.X_add_symbol = two.X_op_symbol = NULL;
+    two.X_add_number = 2;
+    expressionP->X_op_symbol = make_expr_symbol (&two);
+    }
+      /* allow %st(sym1-sym2) */
+  else if (expressionP->X_op == O_subtract && expressionP->X_add_symbol != NULL
+       && expressionP->X_op_symbol != NULL && expressionP->X_add_number == 0)
+    {
+    expressionS two;
+    expressionP->X_add_symbol = make_expr_symbol (expressionP);
+    expressionP->X_op = O_right_shift;
+    two.X_op = O_constant;
+    two.X_add_symbol = two.X_op_symbol = NULL;
+    two.X_add_number = 2;
+    expressionP->X_op_symbol = make_expr_symbol (&two);
+    }
+  else
+    {
+    as_bad ("expression too complex code symbol");
+    return;
+    }
 }
 
 /* Parse an operand that is machine-specific.
@@ -1078,58 +1672,56 @@ md_convert_frag (abfd, sec, fragp)
 
    ??? We can't create new expression types so we map the %-op's onto the
    existing syntax.  This means that the user could use the chosen syntax
-   to achieve the same effect.  Perhaps put a special cookie in X_add_number
-   to mark the expression as special.  */
+   to achieve the same effect. */
 
-void
+void 
 md_operand (expressionP)
      expressionS *expressionP;
 {
   char *p = input_line_pointer;
 
-  if (*p == '%' && strncmp (p, "%st(", 4) == 0)
-    {
+  if (*p == '%')
+    if(strncmp (p, "%st(", 4) == 0)
+      {
       input_line_pointer += 4;
       expression (expressionP);
       if (*input_line_pointer != ')')
 	{
-	  as_bad (_("missing ')' in %-op"));
+	  as_bad ("missing ')' in %%-op");
 	  return;
 	}
       ++input_line_pointer;
-      if (expressionP->X_op == O_symbol
-	  && expressionP->X_add_number == 0
-	  /* I think this test is unnecessary but just as a sanity check...  */
-	  && expressionP->X_op_symbol == NULL)
-	{
-	  expressionS two;
-
-	  expressionP->X_op = O_right_shift;
-	  two.X_op = O_constant;
-	  two.X_add_symbol = two.X_op_symbol = NULL;
-	  two.X_add_number = 2;
-	  expressionP->X_op_symbol = make_expr_symbol (&two);
-	}
-      /* allow %st(sym1-sym2) */
-      else if (expressionP->X_op == O_subtract
-	       && expressionP->X_add_symbol != NULL
-	       && expressionP->X_op_symbol != NULL
-	       && expressionP->X_add_number == 0)
-	{
-	  expressionS two;
-
-	  expressionP->X_add_symbol = make_expr_symbol (expressionP);
-	  expressionP->X_op = O_right_shift;
-	  two.X_op = O_constant;
-	  two.X_add_symbol = two.X_op_symbol = NULL;
-	  two.X_add_number = 2;
-	  expressionP->X_op_symbol = make_expr_symbol (&two);
-	}
-      else
-	{
-	  as_bad (_("expression too complex for %%st"));
-	  return;
-	}
+      arc_code_symbol(expressionP);
+      }
+  else
+    {       /* it could be a register */
+    int i,l;
+    struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+    p++;
+
+    while (ext_oper)
+      {
+      l = strlen(ext_oper->operand.name);
+      if(!strncmp(p,ext_oper->operand.name,l) && !isalnum(*(p + l)))
+        {
+        input_line_pointer += l + 1;
+        expressionP->X_op = O_register;
+        expressionP->X_add_number = (int) &ext_oper->operand;
+        return;
+        }
+      ext_oper = ext_oper->next;
+      }
+    for (i = 0; i < arc_reg_names_count; i++)
+      {
+      l = strlen(arc_reg_names[i].name);
+      if(!strncmp(p,arc_reg_names[i].name,l) && !isalnum(*(p + l)))
+        {
+        input_line_pointer += l + 1;
+        expressionP->X_op = O_register;
+        expressionP->X_add_number = (int)  &arc_reg_names[i];
+        break;
+        }
+      }
     }
 }
 
@@ -1153,10 +1745,24 @@ md_undefined_symbol (name)
 
 void
 arc_parse_cons_expression (exp, nbytes)
-     expressionS *exp;
-     int nbytes ATTRIBUTE_UNUSED;
+  expressionS *exp;
+  unsigned int nbytes ATTRIBUTE_UNUSED;
 {
+  char *p = input_line_pointer;
+  int code_symbol_fix = 0;
+
+  for (;! is_end_of_line[(unsigned char) *p]; p++)
+      if (*p == '@' && !strncmp(p,"@h30",4))
+	  {
+	      code_symbol_fix = 1;
+	      strcpy(p,";   ");
+	  }
   expr (0, exp);
+  if (code_symbol_fix)
+      {
+	  arc_code_symbol(exp);
+	  input_line_pointer = p;
+      }
 }
 
 /* Record a fixup for a cons expression.  */
@@ -1191,7 +1797,7 @@ arc_cons_fix_new (frag, where, nbytes, exp)
 /* The location from which a PC relative jump should be calculated,
    given a PC relative reloc.  */
 
-long
+long 
 md_pcrel_from (fixP)
      fixS *fixP;
 {
@@ -1241,13 +1847,13 @@ get_arc_exp_reloc_type (data_p, default_type, exp, expnew)
 
   if (exp->X_op == O_right_shift
       && exp->X_op_symbol != NULL
-      && symbol_constant_p (exp->X_op_symbol)
-      && S_GET_VALUE (exp->X_op_symbol) == 2
+      && exp->X_op_symbol->sy_value.X_op == O_constant
+      && exp->X_op_symbol->sy_value.X_add_number == 2
       && exp->X_add_number == 0)
     {
       if (exp->X_add_symbol != NULL
-	  && (symbol_constant_p (exp->X_add_symbol)
-	      || symbol_equated_p (exp->X_add_symbol)))
+	  && (exp->X_add_symbol->sy_value.X_op == O_constant
+	      || exp->X_add_symbol->sy_value.X_op == O_symbol))
 	{
 	  *expnew = *exp;
 	  expnew->X_op = O_symbol;
@@ -1255,10 +1861,9 @@ get_arc_exp_reloc_type (data_p, default_type, exp, expnew)
 	  return data_p ? BFD_RELOC_ARC_B26 : arc_operand_map['J'];
 	}
       else if (exp->X_add_symbol != NULL
-	       && (symbol_get_value_expression (exp->X_add_symbol)->X_op
-		   == O_subtract))
+	       && exp->X_add_symbol->sy_value.X_op == O_subtract)
 	{
-	  *expnew = *symbol_get_value_expression (exp->X_add_symbol);
+	  *expnew = exp->X_add_symbol->sy_value;
 	  return data_p ? BFD_RELOC_ARC_B26 : arc_operand_map['J'];
 	}
     }
@@ -1322,7 +1927,7 @@ md_apply_fix3 (fixP, valueP, seg)
 	    {
 	      /* We can't actually support subtracting a symbol.  */
 	      as_bad_where (fixP->fx_file, fixP->fx_line,
-			    _("expression too complex"));
+			    "expression too complex");
 	    }
 	}
     }
@@ -1371,14 +1976,14 @@ md_apply_fix3 (fixP, valueP, seg)
 		  && operand->shift == 7);
 	  fixP->fx_r_type = BFD_RELOC_ARC_B22_PCREL;
 	}
-      else if (0 && operand->fmt == 'J')
+      else if (operand->fmt == 'J')
 	{
 	  assert ((operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH) != 0
 		  && operand->bits == 24
 		  && operand->shift == 32);
 	  fixP->fx_r_type = BFD_RELOC_ARC_B26;
 	}
-      else if (0 && operand->fmt == 'L')
+      else if (operand->fmt == 'L')
 	{
 	  assert ((operand->flags & ARC_OPERAND_LIMM) != 0
 		  && operand->bits == 32
@@ -1388,7 +1993,7 @@ md_apply_fix3 (fixP, valueP, seg)
       else
 	{
 	  as_bad_where (fixP->fx_file, fixP->fx_line,
-			_("unresolved expression that must be resolved"));
+			"unresolved expression that must be resolved");
 	  fixP->fx_done = 1;
 	  return 1;
 	}
@@ -1446,38 +2051,23 @@ tc_gen_reloc (section, fixP)
 
   reloc = (arelent *) xmalloc (sizeof (arelent));
 
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
-  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
+  reloc->sym_ptr_ptr = &fixP->fx_addsy->bsym;
   reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
   if (reloc->howto == (reloc_howto_type *) NULL)
     {
       as_bad_where (fixP->fx_file, fixP->fx_line,
-		    _("internal error: can't export reloc type %d (`%s')"),
+		    "internal error: can't export reloc type %d (`%s')",
 		    fixP->fx_r_type, bfd_get_reloc_code_name (fixP->fx_r_type));
       return NULL;
     }
 
   assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
 
-  reloc->addend = fixP->fx_addnumber;
+/* set addend to account for PC being advanced one insn before the target
+   address is computed, drop fx_addnumber as it is handled elsewhere  mlm */
 
-  return reloc;
-}
-
-/* Frobbers.  */
-
-#if 0
-/* Set the real name if the .rename pseudo-op was used.
-   Return 1 if the symbol should not be included in the symbol table.  */
+  reloc->addend = ( fixP->fx_pcrel ? -4 : 0 );
 
-int
-arc_frob_symbol (sym)
-     symbolS *sym;
-{
-  if (symbol_get_tc (sym)->real_name != (char *) NULL)
-    S_SET_NAME (sym, symbol_get_tc (sym)->real_name);
-
-  return 0;
+  return reloc;
 }
-#endif
diff --git a/gas/config/tc-arc.h b/gas/config/tc-arc.h
index 091c723..d8da4ec 100644
--- a/gas/config/tc-arc.h
+++ b/gas/config/tc-arc.h
@@ -1,5 +1,5 @@
 /* tc-arc.h - Macros and type defines for the ARC.
-   Copyright (C) 1994, 1995, 1997, 1999, 2000 Free Software Foundation, Inc.
+   Copyright (C) 1994, 1995, 1997 Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
 
    This file is part of GAS, the GNU Assembler.
@@ -17,7 +17,7 @@
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   02111-1307, USA. */
 
 #define TC_ARC 1
 
@@ -27,6 +27,9 @@
 
 #define TARGET_ARCH bfd_arch_arc
 
+#define DIFF_EXPR_OK
+#define REGISTER_PREFIX '%'
+
 #ifdef LITTLE_ENDIAN
 #undef LITTLE_ENDIAN
 #endif
@@ -36,6 +39,7 @@
 #endif
 
 #define LITTLE_ENDIAN   1234
+
 #define BIG_ENDIAN      4321
 
 /* The endianness of the target format may change based on command
@@ -62,18 +66,3 @@ arc_parse_cons_expression (EXP, NBYTES)
 extern void arc_cons_fix_new ();
 #define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \
 arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP)
-
-#if 0
-/* Extra stuff that we need to keep track of for each symbol.  */
-struct arc_tc_sy
-{
-  /* The real name, if the symbol was renamed.  */
-  char *real_name;
-};
-
-#define TC_SYMFIELD_TYPE struct arc_tc_sy
-
-/* Finish up the symbol.  */
-extern int arc_frob_symbol PARAMS ((symbolS *));
-#define tc_frob_symbol(sym, punt) punt = arc_frob_symbol (sym)
-#endif
diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index ac10774..60761a4 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -17,6 +17,7 @@ asconfig.texi: $(CONFIG).texi
 
 CPU_DOCS = \
 	c-a29k.texi \
+	c-arc.texi \
 	c-arm.texi \
 	c-d10v.texi \
 	c-h8300.texi \
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index 987ff4d..5f9b258 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -127,6 +127,7 @@ info_TEXINFOS = as.texinfo gasp.texi
 
 CPU_DOCS = \
 	c-a29k.texi \
+	c-arc.texi \
 	c-arm.texi \
 	c-d10v.texi \
 	c-h8300.texi \
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index bc0928a..1a706e9 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -208,7 +208,8 @@ Here is a brief summary of how to invoke @code{@value{AS}}.  For details,
 @c am29k has no machine-dependent assembler options
 @end ifset
 @ifset ARC
- [ -mbig-endian | -mlittle-endian ]
+ [ -marc[5|6|7|8] ]
+ [ -EB | -EL ]
 @end ifset
 @ifset ARM
  [ -m[arm]1 | -m[arm]2 | -m[arm]250 | -m[arm]3 | -m[arm]6 | -m[arm]60 |
@@ -416,17 +417,10 @@ The following options are available when @value{AS} is configured for
 an ARC processor.
 
 @table @code
-
-@cindex ARC endianness
-@cindex endianness, ARC
-@cindex big endian output, ARC
-@item -mbig-endian
-Generate ``big endian'' format output.
-
-@cindex little endian output, ARC
-@item -mlittle-endian
-Generate ``little endian'' format output.
-
+@item -marc[5|6|7|8]
+This option selects the core processor variant.
+@item -EB | -EL
+Select either big-endian (-EB) or little-endian (-EL) output.
 @end table
 @end ifset
 
@@ -5302,80 +5296,7 @@ subject, see the hardware manufacturer's manual.
 @c in both conditional blocks.
 
 @ifset ARC
-@ifset GENERIC
-@page
-@node ARC-Dependent
-@chapter ARC Dependent Features
-@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter ARC Dependent Features
-@end ifclear
-
-@cindex ARC support
-@menu
-* ARC-Opts::                    Options
-* ARC-Float::                   Floating Point
-* ARC-Directives::              Sparc Machine Directives
-@end menu
-
-@node ARC-Opts
-@section Options
-
-@cindex options for ARC
-@cindex ARC options
-@cindex architectures, ARC
-@cindex ARC architectures
-The ARC chip family includes several successive levels (or other
-variants) of chip, using the same core instruction set, but including
-a few additional instructions at each level.
-
-By default, @code{@value{AS}} assumes the core instruction set (ARC
-base).  The @code{.cpu} pseudo-op is intended to be used to select
-the variant.
-
-@table @code
-@cindex @code{-mbig-endian} option (ARC)
-@cindex @code{-mlittle-endian} option (ARC)
-@cindex ARC big-endian output
-@cindex ARC little-endian output
-@cindex big-endian output, ARC
-@cindex little-endian output, ARC
-@item -mbig-endian
-@itemx -mlittle-endian
-Any @sc{arc} configuration of @code{@value{AS}} can select big-endian or
-little-endian output at run time (unlike most other @sc{gnu} development
-tools, which must be configured for one or the other).  Use
-@samp{-mbig-endian} to select big-endian output, and @samp{-mlittle-endian}
-for little-endian.
-@end table
-
-@node ARC-Float
-@section Floating Point
-
-@cindex floating point, ARC (@sc{ieee})
-@cindex ARC floating point (@sc{ieee})
-The ARC cpu family currently does not have hardware floating point
-support.  Software floating point support is provided by @code{GCC}
-and uses @sc{ieee} floating-point numbers.
-
-@node ARC-Directives
-@section ARC Machine Directives
-
-@cindex ARC machine directives
-@cindex machine directives, ARC
-The ARC version of @code{@value{AS}} supports the following additional
-machine directives:
-
-@table @code
-@item .cpu
-@cindex @code{cpu} directive, SPARC
-This must be followed by the desired cpu.
-The ARC is intended to be customizable, @code{.cpu} is used to
-select the desired variant [though currently there are none].
-
-@end table
-
+@include c-arc.texi
 @end ifset
 
 @ifset A29K
diff --git a/gas/po/gas.pot b/gas/po/gas.pot
index 423ad9f..4428b64 100644
--- a/gas/po/gas.pot
+++ b/gas/po/gas.pot
@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2000-12-04 16:54-0800\n"
+"POT-Creation-Date: 2001-01-11 12:04-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -439,11 +439,11 @@ msgstr ""
 msgid "Symbol `%s' can not be both weak and common"
 msgstr ""
 
-#: config/obj-aout.c:255 config/obj-coff.c:1981
+#: config/obj-aout.c:255 config/obj-coff.c:1982
 msgid "unresolved relocation"
 msgstr ""
 
-#: config/obj-aout.c:257 config/obj-coff.c:1983
+#: config/obj-aout.c:257 config/obj-coff.c:1984
 #, c-format
 msgid "bad relocation: symbol `%s' not in symbol table"
 msgstr ""
@@ -453,7 +453,7 @@ msgstr ""
 msgid "%s: bad type for weak symbol"
 msgstr ""
 
-#: config/obj-aout.c:458 config/obj-coff.c:2911 write.c:1849
+#: config/obj-aout.c:458 config/obj-coff.c:2913 write.c:1868
 #, c-format
 msgid "%s: global symbols not supported in common sections"
 msgstr ""
@@ -482,7 +482,7 @@ msgstr ""
 msgid "Line numbers must be positive integers\n"
 msgstr ""
 
-#: config/obj-coff.c:484 config/obj-coff.c:2326
+#: config/obj-coff.c:484 config/obj-coff.c:2328
 msgid ".ln pseudo-op inside .def/.endef: ignored."
 msgstr ""
 
@@ -494,11 +494,11 @@ msgstr ""
 msgid ".loc pseudo-op inside .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:622 config/obj-coff.c:2383
+#: config/obj-coff.c:622 config/obj-coff.c:2385
 msgid ".def pseudo-op used inside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:668 config/obj-coff.c:2435
+#: config/obj-coff.c:668 config/obj-coff.c:2437
 msgid ".endef pseudo-op used outside of .def/.endef: ignored."
 msgstr ""
 
@@ -507,49 +507,49 @@ msgstr ""
 msgid "`%s' symbol without preceding function"
 msgstr ""
 
-#: config/obj-coff.c:793 config/obj-coff.c:2510
+#: config/obj-coff.c:793 config/obj-coff.c:2512
 #, c-format
 msgid "unexpected storage class %d"
 msgstr ""
 
-#: config/obj-coff.c:906 config/obj-coff.c:2617
+#: config/obj-coff.c:906 config/obj-coff.c:2619
 msgid ".dim pseudo-op used outside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:926 config/obj-coff.c:2637
+#: config/obj-coff.c:926 config/obj-coff.c:2639
 msgid "badly formed .dim directive ignored"
 msgstr ""
 
-#: config/obj-coff.c:977 config/obj-coff.c:2700
+#: config/obj-coff.c:977 config/obj-coff.c:2702
 msgid ".size pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:993 config/obj-coff.c:2716
+#: config/obj-coff.c:993 config/obj-coff.c:2718
 msgid ".scl pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1011 config/obj-coff.c:2734
+#: config/obj-coff.c:1011 config/obj-coff.c:2736
 msgid ".tag pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1030 config/obj-coff.c:2752
+#: config/obj-coff.c:1030 config/obj-coff.c:2754
 #, c-format
 msgid "tag not found for .tag %s"
 msgstr ""
 
-#: config/obj-coff.c:1045 config/obj-coff.c:2767
+#: config/obj-coff.c:1045 config/obj-coff.c:2769
 msgid ".type pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1067 config/obj-coff.c:2789
+#: config/obj-coff.c:1067 config/obj-coff.c:2791
 msgid ".val pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1207 config/obj-coff.c:2984
+#: config/obj-coff.c:1207 config/obj-coff.c:2986
 msgid "mismatched .eb"
 msgstr ""
 
-#: config/obj-coff.c:1225 config/obj-coff.c:3024
+#: config/obj-coff.c:1225 config/obj-coff.c:3026
 msgid "C_EFCN symbol out of scope"
 msgstr ""
 
@@ -561,12 +561,12 @@ msgstr ""
 msgid "unsupported section attribute '%c'"
 msgstr ""
 
-#: config/obj-coff.c:1452 config/obj-coff.c:3721 config/tc-ppc.c:3918
+#: config/obj-coff.c:1452 config/obj-coff.c:3726 config/tc-ppc.c:3925
 #, c-format
 msgid "unknown section attribute '%c'"
 msgstr ""
 
-#: config/obj-coff.c:1482 config/tc-ppc.c:3936 read.c:2524
+#: config/obj-coff.c:1482 config/tc-ppc.c:3943 read.c:2512
 #, c-format
 msgid "error setting flags for \"%s\": %s"
 msgstr ""
@@ -585,63 +585,63 @@ msgstr ""
 msgid "Out of step\n"
 msgstr ""
 
-#: config/obj-coff.c:2242
+#: config/obj-coff.c:2244
 msgid "bfd_coff_swap_scnhdr_out failed"
 msgstr ""
 
-#: config/obj-coff.c:2467
+#: config/obj-coff.c:2469
 msgid "`.bf' symbol without preceding function\n"
 msgstr ""
 
-#: config/obj-coff.c:3420 config/obj-ieee.c:507 output-file.c:52
+#: config/obj-coff.c:3422 config/obj-ieee.c:507 output-file.c:52
 #: output-file.c:119
 #, c-format
 msgid "FATAL: Can't create %s"
 msgstr ""
 
-#: config/obj-coff.c:3595
+#: config/obj-coff.c:3600
 #, c-format
 msgid "Can't close %s: %s"
 msgstr ""
 
-#: config/obj-coff.c:3629
+#: config/obj-coff.c:3634
 #, c-format
 msgid "Too many new sections; can't add \"%s\""
 msgstr ""
 
-#: config/obj-coff.c:4036 config/tc-m88k.c:1257 config/tc-sparc.c:3531
+#: config/obj-coff.c:4041 config/tc-m88k.c:1257 config/tc-sparc.c:3531
 msgid "Expected comma after name"
 msgstr ""
 
-#: config/obj-coff.c:4042 read.c:1968
+#: config/obj-coff.c:4047 read.c:1956
 msgid "Missing size expression"
 msgstr ""
 
-#: config/obj-coff.c:4048
+#: config/obj-coff.c:4053
 #, c-format
 msgid "lcomm length (%d.) <0! Ignored."
 msgstr ""
 
-#: config/obj-coff.c:4076 read.c:2202
+#: config/obj-coff.c:4081 read.c:2190
 #, c-format
 msgid "Symbol %s already defined"
 msgstr ""
 
-#: config/obj-coff.c:4170 config/tc-i960.c:3215
+#: config/obj-coff.c:4176 config/tc-i960.c:3215
 #, c-format
 msgid "No 'bal' entry point for leafproc %s"
 msgstr ""
 
-#: config/obj-coff.c:4249 write.c:2554
+#: config/obj-coff.c:4255 write.c:2575
 #, c-format
 msgid "Negative of non-absolute symbol %s"
 msgstr ""
 
-#: config/obj-coff.c:4270 write.c:2568
+#: config/obj-coff.c:4276 write.c:2589
 msgid "callj to difference of 2 symbols"
 msgstr ""
 
-#: config/obj-coff.c:4316
+#: config/obj-coff.c:4322
 #, c-format
 msgid "Can't emit reloc {- %s-seg symbol \"%s\"} @ file address %ld."
 msgstr ""
@@ -649,16 +649,16 @@ msgstr ""
 #. This is a COBR instruction.  They have only a 13-bit
 #. displacement and are only to be used for local branches:
 #. flag as error, don't generate relocation.
-#: config/obj-coff.c:4405 config/tc-i960.c:3235 write.c:2712
+#: config/obj-coff.c:4411 config/tc-i960.c:3235 write.c:2733
 msgid "can't use COBR format with external label"
 msgstr ""
 
-#: config/obj-coff.c:4484
+#: config/obj-coff.c:4490
 #, c-format
 msgid "Value of %ld too large for field of %d bytes at 0x%lx"
 msgstr ""
 
-#: config/obj-coff.c:4498 write.c:2802
+#: config/obj-coff.c:4504 write.c:2823
 #, c-format
 msgid "Signed .word overflow; switch may be too large; %ld at 0x%lx"
 msgstr ""
@@ -675,33 +675,31 @@ msgstr ""
 msgid "Expected comma after symbol-name"
 msgstr ""
 
-#: config/obj-elf.c:315 config/tc-arc.c:779 config/tc-sparc.c:3684
+#: config/obj-elf.c:315 config/tc-sparc.c:3684
 #, c-format
 msgid ".COMMon length (%d.) <0! Ignored."
 msgstr ""
 
-#: config/obj-elf.c:325 config/tc-alpha.c:4327 config/tc-sparc.c:3694
+#: config/obj-elf.c:325 config/tc-alpha.c:4335 config/tc-sparc.c:3694
 #: config/tc-v850.c:282
 msgid "Ignoring attempt to re-define symbol"
 msgstr ""
 
-#: config/obj-elf.c:333 config/tc-arc.c:797 config/tc-sparc.c:3702
-#: config/tc-v850.c:292
+#: config/obj-elf.c:333 config/tc-sparc.c:3702 config/tc-v850.c:292
 #, c-format
 msgid "Length of .comm \"%s\" is already %ld. Not changed to %d."
 msgstr ""
 
-#: config/obj-elf.c:356 config/tc-arc.c:816 config/tc-v850.c:319
+#: config/obj-elf.c:356 config/tc-v850.c:319
 msgid "Common alignment negative; 0 assumed"
 msgstr ""
 
-#: config/obj-elf.c:375 config/tc-m32r.c:1296 config/tc-ppc.c:1515
+#: config/obj-elf.c:375 config/tc-m32r.c:1286 config/tc-ppc.c:1518
 #: config/tc-v850.c:382
 msgid "Common alignment not a power of 2"
 msgstr ""
 
-#: config/obj-elf.c:438 config/tc-arc.c:875 config/tc-sparc.c:3826
-#: config/tc-v850.c:564
+#: config/obj-elf.c:438 config/tc-sparc.c:3826 config/tc-v850.c:564
 #, c-format
 msgid "bad .common segment %s"
 msgstr ""
@@ -979,17 +977,16 @@ msgid "Unknown segment type"
 msgstr ""
 
 #. Probably a memory allocation problem?  Give up now.
-#: config/tc-a29k.c:330 config/tc-hppa.c:1412 config/tc-mips.c:1028
-#: config/tc-mips.c:1070 config/tc-sparc.c:846
+#: config/tc-a29k.c:330 config/tc-hppa.c:1412 config/tc-mips.c:1030
+#: config/tc-mips.c:1072 config/tc-sparc.c:846
 msgid "Broken assembler.  No assembly attempted."
 msgstr ""
 
-#: config/tc-a29k.c:375 config/tc-arc.c:535 config/tc-avr.c:1124
-#: config/tc-d10v.c:532 config/tc-d30v.c:552 config/tc-h8300.c:296
-#: config/tc-h8500.c:294 config/tc-mcore.c:655 config/tc-mn10200.c:954
-#: config/tc-mn10300.c:1335 config/tc-ppc.c:1971 config/tc-sh.c:838
-#: config/tc-tic80.c:282 config/tc-v850.c:2076 config/tc-w65.c:248
-#: config/tc-z8k.c:336
+#: config/tc-a29k.c:375 config/tc-avr.c:1124 config/tc-d10v.c:532
+#: config/tc-d30v.c:552 config/tc-h8300.c:296 config/tc-h8500.c:294
+#: config/tc-mcore.c:655 config/tc-mn10200.c:954 config/tc-mn10300.c:1335
+#: config/tc-ppc.c:1974 config/tc-sh.c:838 config/tc-tic80.c:282
+#: config/tc-v850.c:2076 config/tc-w65.c:248 config/tc-z8k.c:336
 msgid "missing operand"
 msgstr ""
 
@@ -1090,405 +1087,287 @@ msgid ""
 "-H\t\t\tshow new symbol after hash truncation\n"
 msgstr ""
 
-#: config/tc-alpha.c:1301
+#: config/tc-alpha.c:1305
 #, c-format
 msgid "unhandled relocation type %s"
 msgstr ""
 
-#: config/tc-alpha.c:1314
+#: config/tc-alpha.c:1318
 msgid "non-absolute expression in constant field"
 msgstr ""
 
-#: config/tc-alpha.c:1328
+#: config/tc-alpha.c:1332
 #, c-format
 msgid "type %d reloc done?\n"
 msgstr ""
 
-#: config/tc-alpha.c:1379 config/tc-alpha.c:1386 config/tc-mips.c:7353
+#: config/tc-alpha.c:1383 config/tc-alpha.c:1390 config/tc-mips.c:7356
 msgid "Used $at without \".set noat\""
 msgstr ""
 
-#: config/tc-alpha.c:1564
+#: config/tc-alpha.c:1572
 #, c-format
 msgid "cannot represent `%s' relocation in object file"
 msgstr ""
 
-#: config/tc-alpha.c:1571
+#: config/tc-alpha.c:1579
 #, c-format
 msgid "internal error? cannot generate `%s' relocation"
 msgstr ""
 
-#: config/tc-alpha.c:1625
+#: config/tc-alpha.c:1633
 #, c-format
 msgid "frame reg expected, using $%d."
 msgstr ""
 
-#: config/tc-alpha.c:1750
+#: config/tc-alpha.c:1758
 #, c-format
 msgid "No !literal!%d was found"
 msgstr ""
 
 #. only support one relocation op per insn
-#: config/tc-alpha.c:1938
+#: config/tc-alpha.c:1946
 msgid "More than one relocation op per insn"
 msgstr ""
 
-#: config/tc-alpha.c:1955
+#: config/tc-alpha.c:1963
 msgid "No relocation operand"
 msgstr ""
 
-#: config/tc-alpha.c:1961
+#: config/tc-alpha.c:1969
 #, c-format
 msgid "No !sequence-number after !%s"
 msgstr ""
 
-#: config/tc-alpha.c:1974
+#: config/tc-alpha.c:1982
 #, c-format
 msgid "Unknown relocation operand: !%s"
 msgstr ""
 
-#: config/tc-alpha.c:1987
+#: config/tc-alpha.c:1995
 #, c-format
 msgid "Bad sequence number: !%s!%s"
 msgstr ""
 
-#: config/tc-alpha.c:2338
+#: config/tc-alpha.c:2346
 #, c-format
 msgid "operand out of range (%s not between %d and %d)"
 msgstr ""
 
-#: config/tc-alpha.c:2437 config/tc-arc.c:548 config/tc-d10v.c:621
-#: config/tc-d30v.c:640 config/tc-mn10200.c:1009 config/tc-mn10300.c:1406
-#: config/tc-ppc.c:1937 config/tc-ppc.c:2045 config/tc-ppc.c:2057
-#: config/tc-v850.c:1856 config/tc-v850.c:1879 config/tc-v850.c:2099
+#: config/tc-alpha.c:2445 config/tc-d10v.c:621 config/tc-d30v.c:640
+#: config/tc-mn10200.c:1009 config/tc-mn10300.c:1406 config/tc-ppc.c:1940
+#: config/tc-ppc.c:2048 config/tc-ppc.c:2060 config/tc-v850.c:1856
+#: config/tc-v850.c:1879 config/tc-v850.c:2099
 msgid "too many fixups"
 msgstr ""
 
-#: config/tc-alpha.c:2652 config/tc-alpha.c:2721
+#: config/tc-alpha.c:2660 config/tc-alpha.c:2729
 #, c-format
 msgid "inappropriate arguments for opcode `%s'"
 msgstr ""
 
-#: config/tc-alpha.c:2654 config/tc-alpha.c:2723
+#: config/tc-alpha.c:2662 config/tc-alpha.c:2731
 #, c-format
 msgid "opcode `%s' not supported for target %s"
 msgstr ""
 
-#: config/tc-alpha.c:2658 config/tc-alpha.c:2726 config/tc-avr.c:1090
+#: config/tc-alpha.c:2666 config/tc-alpha.c:2734 config/tc-avr.c:1090
 #, c-format
 msgid "unknown opcode `%s'"
 msgstr ""
 
-#: config/tc-alpha.c:2698 config/tc-alpha.c:2765 config/tc-alpha.c:3276
-#: config/tc-alpha.c:3336 config/tc-alpha.c:3388 config/tc-alpha.c:3463
-#: config/tc-alpha.c:3548 config/tc-alpha.c:3674 config/tc-alpha.c:3851
-#: config/tc-alpha.c:3908 config/tc-alpha.c:4018 config/tc-alpha.c:4125
-#: config/tc-alpha.c:4202
+#: config/tc-alpha.c:2706 config/tc-alpha.c:2773 config/tc-alpha.c:3284
+#: config/tc-alpha.c:3344 config/tc-alpha.c:3396 config/tc-alpha.c:3471
+#: config/tc-alpha.c:3556 config/tc-alpha.c:3682 config/tc-alpha.c:3859
+#: config/tc-alpha.c:3916 config/tc-alpha.c:4026 config/tc-alpha.c:4133
+#: config/tc-alpha.c:4210
 #, c-format
 msgid "Cannot use !%s!%d with %s"
 msgstr ""
 
-#: config/tc-alpha.c:2786
+#: config/tc-alpha.c:2794
 msgid "can not resolve expression"
 msgstr ""
 
-#: config/tc-alpha.c:2928 config/tc-alpha.c:3120
+#: config/tc-alpha.c:2936 config/tc-alpha.c:3128
 msgid "overflow in literal (.lita) table"
 msgstr ""
 
-#: config/tc-alpha.c:2935 config/tc-alpha.c:2958 config/tc-alpha.c:3133
-#: config/tc-alpha.c:3477 config/tc-alpha.c:3555 config/tc-alpha.c:3603
-#: config/tc-alpha.c:3703 config/tc-alpha.c:3928 config/tc-alpha.c:4040
+#: config/tc-alpha.c:2943 config/tc-alpha.c:2966 config/tc-alpha.c:3141
+#: config/tc-alpha.c:3485 config/tc-alpha.c:3563 config/tc-alpha.c:3611
+#: config/tc-alpha.c:3711 config/tc-alpha.c:3936 config/tc-alpha.c:4048
 msgid "macro requires $at register while noat in effect"
 msgstr ""
 
-#: config/tc-alpha.c:2937 config/tc-alpha.c:2960 config/tc-alpha.c:3135
+#: config/tc-alpha.c:2945 config/tc-alpha.c:2968 config/tc-alpha.c:3143
 msgid "macro requires $at while $at in use"
 msgstr ""
 
-#: config/tc-alpha.c:3082 expr.c:83 read.c:3176
+#: config/tc-alpha.c:3090 expr.c:83 read.c:3164
 msgid "bignum invalid; zero assumed"
 msgstr ""
 
-#: config/tc-alpha.c:3084 expr.c:85 read.c:3178 read.c:3511 read.c:4409
+#: config/tc-alpha.c:3092 expr.c:85 read.c:3166 read.c:3499 read.c:4397
 msgid "floating point number invalid; zero assumed"
 msgstr ""
 
-#: config/tc-alpha.c:3089
+#: config/tc-alpha.c:3097
 msgid "can't handle expression"
 msgstr ""
 
-#: config/tc-alpha.c:3126
+#: config/tc-alpha.c:3134
 msgid "overflow in literal (.lit8) table"
 msgstr ""
 
-#: config/tc-alpha.c:3298
+#: config/tc-alpha.c:3306
 #, c-format
 msgid "bad instruction format for lda !%s!%ld"
 msgstr ""
 
-#: config/tc-alpha.c:4298 config/tc-ppc.c:1464 config/tc-ppc.c:3682
-#: read.c:1381
+#: config/tc-alpha.c:4306 config/tc-ppc.c:1467 config/tc-ppc.c:3689
+#: read.c:1369
 #, c-format
 msgid ".COMMon length (%ld.) <0! Ignored."
 msgstr ""
 
-#: config/tc-alpha.c:4336 config/tc-alpha.c:4345 config/tc-ppc.c:3719
-#: read.c:1405
+#: config/tc-alpha.c:4344 config/tc-alpha.c:4353 config/tc-ppc.c:3726
+#: read.c:1393
 #, c-format
 msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
 
-#: config/tc-alpha.c:4447 ecoff.c:3087
+#: config/tc-alpha.c:4455 ecoff.c:3087
 msgid ".ent directive has no name"
 msgstr ""
 
-#: config/tc-alpha.c:4455
+#: config/tc-alpha.c:4463
 msgid "nested .ent directives"
 msgstr ""
 
-#: config/tc-alpha.c:4491 ecoff.c:3035
+#: config/tc-alpha.c:4499 ecoff.c:3035
 msgid ".end directive has no name"
 msgstr ""
 
-#: config/tc-alpha.c:4500
+#: config/tc-alpha.c:4508
 msgid ".end directive names different symbol than .ent"
 msgstr ""
 
-#: config/tc-alpha.c:4577
+#: config/tc-alpha.c:4585
 #, c-format
 msgid "Invalid argument %d to .prologue."
 msgstr ""
 
-#: config/tc-alpha.c:4669
+#: config/tc-alpha.c:4677
 msgid "ECOFF debugging is disabled."
 msgstr ""
 
-#: config/tc-alpha.c:4690
+#: config/tc-alpha.c:4698
 msgid "Unknown section directive"
 msgstr ""
 
-#: config/tc-alpha.c:4726
+#: config/tc-alpha.c:4734
 msgid ".ent directive has no symbol"
 msgstr ""
 
-#: config/tc-alpha.c:4753
+#: config/tc-alpha.c:4761
 msgid "Bad .frame directive 1./2. param"
 msgstr ""
 
-#: config/tc-alpha.c:4765
+#: config/tc-alpha.c:4773
 msgid "Bad .frame directive 3./4. param"
 msgstr ""
 
-#: config/tc-alpha.c:4790
+#: config/tc-alpha.c:4798
 msgid ".pdesc directive not in link (.link) section"
 msgstr ""
 
-#: config/tc-alpha.c:4798
+#: config/tc-alpha.c:4806
 msgid ".pdesc has no matching .ent"
 msgstr ""
 
-#: config/tc-alpha.c:4809
+#: config/tc-alpha.c:4817
 msgid ".pdesc directive has no entry symbol"
 msgstr ""
 
-#: config/tc-alpha.c:4822
+#: config/tc-alpha.c:4830
 msgid "No comma after .pdesc <entryname>"
 msgstr ""
 
-#: config/tc-alpha.c:4845
+#: config/tc-alpha.c:4853
 msgid "unknown procedure kind"
 msgstr ""
 
-#: config/tc-alpha.c:4939
+#: config/tc-alpha.c:4947
 msgid ".name directive not in link (.link) section"
 msgstr ""
 
-#: config/tc-alpha.c:4947
+#: config/tc-alpha.c:4955
 msgid ".name directive has no symbol"
 msgstr ""
 
-#: config/tc-alpha.c:4981
+#: config/tc-alpha.c:4989
 msgid "No symbol after .linkage"
 msgstr ""
 
-#: config/tc-alpha.c:5009
+#: config/tc-alpha.c:5017
 msgid "No symbol after .code_address"
 msgstr ""
 
-#: config/tc-alpha.c:5042 ecoff.c:3253
+#: config/tc-alpha.c:5050 ecoff.c:3253
 msgid "Bad .mask directive"
 msgstr ""
 
-#: config/tc-alpha.c:5063 ecoff.c:3183
+#: config/tc-alpha.c:5071 ecoff.c:3183
 msgid "Bad .fmask directive"
 msgstr ""
 
-#: config/tc-alpha.c:5233 config/tc-arm.c:1593 read.c:2162 read.c:2749
+#: config/tc-alpha.c:5241 config/tc-arm.c:1593 read.c:2150 read.c:2737
 #: stabs.c:464
 #, c-format
 msgid "Expected comma after name \"%s\""
 msgstr ""
 
 #. *symbol_get_obj (symbolP) = (signed char) temp;
-#: config/tc-alpha.c:5244
+#: config/tc-alpha.c:5252
 #, c-format
 msgid "unhandled: .proc %s,%d"
 msgstr ""
 
-#: config/tc-alpha.c:5279
+#: config/tc-alpha.c:5287
 #, c-format
 msgid "Tried to .set unrecognized mode `%s'"
 msgstr ""
 
 #. not fatal, but it might not work in the end
-#: config/tc-alpha.c:5296
+#: config/tc-alpha.c:5304
 msgid "File overrides no-base-register option."
 msgstr ""
 
-#: config/tc-alpha.c:5313
+#: config/tc-alpha.c:5321
 #, c-format
 msgid "Bad base register, using $%d."
 msgstr ""
 
-#: config/tc-alpha.c:5335
+#: config/tc-alpha.c:5343
 #, c-format
 msgid "Alignment too large: %d. assumed"
 msgstr ""
 
-#: config/tc-alpha.c:5339 config/tc-d30v.c:2219
+#: config/tc-alpha.c:5347 config/tc-d30v.c:2219
 msgid "Alignment negative: 0 assumed"
 msgstr ""
 
-#: config/tc-alpha.c:5654
+#: config/tc-alpha.c:5662
 #, c-format
 msgid "Chose GP value of %lx\n"
 msgstr ""
 
-#: config/tc-arc.c:138
-msgid ""
-"ARC options:\n"
-"-EB\t\t\tgenerate big endian output\n"
-"-EL\t\t\tgenerate little endian output\n"
-msgstr ""
-
-#: config/tc-arc.c:156 config/tc-arc.c:179 config/tc-arc.c:921
-#: config/tc-hppa.c:1372 config/tc-hppa.c:6839 config/tc-hppa.c:6845
-#: config/tc-hppa.c:6851 config/tc-hppa.c:6857 config/tc-mn10300.c:924
-#: config/tc-mn10300.c:2133
-msgid "could not set architecture and machine"
-msgstr ""
-
-#: config/tc-arc.c:176
-msgid "virtual memory exhausted"
-msgstr ""
-
-#: config/tc-arc.c:255 config/tc-mn10200.c:1374 config/tc-mn10300.c:2045
-#: config/tc-ppc.c:1221 config/tc-v850.c:1656
-#, c-format
-msgid "operand out of range (%s not between %ld and %ld)"
-msgstr ""
-
-#: config/tc-arc.c:390
-#, c-format
-msgid "unknown syntax format character `%c'"
-msgstr ""
-
-#: config/tc-arc.c:489
-msgid "too many suffixes"
-msgstr ""
-
-#: config/tc-arc.c:533 config/tc-d10v.c:530 config/tc-d30v.c:550
-#: config/tc-mn10200.c:951 config/tc-mn10300.c:1332 config/tc-ppc.c:1969
-#: config/tc-tic80.c:278 config/tc-v850.c:2073
-msgid "illegal operand"
-msgstr ""
-
-#: config/tc-arc.c:620 config/tc-mn10200.c:1050 config/tc-mn10300.c:1476
-#: config/tc-ppc.c:2094 config/tc-v850.c:2152
-#, c-format
-msgid "junk at end of line: `%s'"
-msgstr ""
-
-#: config/tc-arc.c:659
-msgid "8 byte instruction in delay slot"
-msgstr ""
-
-#: config/tc-arc.c:661
-msgid "8 byte jump instruction with delay slot"
-msgstr ""
-
-#: config/tc-arc.c:669
-msgid "conditional branch follows set of flags"
-msgstr ""
-
-#: config/tc-arc.c:748 config/tc-arm.c:7860
-#, c-format
-msgid "bad instruction `%s'"
-msgstr ""
-
-#: config/tc-arc.c:772
-msgid "expected comma after symbol-name"
-msgstr ""
-
-#: config/tc-arc.c:789
-msgid "ignoring attempt to re-define symbol"
-msgstr ""
-
-#: config/tc-arc.c:804
-msgid "expected comma after common length"
-msgstr ""
-
-#: config/tc-arc.c:896
-msgid ".cpu command must appear before any instructions"
-msgstr ""
-
-#: config/tc-arc.c:915
-msgid ".cpu conflicts with previous value"
-msgstr ""
-
-#: config/tc-arc.c:926
-msgid "bad .cpu op"
-msgstr ""
-
-#: config/tc-arc.c:950 config/tc-ppc.c:2742
-msgid "missing rename string"
-msgstr ""
-
-#: config/tc-arc.c:962
-msgid "invalid symbol to rename to"
-msgstr ""
-
-#: config/tc-arc.c:1009 config/tc-avr.c:372 config/tc-d10v.c:313
-#: config/tc-d30v.c:366 config/tc-mips.c:8785 config/tc-mn10200.c:375
-#: config/tc-pj.c:356 config/tc-ppc.c:4511 config/tc-sh.c:2058
-#: config/tc-v850.c:1291
-msgid "bad call to md_atof"
-msgstr ""
-
-#: config/tc-arc.c:1096
-#, c-format
-msgid "missing ')' in %-op"
-msgstr ""
-
-#: config/tc-arc.c:1130
-msgid "expression too complex for %%st"
-msgstr ""
-
-#: config/tc-arc.c:1325 config/tc-arm.c:4569 config/tc-avr.c:852
-#: config/tc-cris.c:2733 config/tc-d10v.c:1558 config/tc-d30v.c:1865
-#: config/tc-mips.c:3227 config/tc-mips.c:4159 config/tc-mips.c:4944
-#: config/tc-mips.c:5490 config/tc-ppc.c:4847 config/tc-v850.c:2385
-msgid "expression too complex"
+#: config/tc-arc.c:1618 config/tc-arm.c:7532
+msgid "md_estimate_size_before_relax\n"
 msgstr ""
 
-#: config/tc-arc.c:1391 config/tc-ppc.c:4949 config/tc-v850.c:2431
-msgid "unresolved expression that must be resolved"
-msgstr ""
-
-#: config/tc-arc.c:1456 config/tc-sparc.c:3380
-#, c-format
-msgid "internal error: can't export reloc type %d (`%s')"
+#: config/tc-arc.c:1630
+msgid "md_convert_frag\n"
 msgstr ""
 
 #: config/tc-arm.c:1156
@@ -1519,16 +1398,16 @@ msgstr ""
 msgid "Invalid syntax for .req directive."
 msgstr ""
 
-#: config/tc-arm.c:1506 config/tc-mips.c:9909 read.c:2047
+#: config/tc-arm.c:1506 config/tc-mips.c:9916 read.c:2035
 #, c-format
 msgid "Alignment too large: %d. assumed."
 msgstr ""
 
-#: config/tc-arm.c:1509 read.c:2052
+#: config/tc-arm.c:1509 read.c:2040
 msgid "Alignment negative. 0 assumed."
 msgstr ""
 
-#: config/tc-arm.c:1643 config/tc-m32r.c:427 read.c:2807 read.c:4869
+#: config/tc-arm.c:1643 config/tc-m32r.c:417 read.c:2795 read.c:4857
 #, c-format
 msgid "symbol `%s' already defined"
 msgstr ""
@@ -1801,6 +1680,13 @@ msgstr ""
 msgid "invalid register mask"
 msgstr ""
 
+#: config/tc-arm.c:4569 config/tc-avr.c:852 config/tc-cris.c:2733
+#: config/tc-d10v.c:1560 config/tc-d30v.c:1865 config/tc-mips.c:3230
+#: config/tc-mips.c:4162 config/tc-mips.c:4947 config/tc-mips.c:5493
+#: config/tc-ppc.c:4854 config/tc-v850.c:2385
+msgid "expression too complex"
+msgstr ""
+
 #: config/tc-arm.c:4608
 msgid "r15 not allowed as base register"
 msgstr ""
@@ -1978,7 +1864,7 @@ msgstr ""
 msgid "out of range branch"
 msgstr ""
 
-#: config/tc-arm.c:7095 config/tc-arm.c:7111 config/tc-mips.c:9736
+#: config/tc-arm.c:7095 config/tc-arm.c:7111 config/tc-mips.c:9743
 msgid "Branch out of range"
 msgstr ""
 
@@ -2061,15 +1947,11 @@ msgstr ""
 msgid "Cannot represent %s relocation in this object file format"
 msgstr ""
 
-#: config/tc-arm.c:7514 config/tc-mips.c:11255 config/tc-sh.c:3177
+#: config/tc-arm.c:7514 config/tc-mips.c:11261 config/tc-sh.c:3177
 #, c-format
 msgid "Can not represent %s relocation in this object file format"
 msgstr ""
 
-#: config/tc-arm.c:7532
-msgid "md_estimate_size_before_relax\n"
-msgstr ""
-
 #: config/tc-arm.c:7611
 #, c-format
 msgid "No operator -- statement `%s'\n"
@@ -2118,6 +2000,11 @@ msgstr ""
 msgid "ignoring incomplete .req pseuso op"
 msgstr ""
 
+#: config/tc-arm.c:7860
+#, c-format
+msgid "bad instruction `%s'"
+msgstr ""
+
 #: config/tc-arm.c:8035
 #, c-format
 msgid "Unrecognised APCS switch -m%s"
@@ -2214,6 +2101,12 @@ msgstr ""
 msgid "redefinition of mcu type `%s' to `%s'"
 msgstr ""
 
+#: config/tc-avr.c:372 config/tc-d10v.c:313 config/tc-d30v.c:366
+#: config/tc-mips.c:8789 config/tc-mn10200.c:375 config/tc-pj.c:356
+#: config/tc-ppc.c:4518 config/tc-sh.c:2058 config/tc-v850.c:1291
+msgid "bad call to md_atof"
+msgstr ""
+
 #: config/tc-avr.c:435
 msgid "constant value required"
 msgstr ""
@@ -2294,7 +2187,7 @@ msgstr ""
 msgid "operand out of range: %ld"
 msgstr ""
 
-#: config/tc-avr.c:1008 config/tc-d10v.c:1629 config/tc-d30v.c:1990
+#: config/tc-avr.c:1008 config/tc-d10v.c:1631 config/tc-d30v.c:1990
 #, c-format
 msgid "line %d: unknown relocation type: 0x%x"
 msgstr ""
@@ -2303,14 +2196,14 @@ msgstr ""
 msgid "only constant expression allowed"
 msgstr ""
 
-#: config/tc-avr.c:1060 config/tc-d10v.c:1493 config/tc-d30v.c:1807
-#: config/tc-mn10200.c:1254 config/tc-mn10300.c:1810 config/tc-ppc.c:5154
+#: config/tc-avr.c:1060 config/tc-d10v.c:1495 config/tc-d30v.c:1807
+#: config/tc-mn10200.c:1254 config/tc-mn10300.c:1810 config/tc-ppc.c:5161
 #: config/tc-v850.c:2301
 #, c-format
 msgid "reloc %d not supported by object file format"
 msgstr ""
 
-#: config/tc-avr.c:1084 config/tc-d10v.c:1100 config/tc-d10v.c:1114
+#: config/tc-avr.c:1084 config/tc-d10v.c:1102 config/tc-d10v.c:1116
 #: config/tc-h8300.c:1239 config/tc-h8500.c:1098 config/tc-mcore.c:988
 #: config/tc-pj.c:265 config/tc-sh.c:1640 config/tc-z8k.c:1195
 msgid "can't find opcode "
@@ -2521,6 +2414,12 @@ msgid ""
 "                        instructions together.\n"
 msgstr ""
 
+#: config/tc-d10v.c:530 config/tc-d30v.c:550 config/tc-mn10200.c:951
+#: config/tc-mn10300.c:1332 config/tc-ppc.c:1972 config/tc-tic80.c:278
+#: config/tc-v850.c:2073
+msgid "illegal operand"
+msgstr ""
+
 #: config/tc-d10v.c:573 config/tc-d10v.c:655 config/tc-d30v.c:656
 #, c-format
 msgid "operand out of range: %d"
@@ -2573,32 +2472,32 @@ msgstr ""
 msgid "unknown execution type passed to write_2_short()"
 msgstr ""
 
-#: config/tc-d10v.c:1128 config/tc-d10v.c:1149 config/tc-d30v.c:1411
+#: config/tc-d10v.c:1130 config/tc-d10v.c:1151 config/tc-d30v.c:1411
 msgid "Unable to mix instructions as specified"
 msgstr ""
 
-#: config/tc-d10v.c:1196 config/tc-d30v.c:1548
+#: config/tc-d10v.c:1198 config/tc-d30v.c:1548
 #, c-format
 msgid "unknown opcode: %s"
 msgstr ""
 
-#: config/tc-d10v.c:1278 config/tc-d10v.c:1449 config/tc-tic80.c:535
+#: config/tc-d10v.c:1280 config/tc-d10v.c:1451 config/tc-tic80.c:535
 msgid "bad opcode or operands"
 msgstr ""
 
-#: config/tc-d10v.c:1351 config/tc-m68k.c:4286
+#: config/tc-d10v.c:1353 config/tc-m68k.c:4286
 msgid "value out of range"
 msgstr ""
 
-#: config/tc-d10v.c:1424
+#: config/tc-d10v.c:1426
 msgid "illegal operand - register name found where none expected"
 msgstr ""
 
-#: config/tc-d10v.c:1460 config/tc-tic80.c:546
+#: config/tc-d10v.c:1462 config/tc-tic80.c:546
 msgid "Register number must be EVEN"
 msgstr ""
 
-#: config/tc-d10v.c:1609
+#: config/tc-d10v.c:1611
 #, c-format
 msgid "line %d: rep or repi must include at least 4 instructions"
 msgstr ""
@@ -2754,11 +2653,11 @@ msgstr ""
 msgid "Instruction %s not allowed in a delay slot."
 msgstr ""
 
-#: config/tc-fr30.c:380 config/tc-m32r.c:1565
+#: config/tc-fr30.c:380 config/tc-m32r.c:1555
 msgid "Addend to unresolved symbol not on word boundary."
 msgstr ""
 
-#: config/tc-fr30.c:538 config/tc-i960.c:772 config/tc-m32r.c:1874
+#: config/tc-fr30.c:538 config/tc-i960.c:772 config/tc-m32r.c:1864
 msgid "Bad call to md_atof()"
 msgstr ""
 
@@ -2834,7 +2733,7 @@ msgstr ""
 msgid "invalid operands"
 msgstr ""
 
-#: config/tc-h8300.c:1250 config/tc-h8500.c:1104 config/tc-mips.c:7981
+#: config/tc-h8300.c:1250 config/tc-h8500.c:1104 config/tc-mips.c:7984
 #: config/tc-sh.c:1877 config/tc-w65.c:740 config/tc-z8k.c:1205
 msgid "unknown opcode"
 msgstr ""
@@ -2939,6 +2838,12 @@ msgstr ""
 msgid "Invalid field selector.  Assuming F%%."
 msgstr ""
 
+#: config/tc-hppa.c:1372 config/tc-hppa.c:6839 config/tc-hppa.c:6845
+#: config/tc-hppa.c:6851 config/tc-hppa.c:6857 config/tc-mn10300.c:924
+#: config/tc-mn10300.c:2133
+msgid "could not set architecture and machine"
+msgstr ""
+
 #: config/tc-hppa.c:1378
 msgid "-R option not supported on this target."
 msgstr ""
@@ -3183,7 +3088,7 @@ msgstr ""
 msgid ".REG expression must be a register"
 msgstr ""
 
-#: config/tc-hppa.c:6442 read.c:4740
+#: config/tc-hppa.c:6442 read.c:4728
 msgid "bad or irreducible absolute expression; zero assumed"
 msgstr ""
 
@@ -3332,304 +3237,344 @@ msgstr ""
 msgid "No memory for symbol name."
 msgstr ""
 
-#: config/tc-i386.c:517
+#: config/tc-i386.c:581
 #, c-format
 msgid "%s shortened to %s"
 msgstr ""
 
-#: config/tc-i386.c:569
+#: config/tc-i386.c:636
 msgid "same type of prefix used twice"
 msgstr ""
 
-#: config/tc-i386.c:612
+#: config/tc-i386.c:654
+msgid "64bit mode not supported on this CPU."
+msgstr ""
+
+#: config/tc-i386.c:658
+msgid "32bit mode not supported on this CPU."
+msgstr ""
+
+#: config/tc-i386.c:691
 msgid "bad argument to syntax directive."
 msgstr ""
 
-#: config/tc-i386.c:655
+#: config/tc-i386.c:734
 #, c-format
 msgid "no such architecture: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:660
+#: config/tc-i386.c:739
 msgid "missing cpu architecture"
 msgstr ""
 
-#: config/tc-i386.c:733 config/tc-m68k.c:3802
+#: config/tc-i386.c:812 config/tc-i386.c:835 config/tc-m68k.c:3802
 #, c-format
 msgid "Internal Error:  Can't hash %s: %s"
 msgstr ""
 
-#: config/tc-i386.c:961
-msgid "Unknown"
+#: config/tc-i386.c:1088
+msgid "There are no unsigned pc-relative relocations"
 msgstr ""
 
-#: config/tc-i386.c:1010 config/tc-i386.c:4060
+#: config/tc-i386.c:1095 config/tc-i386.c:4622
 #, c-format
 msgid "can not do %d byte pc-relative relocation"
 msgstr ""
 
-#: config/tc-i386.c:1020 config/tc-i386.c:4074
+#: config/tc-i386.c:1112
 #, c-format
-msgid "can not do %d byte relocation"
+msgid "can not do %s %d byte relocation"
 msgstr ""
 
-#: config/tc-i386.c:1122 config/tc-i386.c:1204
+#: config/tc-i386.c:1221 config/tc-i386.c:1314
 #, c-format
 msgid "no such instruction: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1131
+#: config/tc-i386.c:1230
 #, c-format
 msgid "invalid character %s in mnemonic"
 msgstr ""
 
-#: config/tc-i386.c:1138
+#: config/tc-i386.c:1237
 msgid "expecting prefix; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1140
+#: config/tc-i386.c:1239
 msgid "expecting mnemonic; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1158
+#: config/tc-i386.c:1257
 #, c-format
 msgid "redundant %s prefix"
 msgstr ""
 
-#: config/tc-i386.c:1214
+#: config/tc-i386.c:1325
 #, c-format
 msgid "`%s' is not supported on `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1219
+#: config/tc-i386.c:1330
 msgid "use .code16 to ensure correct addressing mode"
 msgstr ""
 
-#: config/tc-i386.c:1227
+#: config/tc-i386.c:1338
 #, c-format
 msgid "expecting string instruction after `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1248
+#: config/tc-i386.c:1359
 #, c-format
 msgid "invalid character %s before operand %d"
 msgstr ""
 
-#: config/tc-i386.c:1262
+#: config/tc-i386.c:1373
 #, c-format
 msgid "unbalanced parenthesis in operand %d."
 msgstr ""
 
-#: config/tc-i386.c:1265
+#: config/tc-i386.c:1376
 #, c-format
 msgid "unbalanced brackets in operand %d."
 msgstr ""
 
-#: config/tc-i386.c:1274
+#: config/tc-i386.c:1385
 #, c-format
 msgid "invalid character %s in operand %d"
 msgstr ""
 
-#: config/tc-i386.c:1301
+#: config/tc-i386.c:1412
 #, c-format
 msgid "spurious operands; (%d operands/instruction max)"
 msgstr ""
 
-#: config/tc-i386.c:1324
+#: config/tc-i386.c:1435
 msgid "expecting operand after ','; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1329
+#: config/tc-i386.c:1440
 msgid "expecting operand before ','; got nothing"
 msgstr ""
 
 #. We found no match.
-#: config/tc-i386.c:1607
+#: config/tc-i386.c:1782
 #, c-format
 msgid "suffix or operands invalid for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1618
+#: config/tc-i386.c:1793
 #, c-format
 msgid "indirect %s without `*'"
 msgstr ""
 
 #. Warn them that a data or address size prefix doesn't
 #. affect assembly of the next line of code.
-#: config/tc-i386.c:1626
+#: config/tc-i386.c:1801
 #, c-format
 msgid "stand-alone `%s' prefix"
 msgstr ""
 
-#: config/tc-i386.c:1662 config/tc-i386.c:1677
+#: config/tc-i386.c:1837 config/tc-i386.c:1852
 msgid "`%s' operand %d must use `%%es' segment"
 msgstr ""
 
-#: config/tc-i386.c:1745 config/tc-i386.c:1788 config/tc-i386.c:1816
+#: config/tc-i386.c:1867
+msgid "Extended register `%%%s' available only in 64bit mode."
+msgstr ""
+
+#. Prohibit these changes in the 64bit mode, since
+#. the lowering is more complicated.
+#: config/tc-i386.c:1938 config/tc-i386.c:1989 config/tc-i386.c:2004
+#: config/tc-i386.c:2032 config/tc-i386.c:2060
+msgid "Incorrect register `%%%s' used with`%c' suffix"
+msgstr ""
+
+#: config/tc-i386.c:1944 config/tc-i386.c:1994 config/tc-i386.c:2065
 msgid "using `%%%s' instead of `%%%s' due to `%c' suffix"
 msgstr ""
 
-#: config/tc-i386.c:1758 config/tc-i386.c:1776 config/tc-i386.c:1804
+#: config/tc-i386.c:1957 config/tc-i386.c:1975 config/tc-i386.c:2019
+#: config/tc-i386.c:2046
 msgid "`%%%s' not allowed with `%s%c'"
 msgstr ""
 
-#: config/tc-i386.c:1852 config/tc-i386.c:1872
+#: config/tc-i386.c:2106
 msgid "no instruction mnemonic suffix given; can't determine immediate size"
 msgstr ""
 
-#: config/tc-i386.c:1897
+#: config/tc-i386.c:2132
+#, c-format
+msgid ""
+"no instruction mnemonic suffix given; can't determine immediate size %x %c"
+msgstr ""
+
+#: config/tc-i386.c:2157
 msgid ""
 "no instruction mnemonic suffix given and no register operands; can't size "
 "instruction"
 msgstr ""
 
+#: config/tc-i386.c:2205
+msgid "64bit operations available only in 64bit modes."
+msgstr ""
+
 #. Reversed arguments on faddp, fsubp, etc.
-#: config/tc-i386.c:1999
+#: config/tc-i386.c:2273
 msgid "translating to `%s %%%s,%%%s'"
 msgstr ""
 
 #. Extraneous `l' suffix on fp insn.
-#: config/tc-i386.c:2006
+#: config/tc-i386.c:2280
 msgid "translating to `%s %%%s'"
 msgstr ""
 
-#: config/tc-i386.c:2222
+#: config/tc-i386.c:2551
 msgid "you can't `pop %%cs'"
 msgstr ""
 
 #. UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.
-#: config/tc-i386.c:2253
+#: config/tc-i386.c:2584
 #, c-format
 msgid "translating to `%sp'"
 msgstr ""
 
-#: config/tc-i386.c:2302 config/tc-i386.c:2365 config/tc-i386.c:2407
+#: config/tc-i386.c:2627
+msgid ""
+"Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"
+msgstr ""
+
+#: config/tc-i386.c:2679 config/tc-i386.c:2751 config/tc-i386.c:2798
 msgid "skipping prefixes on this instruction"
 msgstr ""
 
-#: config/tc-i386.c:2423
+#: config/tc-i386.c:2819
 msgid "16-bit jump out of range"
 msgstr ""
 
-#: config/tc-i386.c:2432
+#: config/tc-i386.c:2828
 #, c-format
 msgid "can't handle non absolute segment in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:2650
+#: config/tc-i386.c:3085
 msgid "only 1 or 2 immediate operands are allowed"
 msgstr ""
 
-#: config/tc-i386.c:2680 config/tc-i386.c:2899
+#: config/tc-i386.c:3115 config/tc-i386.c:3353
 msgid "GOT relocations not supported in 16 bit mode"
 msgstr ""
 
-#: config/tc-i386.c:2701 config/tc-i386.c:2920
+#: config/tc-i386.c:3152 config/tc-i386.c:3389
 msgid "bad reloc specifier in expression"
 msgstr ""
 
-#: config/tc-i386.c:2719 config/tc-i386.c:2954
+#: config/tc-i386.c:3170 config/tc-i386.c:3424
 #, c-format
 msgid "ignoring junk `%s' after expression"
 msgstr ""
 
 #. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:2726
+#: config/tc-i386.c:3177
 #, c-format
 msgid "missing or invalid immediate expression `%s' taken as 0"
 msgstr ""
 
-#: config/tc-i386.c:2754 config/tc-i386.c:2984
+#: config/tc-i386.c:3208 config/tc-i386.c:3454
 #, c-format
 msgid "unimplemented segment %s in operand"
 msgstr ""
 
-#: config/tc-i386.c:2756 config/tc-i386.c:2986
+#: config/tc-i386.c:3210 config/tc-i386.c:3456
 #, c-format
 msgid "unimplemented segment type %d in operand"
 msgstr ""
 
-#: config/tc-i386.c:2800 config/tc-i386.c:4755
+#: config/tc-i386.c:3252 config/tc-i386.c:5392
 #, c-format
 msgid "expecting scale factor of 1, 2, 4, or 8: got `%s'"
 msgstr ""
 
-#: config/tc-i386.c:2806
+#: config/tc-i386.c:3258
 #, c-format
 msgid "scale factor of %d without an index register"
 msgstr ""
 
 #. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:2965
+#: config/tc-i386.c:3435
 #, c-format
 msgid "missing or invalid displacement expression `%s' taken as 0"
 msgstr ""
 
-#: config/tc-i386.c:3043
+#: config/tc-i386.c:3541
 #, c-format
 msgid "`%s' is not a valid base/index expression"
 msgstr ""
 
-#: config/tc-i386.c:3047
+#: config/tc-i386.c:3545
 #, c-format
 msgid "`%s' is not a valid %s bit base/index expression"
 msgstr ""
 
-#: config/tc-i386.c:3122
+#: config/tc-i386.c:3620
 #, c-format
 msgid "bad memory operand `%s'"
 msgstr ""
 
-#: config/tc-i386.c:3137
+#: config/tc-i386.c:3635
 #, c-format
 msgid "junk `%s' after register"
 msgstr ""
 
-#: config/tc-i386.c:3146 config/tc-i386.c:3261 config/tc-i386.c:3297
+#: config/tc-i386.c:3644 config/tc-i386.c:3759 config/tc-i386.c:3795
 #, c-format
 msgid "bad register name `%s'"
 msgstr ""
 
-#: config/tc-i386.c:3154
+#: config/tc-i386.c:3652
 msgid "immediate operand illegal with absolute jump"
 msgstr ""
 
-#: config/tc-i386.c:3176
+#: config/tc-i386.c:3674
 #, c-format
 msgid "too many memory references for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:3254
+#: config/tc-i386.c:3752
 #, c-format
 msgid "expecting `,' or `)' after index register in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:3276
+#: config/tc-i386.c:3774
 #, c-format
 msgid "expecting `)' after scale factor in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:3283
+#: config/tc-i386.c:3781
 #, c-format
 msgid "expecting index register or scale factor after `,'; got '%c'"
 msgstr ""
 
-#: config/tc-i386.c:3290
+#: config/tc-i386.c:3788
 #, c-format
 msgid "expecting `,' or `)' after base register in `%s'"
 msgstr ""
 
 #. It's not a memory operand; argh!
-#: config/tc-i386.c:3331
+#: config/tc-i386.c:3829
 #, c-format
 msgid "invalid char %s beginning operand %d `%s'"
 msgstr ""
 
-#: config/tc-i386.c:3753
+#: config/tc-i386.c:4267
 msgid "Bad call to md_atof ()"
 msgstr ""
 
-#: config/tc-i386.c:3903
+#: config/tc-i386.c:4431 config/tc-sparc.c:548
+#, c-format
+msgid "No compiled in support for %d bit object file format"
+msgstr ""
+
+#: config/tc-i386.c:4449
 msgid ""
 "  -Q                      ignored\n"
 "  -V                      print assembler version number\n"
@@ -3638,58 +3583,67 @@ msgid ""
 "  -s                      ignored\n"
 msgstr ""
 
-#: config/tc-i386.c:3910
+#: config/tc-i386.c:4456
 msgid "  -q                      quieten some warnings\n"
 msgstr ""
 
-#: config/tc-i386.c:3960
+#: config/tc-i386.c:4475
+msgid "Unknown architecture"
+msgstr ""
+
+#: config/tc-i386.c:4515
 msgid "GOT already in symbol table"
 msgstr ""
 
-#: config/tc-i386.c:4109
+#: config/tc-i386.c:4636
+#, c-format
+msgid "can not do %d byte relocation"
+msgstr ""
+
+#: config/tc-i386.c:4697
 #, c-format
 msgid "cannot represent relocation type %s"
 msgstr ""
 
-#: config/tc-i386.c:4403
+#: config/tc-i386.c:4994
 #, c-format
 msgid "too many memory references for '%s'"
 msgstr ""
 
-#: config/tc-i386.c:4561
+#: config/tc-i386.c:5157
 #, c-format
 msgid "Unknown operand modifier `%s'\n"
 msgstr ""
 
-#: config/tc-i386.c:4727
+#: config/tc-i386.c:5364
 #, c-format
 msgid "`%s' is not a valid segment register"
 msgstr ""
 
-#: config/tc-i386.c:4737 config/tc-i386.c:4859
+#: config/tc-i386.c:5374 config/tc-i386.c:5495
 msgid "Register scaling only allowed in memory operands."
 msgstr ""
 
-#: config/tc-i386.c:4768
+#: config/tc-i386.c:5405
 msgid "Too many register references in memory operand.\n"
 msgstr ""
 
-#: config/tc-i386.c:4838
+#: config/tc-i386.c:5474
 #, c-format
 msgid "Syntax error. Expecting a constant. Got `%s'.\n"
 msgstr ""
 
-#: config/tc-i386.c:4908
+#: config/tc-i386.c:5544
 #, c-format
 msgid "Unrecognized token '%s'"
 msgstr ""
 
-#: config/tc-i386.c:4925
+#: config/tc-i386.c:5561
 #, c-format
 msgid "Unexpected token `%s'\n"
 msgstr ""
 
-#: config/tc-i386.c:5069
+#: config/tc-i386.c:5705
 #, c-format
 msgid "Unrecognized token `%s'\n"
 msgstr ""
@@ -3698,7 +3652,7 @@ msgstr ""
 msgid "Unknown temporary pseudo register"
 msgstr ""
 
-#: config/tc-i860.c:181 config/tc-mips.c:1025
+#: config/tc-i860.c:181 config/tc-mips.c:1027
 #, c-format
 msgid "internal error: can't hash `%s': %s\n"
 msgstr ""
@@ -4055,7 +4009,7 @@ msgid ""
 "  -xdebug\t\t  debug dependency violation checker\n"
 msgstr ""
 
-#: config/tc-ia64.c:6147 config/tc-mips.c:1012
+#: config/tc-ia64.c:6147 config/tc-mips.c:1014
 msgid "Could not set architecture and machine"
 msgstr ""
 
@@ -4161,87 +4115,87 @@ msgstr ""
 msgid "  -cpu-desc              provide runtime cpu description file\n"
 msgstr ""
 
-#: config/tc-m32r.c:698
+#: config/tc-m32r.c:688
 msgid "Instructions write to the same destination register."
 msgstr ""
 
-#: config/tc-m32r.c:706
+#: config/tc-m32r.c:696
 msgid "Instructions do not use parallel execution pipelines."
 msgstr ""
 
-#: config/tc-m32r.c:713
+#: config/tc-m32r.c:703
 msgid "Instructions share the same execution pipeline"
 msgstr ""
 
-#: config/tc-m32r.c:783 config/tc-m32r.c:880
+#: config/tc-m32r.c:773 config/tc-m32r.c:870
 #, c-format
 msgid "not a 16 bit instruction '%s'"
 msgstr ""
 
-#: config/tc-m32r.c:790 config/tc-m32r.c:887 config/tc-m32r.c:1043
+#: config/tc-m32r.c:780 config/tc-m32r.c:877 config/tc-m32r.c:1033
 #, c-format
 msgid "unknown instruction '%s'"
 msgstr ""
 
-#: config/tc-m32r.c:799 config/tc-m32r.c:894 config/tc-m32r.c:1050
+#: config/tc-m32r.c:789 config/tc-m32r.c:884 config/tc-m32r.c:1040
 #, c-format
 msgid "instruction '%s' is for the M32RX only"
 msgstr ""
 
-#: config/tc-m32r.c:808 config/tc-m32r.c:903
+#: config/tc-m32r.c:798 config/tc-m32r.c:893
 #, c-format
 msgid "instruction '%s' cannot be executed in parallel."
 msgstr ""
 
-#: config/tc-m32r.c:864 config/tc-m32r.c:928 config/tc-m32r.c:1100
+#: config/tc-m32r.c:854 config/tc-m32r.c:918 config/tc-m32r.c:1090
 msgid "internal error: lookup/get operands failed"
 msgstr ""
 
-#: config/tc-m32r.c:913
+#: config/tc-m32r.c:903
 #, c-format
 msgid "'%s': only the NOP instruction can be issued in parallel on the m32r"
 msgstr ""
 
-#: config/tc-m32r.c:942
+#: config/tc-m32r.c:932
 #, c-format
 msgid ""
 "%s: output of 1st instruction is the same as an input to 2nd instruction - "
 "is this intentional ?"
 msgstr ""
 
-#: config/tc-m32r.c:946
+#: config/tc-m32r.c:936
 #, c-format
 msgid ""
 "%s: output of 2nd instruction is the same as an input to 1st instruction - "
 "is this intentional ?"
 msgstr ""
 
-#: config/tc-m32r.c:1260 config/tc-ppc.c:1456 config/tc-ppc.c:3674 read.c:1370
+#: config/tc-m32r.c:1250 config/tc-ppc.c:1459 config/tc-ppc.c:3681 read.c:1358
 msgid "Expected comma after symbol-name: rest of line ignored."
 msgstr ""
 
-#: config/tc-m32r.c:1270
+#: config/tc-m32r.c:1260
 #, c-format
 msgid ".SCOMMon length (%ld.) <0! Ignored."
 msgstr ""
 
-#: config/tc-m32r.c:1284 config/tc-ppc.c:1478 config/tc-ppc.c:2385
-#: config/tc-ppc.c:3698
+#: config/tc-m32r.c:1274 config/tc-ppc.c:1481 config/tc-ppc.c:2392
+#: config/tc-ppc.c:3705
 msgid "ignoring bad alignment"
 msgstr ""
 
-#: config/tc-m32r.c:1311 config/tc-ppc.c:1489 config/tc-ppc.c:3710 read.c:1394
-#: read.c:2120
+#: config/tc-m32r.c:1301 config/tc-ppc.c:1492 config/tc-ppc.c:3717 read.c:1382
+#: read.c:2108
 #, c-format
 msgid "Ignoring attempt to re-define symbol `%s'."
 msgstr ""
 
-#: config/tc-m32r.c:1320
+#: config/tc-m32r.c:1310
 #, c-format
 msgid "Length of .scomm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
 
-#: config/tc-m32r.c:1796
+#: config/tc-m32r.c:1786
 msgid "Unmatched high/shigh reloc"
 msgstr ""
 
@@ -4526,34 +4480,34 @@ msgstr ""
 msgid "Relocation %d is not supported by object file format."
 msgstr ""
 
-#: config/tc-m68hc11.c:2560
+#: config/tc-m68hc11.c:2571
 msgid "bra or bsr with undefined symbol."
 msgstr ""
 
-#: config/tc-m68hc11.c:2668
+#: config/tc-m68hc11.c:2683
 #, c-format
 msgid "Subtype %d is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:2705
+#: config/tc-m68hc11.c:2720
 msgid "Expression too complex."
 msgstr ""
 
-#: config/tc-m68hc11.c:2734
+#: config/tc-m68hc11.c:2749
 msgid "Value out of 16-bit range."
 msgstr ""
 
-#: config/tc-m68hc11.c:2757
+#: config/tc-m68hc11.c:2772
 #, c-format
 msgid "Value %ld too large for 8-bit PC-relative branch."
 msgstr ""
 
-#: config/tc-m68hc11.c:2764
+#: config/tc-m68hc11.c:2779
 #, c-format
 msgid "Auto increment/decrement offset '%ld' is out of range."
 msgstr ""
 
-#: config/tc-m68hc11.c:2775
+#: config/tc-m68hc11.c:2790
 #, c-format
 msgid "Line %d: unknown relocation type: 0x%x."
 msgstr ""
@@ -4582,7 +4536,7 @@ msgstr ""
 msgid "Can not do %d byte pic relocation"
 msgstr ""
 
-#: config/tc-m68k.c:919 config/tc-mips.c:11236
+#: config/tc-m68k.c:919 config/tc-mips.c:11242
 #, c-format
 msgid "Cannot make %s relocation PC relative"
 msgstr ""
@@ -4993,7 +4947,7 @@ msgstr ""
 msgid "Relaxation should never occur"
 msgstr ""
 
-#: config/tc-m88k.c:1264 config/tc-sparc.c:3540 read.c:1974
+#: config/tc-m88k.c:1264 config/tc-sparc.c:3540 read.c:1962
 #, c-format
 msgid "BSS length (%d.) <0! Ignored."
 msgstr ""
@@ -5225,327 +5179,327 @@ msgstr ""
 msgid "Cannot represent relocation type %s"
 msgstr ""
 
-#: config/tc-mips.c:641
+#: config/tc-mips.c:642
 #, c-format
 msgid "internal Error, line %d, %s"
 msgstr ""
 
-#: config/tc-mips.c:643
+#: config/tc-mips.c:644
 msgid "MIPS internal Error"
 msgstr ""
 
-#: config/tc-mips.c:925
+#: config/tc-mips.c:927
 msgid "-G not supported in this configuration."
 msgstr ""
 
-#: config/tc-mips.c:994
+#: config/tc-mips.c:996
 msgid "trap exception not supported at ISA 1"
 msgstr ""
 
-#: config/tc-mips.c:1051
+#: config/tc-mips.c:1053
 #, c-format
 msgid "internal: can't hash `%s': %s"
 msgstr ""
 
-#: config/tc-mips.c:1059
+#: config/tc-mips.c:1061
 #, c-format
 msgid "internal error: bad mips16 opcode: %s %s\n"
 msgstr ""
 
-#: config/tc-mips.c:1227
+#: config/tc-mips.c:1229
 #, c-format
 msgid "returned from mips_ip(%s) insn_opcode = 0x%x\n"
 msgstr ""
 
-#: config/tc-mips.c:1781 config/tc-mips.c:11368
+#: config/tc-mips.c:1782 config/tc-mips.c:11374
 msgid "extended instruction in delay slot"
 msgstr ""
 
-#: config/tc-mips.c:1803 config/tc-mips.c:1810
+#: config/tc-mips.c:1804 config/tc-mips.c:1811
 #, c-format
 msgid "jump to misaligned address (0x%lx)"
 msgstr ""
 
-#: config/tc-mips.c:2459 config/tc-mips.c:2813
+#: config/tc-mips.c:2460 config/tc-mips.c:2814
 msgid "Macro instruction expanded into multiple instructions"
 msgstr ""
 
-#: config/tc-mips.c:2866
+#: config/tc-mips.c:2867
 msgid "unsupported large constant"
 msgstr ""
 
-#: config/tc-mips.c:2868
+#: config/tc-mips.c:2869
 #, c-format
 msgid "Instruction %s requires absolute expression"
 msgstr ""
 
-#: config/tc-mips.c:3014
+#: config/tc-mips.c:3015
 msgid "Number larger than 32 bits"
 msgstr ""
 
-#: config/tc-mips.c:3035
+#: config/tc-mips.c:3036
 msgid "Number larger than 64 bits"
 msgstr ""
 
-#: config/tc-mips.c:3301 config/tc-mips.c:3373 config/tc-mips.c:5052
-#: config/tc-mips.c:5103 config/tc-mips.c:5639 config/tc-mips.c:5702
+#: config/tc-mips.c:3304 config/tc-mips.c:3376 config/tc-mips.c:5055
+#: config/tc-mips.c:5106 config/tc-mips.c:5642 config/tc-mips.c:5705
 msgid "PIC code offset overflow (max 16 signed bits)"
 msgstr ""
 
-#: config/tc-mips.c:3612
+#: config/tc-mips.c:3615
 #, c-format
 msgid "Branch %s is always false (nop)"
 msgstr ""
 
-#: config/tc-mips.c:3617
+#: config/tc-mips.c:3620
 #, c-format
 msgid "Branch likely %s is always false"
 msgstr ""
 
-#: config/tc-mips.c:3624 config/tc-mips.c:3698 config/tc-mips.c:3801
-#: config/tc-mips.c:3856 config/tc-mips.c:6739 config/tc-mips.c:6748
-#: config/tc-mips.c:6756 config/tc-mips.c:6865
+#: config/tc-mips.c:3627 config/tc-mips.c:3701 config/tc-mips.c:3804
+#: config/tc-mips.c:3859 config/tc-mips.c:6742 config/tc-mips.c:6751
+#: config/tc-mips.c:6759 config/tc-mips.c:6868
 msgid "Unsupported large constant"
 msgstr ""
 
 #. result is always true
-#: config/tc-mips.c:3660
+#: config/tc-mips.c:3663
 #, c-format
 msgid "Branch %s is always true"
 msgstr ""
 
-#: config/tc-mips.c:3932 config/tc-mips.c:4039
+#: config/tc-mips.c:3935 config/tc-mips.c:4042
 msgid "Divide by zero."
 msgstr ""
 
-#: config/tc-mips.c:4623
+#: config/tc-mips.c:4626
 msgid "MIPS PIC call to register other than $25"
 msgstr ""
 
-#: config/tc-mips.c:4628 config/tc-mips.c:4740
+#: config/tc-mips.c:4631 config/tc-mips.c:4743
 msgid "No .cprestore pseudo-op used in PIC code"
 msgstr ""
 
-#: config/tc-mips.c:4813 config/tc-mips.c:4902 config/tc-mips.c:5390
-#: config/tc-mips.c:5431 config/tc-mips.c:5449 config/tc-mips.c:6078
+#: config/tc-mips.c:4816 config/tc-mips.c:4905 config/tc-mips.c:5393
+#: config/tc-mips.c:5434 config/tc-mips.c:5452 config/tc-mips.c:6081
 msgid "opcode not supported on this processor"
 msgstr ""
 
-#: config/tc-mips.c:5909 config/tc-mips.c:6633
+#: config/tc-mips.c:5912 config/tc-mips.c:6636
 msgid "Macro used $at after \".set noat\""
 msgstr ""
 
-#: config/tc-mips.c:6049 config/tc-mips.c:6067
+#: config/tc-mips.c:6052 config/tc-mips.c:6070
 msgid "rotate count too large"
 msgstr ""
 
-#: config/tc-mips.c:6118
+#: config/tc-mips.c:6121
 #, c-format
 msgid "Instruction %s: result is always false"
 msgstr ""
 
-#: config/tc-mips.c:6287
+#: config/tc-mips.c:6290
 #, c-format
 msgid "Instruction %s: result is always true"
 msgstr ""
 
-#: config/tc-mips.c:6426 config/tc-mips.c:6453 config/tc-mips.c:6525
-#: config/tc-mips.c:6550
+#: config/tc-mips.c:6429 config/tc-mips.c:6456 config/tc-mips.c:6528
+#: config/tc-mips.c:6553
 msgid "operand overflow"
 msgstr ""
 
 #. FIXME: Check if this is one of the itbl macros, since they
 #. are added dynamically.
-#: config/tc-mips.c:6629
+#: config/tc-mips.c:6632
 #, c-format
 msgid "Macro %s not implemented yet"
 msgstr ""
 
-#: config/tc-mips.c:6899
+#: config/tc-mips.c:6902
 #, c-format
 msgid "internal: bad mips opcode (mask error): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:6955
+#: config/tc-mips.c:6958
 #, c-format
 msgid "internal: bad mips opcode (unknown operand type `%c'): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:6962
+#: config/tc-mips.c:6965
 #, c-format
 msgid "internal: bad mips opcode (bits 0x%lx undefined): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:7070
+#: config/tc-mips.c:7073
 #, c-format
 msgid "opcode not supported on this processor: %s (%s)"
 msgstr ""
 
-#: config/tc-mips.c:7141
+#: config/tc-mips.c:7144
 #, c-format
 msgid "Improper shift amount (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:7167 config/tc-mips.c:8321 config/tc-mips.c:8436
+#: config/tc-mips.c:7170 config/tc-mips.c:8324 config/tc-mips.c:8439
 #, c-format
 msgid "Invalid value for `%s' (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:7185
+#: config/tc-mips.c:7188
 #, c-format
 msgid "Illegal break code (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:7199
+#: config/tc-mips.c:7202
 #, c-format
 msgid "Illegal lower break code (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:7212
+#: config/tc-mips.c:7215
 #, c-format
 msgid "Illegal 20-bit code (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:7224
+#: config/tc-mips.c:7227
 #, c-format
 msgid "Coproccesor code > 25 bits (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:7237
+#: config/tc-mips.c:7240
 #, c-format
 msgid "Illegal 19-bit code (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:7249
+#: config/tc-mips.c:7252
 #, c-format
 msgid "Invalidate performance regster (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:7286
+#: config/tc-mips.c:7289
 #, c-format
 msgid "Invalid register number (%d)"
 msgstr ""
 
-#: config/tc-mips.c:7450
+#: config/tc-mips.c:7453
 #, c-format
 msgid "Invalid float register number (%d)"
 msgstr ""
 
-#: config/tc-mips.c:7460
+#: config/tc-mips.c:7463
 #, c-format
 msgid "Float register should be even, was %d"
 msgstr ""
 
-#: config/tc-mips.c:7511
+#: config/tc-mips.c:7514
 msgid "absolute expression required"
 msgstr ""
 
-#: config/tc-mips.c:7572
+#: config/tc-mips.c:7575
 #, c-format
 msgid "Bad floating point constant: %s"
 msgstr ""
 
-#: config/tc-mips.c:7694
+#: config/tc-mips.c:7697
 msgid "Can't use floating point insn in this section"
 msgstr ""
 
-#: config/tc-mips.c:7748
+#: config/tc-mips.c:7751
 msgid "16 bit expression not in range 0..65535"
 msgstr ""
 
-#: config/tc-mips.c:7785
+#: config/tc-mips.c:7788
 msgid "16 bit expression not in range -32768..32767"
 msgstr ""
 
-#: config/tc-mips.c:7856
+#: config/tc-mips.c:7859
 msgid "lui expression not in range 0..65535"
 msgstr ""
 
-#: config/tc-mips.c:7880
+#: config/tc-mips.c:7883
 #, c-format
 msgid "invalid condition code register $fcc%d"
 msgstr ""
 
-#: config/tc-mips.c:7905
+#: config/tc-mips.c:7908
 msgid "invalid coprocessor sub-selection value (0-7)"
 msgstr ""
 
-#: config/tc-mips.c:7910
+#: config/tc-mips.c:7913
 #, c-format
 msgid "bad char = '%c'\n"
 msgstr ""
 
-#: config/tc-mips.c:7923 config/tc-mips.c:8461
+#: config/tc-mips.c:7926 config/tc-mips.c:8464
 msgid "illegal operands"
 msgstr ""
 
-#: config/tc-mips.c:7990
+#: config/tc-mips.c:7993
 msgid "unrecognized opcode"
 msgstr ""
 
-#: config/tc-mips.c:8099
+#: config/tc-mips.c:8102
 #, c-format
 msgid "invalid register number (%d)"
 msgstr ""
 
-#: config/tc-mips.c:8180
+#: config/tc-mips.c:8183
 msgid "used $at without \".set noat\""
 msgstr ""
 
-#: config/tc-mips.c:8355
+#: config/tc-mips.c:8358
 msgid "can't parse register list"
 msgstr ""
 
-#: config/tc-mips.c:8389 config/tc-mips.c:8419
+#: config/tc-mips.c:8392 config/tc-mips.c:8422
 msgid "invalid register list"
 msgstr ""
 
-#: config/tc-mips.c:8586
+#: config/tc-mips.c:8590
 msgid "extended operand requested but not required"
 msgstr ""
 
-#: config/tc-mips.c:8588
+#: config/tc-mips.c:8592
 msgid "invalid unextended operand value"
 msgstr ""
 
-#: config/tc-mips.c:8616
+#: config/tc-mips.c:8620
 msgid "operand value out of range for instruction"
 msgstr ""
 
-#: config/tc-mips.c:9001
+#: config/tc-mips.c:9005
 #, c-format
 msgid "invalid architecture -mcpu=%s"
 msgstr ""
 
-#: config/tc-mips.c:9050
+#: config/tc-mips.c:9054
 msgid "-G may not be used with embedded PIC code"
 msgstr ""
 
-#: config/tc-mips.c:9062
+#: config/tc-mips.c:9066
 msgid "-call_shared is supported only for ELF format"
 msgstr ""
 
-#: config/tc-mips.c:9068 config/tc-mips.c:10151 config/tc-mips.c:10325
+#: config/tc-mips.c:9072 config/tc-mips.c:10158 config/tc-mips.c:10332
 msgid "-G may not be used with SVR4 PIC code"
 msgstr ""
 
-#: config/tc-mips.c:9077
+#: config/tc-mips.c:9081
 msgid "-non_shared is supported only for ELF format"
 msgstr ""
 
-#: config/tc-mips.c:9093
+#: config/tc-mips.c:9097
 msgid "-G is not supported for this configuration"
 msgstr ""
 
-#: config/tc-mips.c:9098
+#: config/tc-mips.c:9102
 msgid "-G may not be used with SVR4 or embedded PIC code"
 msgstr ""
 
-#: config/tc-mips.c:9122
+#: config/tc-mips.c:9126
 msgid "No compiled in support for 64 bit object file format"
 msgstr ""
 
-#: config/tc-mips.c:9210
+#: config/tc-mips.c:9218
 msgid ""
 "MIPS options:\n"
 "-membedded-pic\t\tgenerate embedded position independent code\n"
@@ -5556,7 +5510,7 @@ msgid ""
 "\t\t\timplicitly with the gp register [default 8]\n"
 msgstr ""
 
-#: config/tc-mips.c:9218
+#: config/tc-mips.c:9226
 msgid ""
 "-mips1\t\t\tgenerate MIPS ISA I instructions\n"
 "-mips2\t\t\tgenerate MIPS ISA II instructions\n"
@@ -5568,20 +5522,20 @@ msgid ""
 "-mcpu=CPU\t\tgenerate code for CPU, where CPU is one of:\n"
 msgstr ""
 
-#: config/tc-mips.c:9249
+#: config/tc-mips.c:9257
 msgid ""
 "-mCPU\t\t\tequivalent to -mcpu=CPU.\n"
 "-no-mCPU\t\tdon't generate code specific to CPU.\n"
 "\t\t\tFor -mCPU and -no-mCPU, CPU must be one of:\n"
 msgstr ""
 
-#: config/tc-mips.c:9262
+#: config/tc-mips.c:9270
 msgid ""
 "-mips16\t\t\tgenerate mips16 instructions\n"
 "-no-mips16\t\tdo not generate mips16 instructions\n"
 msgstr ""
 
-#: config/tc-mips.c:9265
+#: config/tc-mips.c:9273
 msgid ""
 "-O0\t\t\tremove unneeded NOPs, do not swap branches\n"
 "-O\t\t\tremove unneeded NOPs and swap branches\n"
@@ -5590,7 +5544,7 @@ msgid ""
 "--break, --no-trap\tbreak exception on div by 0 and mult overflow\n"
 msgstr ""
 
-#: config/tc-mips.c:9272
+#: config/tc-mips.c:9280
 msgid ""
 "-KPIC, -call_shared\tgenerate SVR4 position independent code\n"
 "-non_shared\t\tdo not generate position independent code\n"
@@ -5599,170 +5553,170 @@ msgid ""
 "-64\t\t\tcreate 64 bit object file\n"
 msgstr ""
 
-#: config/tc-mips.c:9329
+#: config/tc-mips.c:9337
 #, c-format
 msgid "Unsupported reloc size %d"
 msgstr ""
 
-#: config/tc-mips.c:9432
+#: config/tc-mips.c:9440
 msgid "Unmatched %%hi reloc"
 msgstr ""
 
-#: config/tc-mips.c:9556
+#: config/tc-mips.c:9563
 msgid "Invalid PC relative reloc"
 msgstr ""
 
-#: config/tc-mips.c:9666 config/tc-sparc.c:3101 config/tc-sparc.c:3108
+#: config/tc-mips.c:9673 config/tc-sparc.c:3101 config/tc-sparc.c:3108
 #: config/tc-sparc.c:3115 config/tc-sparc.c:3122 config/tc-sparc.c:3129
 #: config/tc-sparc.c:3138 config/tc-sparc.c:3149 config/tc-sparc.c:3175
-#: config/tc-sparc.c:3203 write.c:984 write.c:1048
+#: config/tc-sparc.c:3203 write.c:992 write.c:1056
 msgid "relocation overflow"
 msgstr ""
 
-#: config/tc-mips.c:9682
+#: config/tc-mips.c:9689
 #, c-format
 msgid "Branch to odd address (%lx)"
 msgstr ""
 
-#: config/tc-mips.c:9846
+#: config/tc-mips.c:9853
 #, c-format
 msgid "%08lx  UNDEFINED\n"
 msgstr ""
 
-#: config/tc-mips.c:9912
+#: config/tc-mips.c:9919
 msgid "Alignment negative: 0 assumed."
 msgstr ""
 
-#: config/tc-mips.c:10000
+#: config/tc-mips.c:10007
 msgid "No read only data section in this object file format"
 msgstr ""
 
-#: config/tc-mips.c:10023
+#: config/tc-mips.c:10030
 msgid "Global pointers not supported; recompile -G 0"
 msgstr ""
 
-#: config/tc-mips.c:10109
+#: config/tc-mips.c:10116
 #, c-format
 msgid "%s: no such section"
 msgstr ""
 
-#: config/tc-mips.c:10146
+#: config/tc-mips.c:10153
 #, c-format
 msgid ".option pic%d not supported"
 msgstr ""
 
-#: config/tc-mips.c:10157
+#: config/tc-mips.c:10164
 #, c-format
 msgid "Unrecognized option \"%s\""
 msgstr ""
 
-#: config/tc-mips.c:10220
+#: config/tc-mips.c:10227
 msgid "`noreorder' must be set before `nomacro'"
 msgstr ""
 
-#: config/tc-mips.c:10262
+#: config/tc-mips.c:10269
 msgid "unknown ISA level"
 msgstr ""
 
-#: config/tc-mips.c:10284
+#: config/tc-mips.c:10291
 msgid ".set pop with no .set push"
 msgstr ""
 
-#: config/tc-mips.c:10308
+#: config/tc-mips.c:10315
 #, c-format
 msgid "Tried to set unrecognized symbol: %s\n"
 msgstr ""
 
-#: config/tc-mips.c:10358
+#: config/tc-mips.c:10365
 msgid ".cpload not in noreorder section"
 msgstr ""
 
-#: config/tc-mips.c:10440
+#: config/tc-mips.c:10447
 msgid "Unsupported use of .gpword"
 msgstr ""
 
-#: config/tc-mips.c:10577
+#: config/tc-mips.c:10584
 msgid "expected `$'"
 msgstr ""
 
-#: config/tc-mips.c:10585
+#: config/tc-mips.c:10592
 msgid "Bad register number"
 msgstr ""
 
-#: config/tc-mips.c:10601
+#: config/tc-mips.c:10608
 msgid "Unrecognized register name"
 msgstr ""
 
-#: config/tc-mips.c:10800
+#: config/tc-mips.c:10807
 msgid "unsupported PC relative reference to different section"
 msgstr ""
 
-#: config/tc-mips.c:10909
+#: config/tc-mips.c:10916
 msgid "unsupported relocation"
 msgstr ""
 
-#: config/tc-mips.c:11014
+#: config/tc-mips.c:11020
 msgid "AT used after \".set noat\" or macro used after \".set nomacro\""
 msgstr ""
 
-#: config/tc-mips.c:11077
+#: config/tc-mips.c:11083
 msgid "Double check fx_r_type in tc-mips.c:tc_gen_reloc"
 msgstr ""
 
-#: config/tc-mips.c:11589
+#: config/tc-mips.c:11596
 msgid "missing `.end' at end of assembly"
 msgstr ""
 
-#: config/tc-mips.c:11604
+#: config/tc-mips.c:11611
 msgid "Expected simple number."
 msgstr ""
 
-#: config/tc-mips.c:11630
+#: config/tc-mips.c:11637
 #, c-format
 msgid " *input_line_pointer == '%c' 0x%02x\n"
 msgstr ""
 
-#: config/tc-mips.c:11632
+#: config/tc-mips.c:11639
 msgid "Invalid number"
 msgstr ""
 
-#: config/tc-mips.c:11686
+#: config/tc-mips.c:11693
 msgid ".end not in text section"
 msgstr ""
 
-#: config/tc-mips.c:11690
+#: config/tc-mips.c:11697
 msgid ".end directive without a preceding .ent directive."
 msgstr ""
 
-#: config/tc-mips.c:11699
+#: config/tc-mips.c:11706
 msgid ".end symbol does not match .ent symbol."
 msgstr ""
 
-#: config/tc-mips.c:11702
+#: config/tc-mips.c:11709
 msgid ".end directive missing or unknown symbol"
 msgstr ""
 
-#: config/tc-mips.c:11777
+#: config/tc-mips.c:11784
 msgid ".ent or .aent not in text section."
 msgstr ""
 
-#: config/tc-mips.c:11780
+#: config/tc-mips.c:11787
 msgid "missing `.end'"
 msgstr ""
 
-#: config/tc-mips.c:11813 ecoff.c:3205
+#: config/tc-mips.c:11820 ecoff.c:3205
 msgid ".frame outside of .ent"
 msgstr ""
 
-#: config/tc-mips.c:11824 ecoff.c:3216
+#: config/tc-mips.c:11831 ecoff.c:3216
 msgid "Bad .frame directive"
 msgstr ""
 
-#: config/tc-mips.c:11854
+#: config/tc-mips.c:11861
 msgid ".mask/.fmask outside of .ent"
 msgstr ""
 
-#: config/tc-mips.c:11861
+#: config/tc-mips.c:11868
 msgid "Bad .mask/.fmask directive"
 msgstr ""
 
@@ -5772,12 +5726,24 @@ msgid ""
 "none yet\n"
 msgstr ""
 
-#: config/tc-mn10200.c:807 config/tc-mn10300.c:953 config/tc-ppc.c:1733
+#: config/tc-mn10200.c:807 config/tc-mn10300.c:953 config/tc-ppc.c:1736
 #: config/tc-v850.c:1728
 #, c-format
 msgid "Unrecognized opcode: `%s'"
 msgstr ""
 
+#: config/tc-mn10200.c:1050 config/tc-mn10300.c:1476 config/tc-ppc.c:2097
+#: config/tc-v850.c:2152
+#, c-format
+msgid "junk at end of line: `%s'"
+msgstr ""
+
+#: config/tc-mn10200.c:1374 config/tc-mn10300.c:2045 config/tc-ppc.c:1224
+#: config/tc-v850.c:1656
+#, c-format
+msgid "operand out of range (%s not between %ld and %ld)"
+msgstr ""
+
 #: config/tc-mn10300.c:542
 msgid ""
 "MN10300 options:\n"
@@ -5980,12 +5946,12 @@ msgid ""
 "-big\t\t\tgenerate big endian code\n"
 msgstr ""
 
-#: config/tc-pj.c:458 config/tc-sh.c:2869 config/tc-sh.c:2876
-#: config/tc-sh.c:2883 config/tc-sh.c:2890
+#: config/tc-pj.c:458 config/tc-sh.c:2899 config/tc-sh.c:2906
+#: config/tc-sh.c:2913 config/tc-sh.c:2920
 msgid "pcrel too far"
 msgstr ""
 
-#: config/tc-pj.c:526 config/tc-sh.c:2981
+#: config/tc-pj.c:526 config/tc-sh.c:3011
 msgid "offset out of range"
 msgstr ""
 
@@ -5997,12 +5963,12 @@ msgstr ""
 msgid "estimate size\n"
 msgstr ""
 
-#: config/tc-ppc.c:923
+#: config/tc-ppc.c:926
 #, c-format
 msgid "invalid switch -m%s"
 msgstr ""
 
-#: config/tc-ppc.c:960
+#: config/tc-ppc.c:963
 msgid ""
 "PowerPC options:\n"
 "-u\t\t\tignored\n"
@@ -6019,7 +5985,7 @@ msgid ""
 "-mno-regnames\t\tDo not allow symbolic names for registers\n"
 msgstr ""
 
-#: config/tc-ppc.c:975
+#: config/tc-ppc.c:978
 msgid ""
 "-mrelocatable\t\tsupport for GCC's -mrelocatble option\n"
 "-mrelocatable-lib\tsupport for GCC's -mrelocatble-lib option\n"
@@ -6033,202 +5999,210 @@ msgid ""
 "-Qy, -Qn\t\tignored\n"
 msgstr ""
 
-#: config/tc-ppc.c:1010
+#: config/tc-ppc.c:1013
 #, c-format
 msgid "Unknown default cpu = %s, os = %s"
 msgstr ""
 
-#: config/tc-ppc.c:1035
+#: config/tc-ppc.c:1038
 msgid "Neither Power nor PowerPC opcodes were selected."
 msgstr ""
 
-#: config/tc-ppc.c:1114
+#: config/tc-ppc.c:1117
 #, c-format
 msgid "Internal assembler error for instruction %s"
 msgstr ""
 
-#: config/tc-ppc.c:1133
+#: config/tc-ppc.c:1136
 #, c-format
 msgid "Internal assembler error for macro %s"
 msgstr ""
 
-#: config/tc-ppc.c:1343
+#: config/tc-ppc.c:1346
 msgid "identifier+constant@got means identifier@got+constant"
 msgstr ""
 
-#: config/tc-ppc.c:1397 config/tc-sh.c:341 config/tc-sh.c:369
+#: config/tc-ppc.c:1400 config/tc-sh.c:341 config/tc-sh.c:369
 #, c-format
 msgid "%s relocations do not fit in %d bytes\n"
 msgstr ""
 
-#: config/tc-ppc.c:1497
+#: config/tc-ppc.c:1500
 #, c-format
 msgid "Length of .lcomm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
 
-#: config/tc-ppc.c:1579
+#: config/tc-ppc.c:1582
 msgid "Relocation cannot be done when using -mrelocatable"
 msgstr ""
 
-#: config/tc-ppc.c:1660
+#: config/tc-ppc.c:1663
 #, c-format
 msgid "syntax error: invalid toc specifier `%s'"
 msgstr ""
 
-#: config/tc-ppc.c:1674
+#: config/tc-ppc.c:1677
 #, c-format
 msgid "syntax error: expected `]', found  `%c'"
 msgstr ""
 
-#: config/tc-ppc.c:1909
+#: config/tc-ppc.c:1912
 msgid "[tocv] symbol is not a toc symbol"
 msgstr ""
 
-#: config/tc-ppc.c:1920
+#: config/tc-ppc.c:1923
 msgid "Unimplemented toc32 expression modifier"
 msgstr ""
 
-#: config/tc-ppc.c:1925
+#: config/tc-ppc.c:1928
 msgid "Unimplemented toc64 expression modifier"
 msgstr ""
 
-#: config/tc-ppc.c:1929
+#: config/tc-ppc.c:1932
 #, c-format
 msgid "Unexpected return value [%d] from parse_toc_entry!\n"
 msgstr ""
 
-#: config/tc-ppc.c:2082
+#: config/tc-ppc.c:2085
 #, c-format
 msgid "syntax error; found `%c' but expected `%c'"
 msgstr ""
 
-#: config/tc-ppc.c:2190
+#: config/tc-ppc.c:2197
 msgid "wrong number of operands"
 msgstr ""
 
-#: config/tc-ppc.c:2246
+#: config/tc-ppc.c:2253
 msgid "Bad .section directive: want a,w,x,e in string"
 msgstr ""
 
-#: config/tc-ppc.c:2360
+#: config/tc-ppc.c:2367
 msgid "missing size"
 msgstr ""
 
-#: config/tc-ppc.c:2369
+#: config/tc-ppc.c:2376
 msgid "negative size"
 msgstr ""
 
-#: config/tc-ppc.c:2410
+#: config/tc-ppc.c:2417
 msgid "missing real symbol name"
 msgstr ""
 
-#: config/tc-ppc.c:2431
+#: config/tc-ppc.c:2438
 msgid "attempt to redefine symbol"
 msgstr ""
 
-#: config/tc-ppc.c:2665
+#: config/tc-ppc.c:2672
 msgid "The XCOFF file format does not support arbitrary sections"
 msgstr ""
 
-#: config/tc-ppc.c:2773 config/tc-ppc.c:3298 read.c:3004
+#: config/tc-ppc.c:2749
+msgid "missing rename string"
+msgstr ""
+
+#: config/tc-ppc.c:2780 config/tc-ppc.c:3305 read.c:2992
 msgid "missing value"
 msgstr ""
 
-#: config/tc-ppc.c:2791
+#: config/tc-ppc.c:2798
 msgid "illegal .stabx expression; zero assumed"
 msgstr ""
 
-#: config/tc-ppc.c:2823
+#: config/tc-ppc.c:2830
 msgid "missing class"
 msgstr ""
 
-#: config/tc-ppc.c:2832
+#: config/tc-ppc.c:2839
 msgid "missing type"
 msgstr ""
 
-#: config/tc-ppc.c:2893
+#: config/tc-ppc.c:2900
 msgid "missing symbol name"
 msgstr ""
 
-#: config/tc-ppc.c:3069
+#: config/tc-ppc.c:3076
 msgid "nested .bs blocks"
 msgstr ""
 
-#: config/tc-ppc.c:3102
+#: config/tc-ppc.c:3109
 msgid ".es without preceding .bs"
 msgstr ""
 
-#: config/tc-ppc.c:3290
+#: config/tc-ppc.c:3297
 msgid "non-constant byte count"
 msgstr ""
 
-#: config/tc-ppc.c:3335
+#: config/tc-ppc.c:3342
 msgid ".tc not in .toc section"
 msgstr ""
 
-#: config/tc-ppc.c:3354
+#: config/tc-ppc.c:3361
 msgid ".tc with no label"
 msgstr ""
 
-#: config/tc-ppc.c:3429
+#: config/tc-ppc.c:3436
 msgid "No previous section to return to. Directive ignored."
 msgstr ""
 
 #. Section Contents
 #. unknown
-#: config/tc-ppc.c:3848
+#: config/tc-ppc.c:3855
 msgid "Unsupported section attribute -- 'a'"
 msgstr ""
 
-#: config/tc-ppc.c:4038
+#: config/tc-ppc.c:4045
 msgid "bad symbol suffix"
 msgstr ""
 
-#: config/tc-ppc.c:4131
+#: config/tc-ppc.c:4138
 msgid "Unrecognized symbol suffix"
 msgstr ""
 
-#: config/tc-ppc.c:4213
+#: config/tc-ppc.c:4220
 msgid "two .function pseudo-ops with no intervening .ef"
 msgstr ""
 
-#: config/tc-ppc.c:4226
+#: config/tc-ppc.c:4233
 msgid ".ef with no preceding .function"
 msgstr ""
 
-#: config/tc-ppc.c:4354
+#: config/tc-ppc.c:4361
 #, c-format
 msgid "warning: symbol %s has no csect"
 msgstr ""
 
-#: config/tc-ppc.c:4655
+#: config/tc-ppc.c:4662
 msgid "symbol in .toc does not match any .tc"
 msgstr ""
 
-#: config/tc-ppc.c:4952
+#: config/tc-ppc.c:4956 config/tc-v850.c:2431
+msgid "unresolved expression that must be resolved"
+msgstr ""
+
+#: config/tc-ppc.c:4959
 msgid "unsupported relocation type"
 msgstr ""
 
-#: config/tc-ppc.c:5014
+#: config/tc-ppc.c:5021
 #, c-format
 msgid "cannot emit PC relative %s relocation against %s"
 msgstr ""
 
-#: config/tc-ppc.c:5019
+#: config/tc-ppc.c:5026
 #, c-format
 msgid "cannot emit PC relative %s relocation"
 msgstr ""
 
-#: config/tc-ppc.c:5081
+#: config/tc-ppc.c:5088
 msgid "must branch to an address a multiple of 4"
 msgstr ""
 
-#: config/tc-ppc.c:5085
+#: config/tc-ppc.c:5092
 #, c-format
 msgid "@local or @plt branch destination is too far away, %ld bytes"
 msgstr ""
 
-#: config/tc-ppc.c:5109
+#: config/tc-ppc.c:5116
 #, c-format
 msgid "Gas failure, reloc value %d\n"
 msgstr ""
@@ -6389,12 +6363,12 @@ msgstr ""
 msgid "overflow in branch to %s; converted into longer instruction sequence"
 msgstr ""
 
-#: config/tc-sh.c:2581 config/tc-sh.c:2609 config/tc-sparc.c:4084
-#: config/tc-sparc.c:4103
+#: config/tc-sh.c:2581 config/tc-sh.c:2629 config/tc-sparc.c:4084
+#: config/tc-sparc.c:4109
 msgid "misaligned data"
 msgstr ""
 
-#: config/tc-sh.c:2973
+#: config/tc-sh.c:3003
 msgid "misaligned offset"
 msgstr ""
 
@@ -6416,11 +6390,6 @@ msgstr ""
 msgid "invalid architecture -A%s"
 msgstr ""
 
-#: config/tc-sparc.c:548
-#, c-format
-msgid "No compiled in support for %d bit object file format"
-msgstr ""
-
 #: config/tc-sparc.c:585
 msgid "Unrecognized option following -K"
 msgstr ""
@@ -6679,6 +6648,11 @@ msgstr ""
 msgid "bad or unhandled relocation type: 0x%02x"
 msgstr ""
 
+#: config/tc-sparc.c:3380
+#, c-format
+msgid "internal error: can't export reloc type %d (`%s')"
+msgstr ""
+
 #: config/tc-sparc.c:3552
 msgid "bad .reserve segment -- expected BSS segment"
 msgstr ""
@@ -6717,11 +6691,11 @@ msgstr ""
 msgid "Register symbol %s already defined."
 msgstr ""
 
-#: config/tc-sparc.h:53
+#: config/tc-sparc.h:54
 msgid "sparc convert_frag\n"
 msgstr ""
 
-#: config/tc-sparc.h:55
+#: config/tc-sparc.h:56
 msgid "estimate_size_before_relax called"
 msgstr ""
 
@@ -7925,15 +7899,20 @@ msgstr ""
 msgid "Can't close `%s'"
 msgstr ""
 
-#: dwarf2dbg.c:338 dwarf2dbg.c:372
+#: dwarf2dbg.c:345 dwarf2dbg.c:379
 msgid "File number less than zero"
 msgstr ""
 
-#: dwarf2dbg.c:378
+#: dwarf2dbg.c:385
 #, c-format
 msgid "Unassigned file number %ld"
 msgstr ""
 
+#: dwarf2dbg.c:1255 dwarf2dbg.c:1263 dwarf2dbg.c:1271 dwarf2dbg.c:1284
+#: dwarf2dbg.c:1291
+msgid "dwarf2 is not supported for this object file format"
+msgstr ""
+
 #: ecoff.c:1555
 #, c-format
 msgid "String too big (%lu bytes)"
@@ -8182,7 +8161,7 @@ msgstr ""
 msgid "Missing '%c' assumed"
 msgstr ""
 
-#: expr.c:1024 read.c:3881
+#: expr.c:1024 read.c:3869
 msgid "EBCDIC constants are not supported"
 msgstr ""
 
@@ -8223,7 +8202,7 @@ msgstr ""
 msgid "right operand is a float; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1793 symbols.c:1086
+#: expr.c:1793 symbols.c:1089
 msgid "division by zero"
 msgstr ""
 
@@ -8620,21 +8599,21 @@ msgstr ""
 msgid "Error:"
 msgstr ""
 
-#: listing.c:1124
+#: listing.c:1125
 #, c-format
 msgid "can't open list file: %s"
 msgstr ""
 
-#: listing.c:1148
+#: listing.c:1149
 #, c-format
 msgid "error closing list file: %s"
 msgstr ""
 
-#: listing.c:1227
+#: listing.c:1228
 msgid "strange paper height, set to no form"
 msgstr ""
 
-#: listing.c:1293
+#: listing.c:1294
 msgid "New line in title"
 msgstr ""
 
@@ -8741,302 +8720,302 @@ msgstr ""
 msgid "Can't continue"
 msgstr ""
 
-#: read.c:452
+#: read.c:445
 #, c-format
 msgid "error constructing %s pseudo-op table: %s"
 msgstr ""
 
-#: read.c:809
+#: read.c:802
 #, c-format
 msgid "Unknown pseudo-op:  `%s'"
 msgstr ""
 
-#: read.c:941
+#: read.c:934
 #, c-format
 msgid "label \"%d$\" redefined"
 msgstr ""
 
-#: read.c:1159
+#: read.c:1152
 msgid ".abort detected.  Abandoning ship."
 msgstr ""
 
-#: read.c:1250 read.c:2039
+#: read.c:1238 read.c:2027
 msgid "Alignment not a power of 2"
 msgstr ""
 
-#: read.c:1259
+#: read.c:1247
 #, c-format
 msgid "Alignment too large: %u assumed"
 msgstr ""
 
-#: read.c:1291
+#: read.c:1279
 msgid "expected fill pattern missing"
 msgstr ""
 
-#: read.c:1495
+#: read.c:1483
 #, c-format
 msgid "attempt to re-define symbol `%s'"
 msgstr ""
 
 #. Some of the back ends can't deal with non-positive line numbers.
 #. Besides, it's silly.
-#: read.c:1619
+#: read.c:1607
 #, c-format
 msgid "Line numbers must be positive; line number %d rejected."
 msgstr ""
 
-#: read.c:1647
+#: read.c:1635
 msgid "start address not supported"
 msgstr ""
 
-#: read.c:1657
+#: read.c:1645
 msgid ".err encountered"
 msgstr ""
 
-#: read.c:1676 read.c:1678
+#: read.c:1664 read.c:1666
 #, c-format
 msgid ".fail %ld encountered"
 msgstr ""
 
-#: read.c:1715
+#: read.c:1703
 #, c-format
 msgid ".fill size clamped to %d."
 msgstr ""
 
-#: read.c:1720
+#: read.c:1708
 msgid "Size negative: .fill ignored."
 msgstr ""
 
-#: read.c:1726
+#: read.c:1714
 msgid "Repeat < 0, .fill ignored"
 msgstr ""
 
-#: read.c:1886
+#: read.c:1874
 #, c-format
 msgid "unrecognized .linkonce type `%s'"
 msgstr ""
 
-#: read.c:1899 read.c:1925
+#: read.c:1887 read.c:1913
 msgid ".linkonce is not supported for this object file format"
 msgstr ""
 
-#: read.c:1921
+#: read.c:1909
 #, c-format
 msgid "bfd_set_section_flags: %s"
 msgstr ""
 
-#: read.c:1990
+#: read.c:1978
 #, c-format
 msgid "error setting flags for \".sbss\": %s"
 msgstr ""
 
-#: read.c:2013
+#: read.c:2001
 msgid "Expected comma after size"
 msgstr ""
 
-#: read.c:2023
+#: read.c:2011
 msgid "Missing alignment"
 msgstr ""
 
-#: read.c:2174
+#: read.c:2162
 msgid "bad expression"
 msgstr ""
 
-#: read.c:2311
+#: read.c:2299
 #, c-format
 msgid "attempt to redefine pseudo-op `%s' ignored"
 msgstr ""
 
-#: read.c:2377
+#: read.c:2365
 #, c-format
 msgid "invalid segment \"%s\"; segment \"%s\" assumed"
 msgstr ""
 
-#: read.c:2383
+#: read.c:2371
 msgid "ignoring fill value in absolute section"
 msgstr ""
 
-#: read.c:2386
+#: read.c:2374
 msgid "only constant offsets supported in absolute section"
 msgstr ""
 
-#: read.c:2418
+#: read.c:2406
 msgid "MRI style ORG pseudo-op not supported"
 msgstr ""
 
-#: read.c:2507
+#: read.c:2495
 msgid "unrecognized section type"
 msgstr ""
 
-#: read.c:2575
+#: read.c:2563
 #, c-format
 msgid "unrecognized section type `%s'"
 msgstr ""
 
-#: read.c:2589
+#: read.c:2577
 msgid "absolute sections are not supported"
 msgstr ""
 
-#: read.c:2604
+#: read.c:2592
 #, c-format
 msgid "unrecognized section command `%s'"
 msgstr ""
 
-#: read.c:2692
+#: read.c:2680
 #, c-format
 msgid "%s without %s"
 msgstr ""
 
-#: read.c:2893
+#: read.c:2881
 msgid "Unsupported variable size or fill value"
 msgstr ""
 
-#: read.c:2918
+#: read.c:2906
 msgid ".space repeat count is zero, ignored"
 msgstr ""
 
-#: read.c:2920
+#: read.c:2908
 msgid ".space repeat count is negative, ignored"
 msgstr ""
 
-#: read.c:2949
+#: read.c:2937
 msgid "space allocation too complex in absolute section"
 msgstr ""
 
-#: read.c:2955
+#: read.c:2943
 msgid "space allocation too complex in common section"
 msgstr ""
 
-#: read.c:3043 read.c:4126
+#: read.c:3031 read.c:4114
 #, c-format
 msgid "Bad floating literal: %s"
 msgstr ""
 
-#: read.c:3116
+#: read.c:3104
 #, c-format
 msgid "Rest of line ignored. First ignored character is `%c'."
 msgstr ""
 
-#: read.c:3119
+#: read.c:3107
 #, c-format
 msgid "Rest of line ignored. First ignored character valued 0x%x."
 msgstr ""
 
-#: read.c:3170
+#: read.c:3158
 msgid "illegal expression; zero assumed"
 msgstr ""
 
-#: read.c:3172
+#: read.c:3160
 msgid "missing expression; zero assumed"
 msgstr ""
 
-#: read.c:3343
+#: read.c:3331
 msgid "rva without symbol"
 msgstr ""
 
-#: read.c:3467
+#: read.c:3455
 msgid "attempt to store value in absolute section"
 msgstr ""
 
-#: read.c:3505 read.c:4403
+#: read.c:3493 read.c:4391
 msgid "zero assumed for missing expression"
 msgstr ""
 
-#: read.c:3517 read.c:4415
+#: read.c:3505 read.c:4403
 msgid "register value used as expression"
 msgstr ""
 
 #. Leading bits contain both 0s & 1s.
-#: read.c:3607
+#: read.c:3595
 #, c-format
 msgid "Value 0x%lx truncated to 0x%lx."
 msgstr ""
 
-#: read.c:3623
+#: read.c:3611
 #, c-format
 msgid "Bignum truncated to %d bytes"
 msgstr ""
 
-#: read.c:3700
+#: read.c:3688
 #, c-format
 msgid "unsupported BFD relocation size %u"
 msgstr ""
 
-#: read.c:3790
+#: read.c:3778
 msgid "using a bit field width of zero"
 msgstr ""
 
-#: read.c:3798
+#: read.c:3786
 #, c-format
 msgid "field width \"%s\" too complex for a bitfield"
 msgstr ""
 
-#: read.c:3806
+#: read.c:3794
 #, c-format
 msgid "field width %lu too big to fit in %d bytes: truncated to %d bits"
 msgstr ""
 
-#: read.c:3828
+#: read.c:3816
 #, c-format
 msgid "field value \"%s\" too complex for a bitfield"
 msgstr ""
 
-#: read.c:3954
+#: read.c:3942
 msgid "Unresolvable or nonpositive repeat count; using 1"
 msgstr ""
 
-#: read.c:4005
+#: read.c:3993
 #, c-format
 msgid "Unknown floating type type '%c'"
 msgstr ""
 
-#: read.c:4027
+#: read.c:4015
 msgid "Floating point constant too large"
 msgstr ""
 
-#: read.c:4148
+#: read.c:4136
 msgid "unresolvable or nonpositive repeat count; using 1"
 msgstr ""
 
-#: read.c:4546
+#: read.c:4534
 msgid "Expected <nn>"
 msgstr ""
 
 #. To be compatible with BSD 4.2 as: give the luser a linefeed!!
-#: read.c:4579 read.c:4665
+#: read.c:4567 read.c:4653
 msgid "Unterminated string: Newline inserted."
 msgstr ""
 
-#: read.c:4673
+#: read.c:4661
 msgid "Bad escaped character in string, '?' assumed"
 msgstr ""
 
-#: read.c:4699
+#: read.c:4687
 msgid "expected address expression; zero assumed"
 msgstr ""
 
-#: read.c:4719
+#: read.c:4707
 #, c-format
 msgid "symbol \"%s\" undefined; zero assumed"
 msgstr ""
 
-#: read.c:4722
+#: read.c:4710
 msgid "some symbol undefined; zero assumed"
 msgstr ""
 
-#: read.c:4775
+#: read.c:4763
 msgid "This string may not contain '\\0'"
 msgstr ""
 
-#: read.c:4812
+#: read.c:4800
 msgid "Missing string"
 msgstr ""
 
-#: read.c:5034
+#: read.c:5022
 msgid "missing .func"
 msgstr ""
 
-#: read.c:5051
+#: read.c:5039
 msgid ".endfunc missing for previous .func"
 msgstr ""
 
@@ -9058,151 +9037,151 @@ msgstr ""
 msgid "Attempt to switch to nonexistent segment \"%s\""
 msgstr ""
 
-#: symbols.c:354 symbols.c:453
+#: symbols.c:357 symbols.c:456
 #, c-format
 msgid "Symbol %s already defined."
 msgstr ""
 
-#: symbols.c:439
+#: symbols.c:442
 #, c-format
 msgid "Symbol \"%s\" is already defined as \"%s\"/%s%ld."
 msgstr ""
 
-#: symbols.c:516 symbols.c:523
+#: symbols.c:519 symbols.c:526
 #, c-format
 msgid "Inserting \"%s\" into symbol table failed: %s"
 msgstr ""
 
-#: symbols.c:869
+#: symbols.c:872
 #, c-format
 msgid "Symbol definition loop encountered at %s"
 msgstr ""
 
-#: symbols.c:1047 symbols.c:1051
+#: symbols.c:1050 symbols.c:1054
 #, c-format
 msgid "undefined symbol %s in operation"
 msgstr ""
 
-#: symbols.c:1056
+#: symbols.c:1059
 msgid "invalid section for operation"
 msgstr ""
 
-#: symbols.c:1061 symbols.c:1065
+#: symbols.c:1064 symbols.c:1068
 #, c-format
 msgid "undefined symbol %s in operation setting %s"
 msgstr ""
 
-#: symbols.c:1070
+#: symbols.c:1073
 #, c-format
 msgid "invalid section for operation setting %s"
 msgstr ""
 
-#: symbols.c:1088
+#: symbols.c:1091
 #, c-format
 msgid "division by zero when setting %s"
 msgstr ""
 
-#: symbols.c:1160 write.c:1926
+#: symbols.c:1163 write.c:1945
 #, c-format
 msgid "can't resolve value for symbol \"%s\""
 msgstr ""
 
-#: symbols.c:1527
+#: symbols.c:1533
 #, c-format
 msgid "\"%d\" (instance number %d of a %s label)"
 msgstr ""
 
-#: symbols.c:1577
+#: symbols.c:1589
 #, c-format
 msgid "Attempt to get value of unresolved symbol %s"
 msgstr ""
 
-#: write.c:178
+#: write.c:172
 #, c-format
 msgid "field fx_size too small to hold %d"
 msgstr ""
 
-#: write.c:315
+#: write.c:309
 msgid "rva not supported"
 msgstr ""
 
-#: write.c:509
+#: write.c:517
 #, c-format
 msgid "attempt to .org/.space backwards? (%ld)"
 msgstr ""
 
-#: write.c:987
+#: write.c:995
 msgid "relocation out of range"
 msgstr ""
 
-#: write.c:990
+#: write.c:998
 #, c-format
 msgid "%s:%u: bad return from bfd_install_relocation: %x"
 msgstr ""
 
-#: write.c:1035
+#: write.c:1043
 msgid "internal error: fixup not contained within frag"
 msgstr ""
 
-#: write.c:1051
+#: write.c:1059
 #, c-format
 msgid "%s:%u: bad return from bfd_install_relocation"
 msgstr ""
 
-#: write.c:1138 write.c:1162
+#: write.c:1146 write.c:1170
 #, c-format
 msgid "FATAL: Can't write %s"
 msgstr ""
 
-#: write.c:1194
+#: write.c:1202
 msgid "Cannot write to output file."
 msgstr ""
 
-#: write.c:1432
+#: write.c:1451
 #, c-format
 msgid "%d error%s, %d warning%s, generating bad object file.\n"
 msgstr ""
 
-#: write.c:1439
+#: write.c:1458
 #, c-format
 msgid "%d error%s, %d warning%s, no object file generated.\n"
 msgstr ""
 
-#: write.c:1863
+#: write.c:1882
 #, c-format
 msgid "local label %s is not defined"
 msgstr ""
 
-#: write.c:2167
+#: write.c:2187
 #, c-format
 msgid "alignment padding (%lu bytes) not a multiple of %ld"
 msgstr ""
 
-#: write.c:2277
+#: write.c:2297
 #, c-format
 msgid ".word %s-%s+%s didn't fit"
 msgstr ""
 
-#: write.c:2357
+#: write.c:2378
 msgid "attempt to .org backwards ignored"
 msgstr ""
 
-#: write.c:2381
+#: write.c:2402
 msgid ".space specifies non-absolute value"
 msgstr ""
 
-#: write.c:2385
+#: write.c:2406
 msgid ".space or .fill with negative value, ignored"
 msgstr ""
 
-#: write.c:2636
+#: write.c:2657
 #, c-format
 msgid ""
 "Subtraction of two symbols in different sections \"%s\" {%s section} - "
 "\"%s\" {%s section} at file address %s."
 msgstr ""
 
-#: write.c:2790
+#: write.c:2811
 #, c-format
 msgid "Value of %s too large for field of %d bytes at %s"
 msgstr ""
diff --git a/gas/struc-symbol.h b/gas/struc-symbol.h
index 1560f9a..485ba5a 100644
--- a/gas/struc-symbol.h
+++ b/gas/struc-symbol.h
@@ -22,6 +22,12 @@
 #ifndef __struc_symbol_h__
 #define __struc_symbol_h__
 
+#ifdef BFD_ASSEMBLER
+/* The BFD code wants to walk the list in both directions.  */
+#undef  SYMBOLS_NEED_BACKPOINTERS
+#define SYMBOLS_NEED_BACKPOINTERS
+#endif
+
 /* The information we keep for a symbol.  Note that the symbol table
    holds pointers both to this and to local_symbol structures.  See
    below.  */
@@ -89,6 +95,10 @@ struct symbol
 #ifdef TC_SYMFIELD_TYPE
   TC_SYMFIELD_TYPE sy_tc;
 #endif
+
+#ifdef TARGET_SYMBOL_FIELDS
+  TARGET_SYMBOL_FIELDS
+#endif
 };
 
 #ifdef BFD_ASSEMBLER
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 1c6cd51..4f1ddd8 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,53 @@
+2001-01-11  Peter Targett <peter.targett@arccores.com>
+
+	* gas/arc/alias.*: Removed.
+	* gas/arc/branch.*: Likewise.
+	* gas/arc/insn3.*: Likewise.
+	* gas/arc/math.*: Likewise.
+	* gas/arc/sshift.*: Likewise.
+	* gas/arc/arc.exp: Simplified test process for base case
+	instruction set by adding run_dump_test cases for all base
+	instructions.
+ 	* gas/arc/adc.s, gas/arc/adc.d: New test cases and dump.
+ 	* gas/arc/add.s, gas/arc/add.d: Likewise.
+ 	* gas/arc/and.s, gas/arc/and.d: Likewise.
+ 	* gas/arc/asl.s, gas/arc/asl.d: Likewise.
+ 	* gas/arc/asr.s, gas/arc/asr.d: Likewise.
+ 	* gas/arc/b.s, gas/arc/b.d: Likewise.
+ 	* gas/arc/bic.s, gas/arc/bic.d: Likewise.
+ 	* gas/arc/bl.s, gas/arc/bl.d: Likewise.
+ 	* gas/arc/brk.s, gas/arc/brk.d: Likewise.
+ 	* gas/arc/extb.s, gas/arc/extb.d: Likewise.
+ 	* gas/arc/extw.s, gas/arc/extw.d: Likewise.
+ 	* gas/arc/flag.s, gas/arc/flag.d: Likewise.
+ 	* gas/arc/j.s, gas/arc/j.d: Likewise.
+ 	* gas/arc/jl.s, gas/arc/jl.d: Likewise.
+ 	* gas/arc/ld.s, gas/arc/ld.d: Likewise.
+ 	* gas/arc/ld2.s, gas/arc/ld2.d: Likewise.
+ 	* gas/arc/lp.s, gas/arc/lp.d: Likewise.
+ 	* gas/arc/lsr.s, gas/arc/lsr.d: Likewise.
+ 	* gas/arc/mov.s, gas/arc/mov.d: Likewise.
+ 	* gas/arc/nop.s, gas/arc/nop.d: Likewise.
+ 	* gas/arc/or.s, gas/arc/or.d: Likewise.
+ 	* gas/arc/rlc.s, gas/arc/rlc.d: Likewise.
+ 	* gas/arc/ror.s, gas/arc/ror.d: Likewise.
+ 	* gas/arc/rrc.s, gas/arc/rrc.d: Likewise.
+ 	* gas/arc/sbc.s, gas/arc/sbc.d: Likewise.
+ 	* gas/arc/sexb.s, gas/arc/sexb.d: Likewise.
+ 	* gas/arc/sexw.s, gas/arc/sexw.d: Likewise.
+ 	* gas/arc/sleep.s, gas/arc/sleep.d: Likewise.
+ 	* gas/arc/add.s, gas/arc/add.d: Likewise.
+ 	* gas/arc/st.s, gas/arc/st.d: Likewise.
+ 	* gas/arc/sub.s, gas/arc/sub.d: Likewise.
+ 	* gas/arc/swi.s, gas/arc/swi.d: Likewise.
+ 	* gas/arc/xor.s, gas/arc/xor.d: Likewise.
+	* gas/arc/warn.s: Removed warning test case for setting of flags
+	followed by conditional branch, an arc5 only feature.
+
+	* gas/ieee-fp/x930509a.exp: Skip test if target also arc*-*-*.
+
+	* gas/vtable/vtable.exp: Skip tests if target also arc*-*-*.
+
 2001-01-11  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
 
 	* gas/m68hc11/opers12.s: Add more tests for index post byte.
diff --git a/gas/testsuite/gas/arc/adc.d b/gas/testsuite/gas/arc/adc.d
new file mode 100644
index 0000000..7cb8523
--- /dev/null
+++ b/gas/testsuite/gas/arc/adc.d
@@ -0,0 +1,85 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 84 00 48 	48008400     adc        r0,r1,r2
+   4:	00 b8 4d 4b 	4b4db800     adc        gp,fp,sp
+   8:	00 3e af 4b 	4baf3e00     adc        ilink1,ilink2,blink
+   c:	00 f8 1d 4f 	4f1df800     adc        r56,r59,lp_count
+  10:	00 fe 00 48 	4800fe00     adc        r0,r1,0
+  14:	00 84 1f 48 	481f8400     adc        r0,0,r2
+  18:	00 84 e0 4f 	4fe08400     adc        0,r1,r2
+  1c:	ff ff 00 48 	4800ffff     adc        r0,r1,-1
+  20:	ff 85 1f 48 	481f85ff     adc        r0,-1,r2
+  24:	00 84 e0 4f 	4fe08400     adc        0,r1,r2
+  28:	ff fe 00 48 	4800feff     adc        r0,r1,255
+  2c:	ff 84 1f 48 	481f84ff     adc        r0,255,r2
+  30:	00 84 e0 4f 	4fe08400     adc        0,r1,r2
+  34:	00 ff 00 48 	4800ff00     adc        r0,r1,-256
+  38:	00 85 1f 48 	481f8500     adc        r0,-256,r2
+  3c:	00 84 e0 4f 	4fe08400     adc        0,r1,r2
+  40:	00 fc 00 48 	4800fc00     adc        r0,r1,0x100
+  44:	00 01 00 00 
+  48:	00 04 1f 48 	481f0400     adc        r0,0xffff_feff,r2
+  4c:	ff fe ff ff 
+  50:	ff fc 1f 48 	481ffcff     adc        r0,255,0x100
+  54:	00 01 00 00 
+  58:	ff 7e 1f 48 	481f7eff     adc        r0,0x100,255
+  5c:	00 01 00 00 
+  60:	00 fc 00 48 	4800fc00     adc        r0,r1,0
+  64:	00 00 00 00 
+			64: R_ARC_32	foo
+  68:	00 84 00 48 	48008400     adc        r0,r1,r2
+  6c:	00 0a 62 48 	48620a00     adc        r3,r4,r5
+  70:	01 90 c3 48 	48c39001     adc.z      r6,r7,r8
+  74:	01 16 25 49 	49251601     adc.z      r9,r10,r11
+  78:	02 9c 86 49 	49869c02     adc.nz     r12,r13,r14
+  7c:	02 22 e8 49 	49e82202     adc.nz     r15,r16,r17
+  80:	03 a8 49 4a 	4a49a803     adc.p      r18,r19,r20
+  84:	03 2e ab 4a 	4aab2e03     adc.p      r21,r22,r23
+  88:	04 b4 0c 4b 	4b0cb404     adc.n      r24,r25,gp
+  8c:	04 3a 6e 4b 	4b6e3a04     adc.n      fp,sp,ilink1
+  90:	05 c0 cf 4b 	4bcfc005     adc.c      ilink2,blink,r32
+  94:	05 46 31 4c 	4c314605     adc.c      r33,r34,r35
+  98:	05 cc 92 4c 	4c92cc05     adc.c      r36,r37,r38
+  9c:	06 52 f4 4c 	4cf45206     adc.nc     r39,r40,r41
+  a0:	06 d8 55 4d 	4d55d806     adc.nc     r42,r43,r44
+  a4:	06 5e b7 4d 	4db75e06     adc.nc     r45,r46,r47
+  a8:	07 e4 18 4e 	4e18e407     adc.v      r48,r49,r50
+  ac:	07 6a 1a 4f 	4f1a6a07     adc.v      r56,r52,r53
+  b0:	08 f0 1b 4f 	4f1bf008     adc.nv     r56,r55,r56
+  b4:	08 76 1d 4f 	4f1d7608     adc.nv     r56,r58,r59
+  b8:	09 00 9e 4f 	4f9e0009     adc.gt     lp_count,lp_count,r0
+  bc:	0a 7c 00 48 	48007c0a     adc.ge     r0,r0,0
+  c0:	00 00 00 00 
+  c4:	0b 02 3f 48 	483f020b     adc.lt     r1,1,r1
+  c8:	01 00 00 00 
+  cc:	0d 06 7f 48 	487f060d     adc.hi     r3,3,r3
+  d0:	03 00 00 00 
+  d4:	0e 08 df 4f 	4fdf080e     adc.ls     0,4,r4
+  d8:	04 00 00 00 
+  dc:	0f fc c2 4f 	4fc2fc0f     adc.pnz    0,r5,5
+  e0:	05 00 00 00 
+  e4:	00 85 00 48 	48008500     adc.f      r0,r1,r2
+  e8:	01 fa 00 48 	4800fa01     adc.f      r0,r1,1
+  ec:	01 84 1e 48 	481e8401     adc.f      r0,1,r2
+  f0:	00 85 e0 4f 	4fe08500     adc.f      0,r1,r2
+  f4:	00 fd 00 48 	4800fd00     adc.f      r0,r1,0x200
+  f8:	00 02 00 00 
+  fc:	00 05 1f 48 	481f0500     adc.f      r0,0x200,r2
+ 100:	00 02 00 00 
+ 104:	01 85 00 48 	48008501     adc.z.f    r0,r1,r2
+ 108:	02 fd 00 48 	4800fd02     adc.nz.f   r0,r1,0
+ 10c:	00 00 00 00 
+ 110:	0b 05 1f 48 	481f050b     adc.lt.f   r0,0,r2
+ 114:	00 00 00 00 
+ 118:	09 85 c0 4f 	4fc08509     adc.gt.f   0,r1,r2
+ 11c:	00 00 00 00 	00000000                
+ 120:	0c fd 00 48 	4800fd0c     adc.le.f   r0,r1,0x200
+ 124:	00 02 00 00 
+ 128:	0a 05 1f 48 	481f050a     adc.ge.f   r0,0x200,r2
+ 12c:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/adc.s b/gas/testsuite/gas/arc/adc.s
new file mode 100644
index 0000000..162f6b8
--- /dev/null
+++ b/gas/testsuite/gas/arc/adc.s
@@ -0,0 +1,68 @@
+# adc test
+
+	adc r0,r1,r2
+	adc r26,fp,sp
+	adc ilink1,ilink2,blink
+	adc r56,r59,lp_count
+
+	adc r0,r1,0
+	adc r0,0,r2
+	adc 0,r1,r2
+	adc r0,r1,-1
+	adc r0,-1,r2
+	adc -1,r1,r2
+	adc r0,r1,255
+	adc r0,255,r2
+	adc 255,r1,r2
+	adc r0,r1,-256
+	adc r0,-256,r2
+	adc -256,r1,r2
+
+	adc r0,r1,256
+	adc r0,-257,r2
+
+	adc r0,255,256
+	adc r0,256,255
+
+	adc r0,r1,foo
+
+	adc.al r0,r1,r2
+	adc.ra r3,r4,r5
+	adc.eq r6,r7,r8
+	adc.z r9,r10,r11
+	adc.ne r12,r13,r14
+	adc.nz r15,r16,r17
+	adc.pl r18,r19,r20
+	adc.p r21,r22,r23
+	adc.mi r24,r25,r26
+	adc.n r27,r28,r29
+	adc.cs r30,r31,r32
+	adc.c r33,r34,r35
+	adc.lo r36,r37,r38
+	adc.cc r39,r40,r41
+	adc.nc r42,r43,r44
+	adc.hs r45,r46,r47
+	adc.vs r48,r49,r50
+	adc.v r56,r52,r53
+	adc.vc r56,r55,r56
+	adc.nv r56,r58,r59
+	adc.gt r60,r60,r0
+	adc.ge r0,r0,0
+	adc.lt r1,1,r1
+	adc.hi r3,3,r3
+	adc.ls 4,4,r4
+	adc.pnz 5,r5,5
+
+	adc.f r0,r1,r2
+	adc.f r0,r1,1
+	adc.f r0,1,r2
+	adc.f 0,r1,r2
+	adc.f r0,r1,512
+	adc.f r0,512,r2
+
+	adc.eq.f r0,r1,r2
+	adc.ne.f r0,r1,0
+	adc.lt.f r0,0,r2
+	adc.gt.f 0,r1,r2
+	adc.le.f r0,r1,512
+	adc.ge.f r0,512,r2
diff --git a/gas/testsuite/gas/arc/add.d b/gas/testsuite/gas/arc/add.d
new file mode 100644
index 0000000..864bc4d
--- /dev/null
+++ b/gas/testsuite/gas/arc/add.d
@@ -0,0 +1,85 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 84 00 40 	40008400     add        r0,r1,r2
+   4:	00 b8 4d 43 	434db800     add        gp,fp,sp
+   8:	00 3e af 43 	43af3e00     add        ilink1,ilink2,blink
+   c:	00 f8 1d 47 	471df800     add        r56,r59,lp_count
+  10:	00 fe 00 40 	4000fe00     add        r0,r1,0
+  14:	00 84 1f 40 	401f8400     add        r0,0,r2
+  18:	00 84 e0 47 	47e08400     add        0,r1,r2
+  1c:	ff ff 00 40 	4000ffff     add        r0,r1,-1
+  20:	ff 85 1f 40 	401f85ff     add        r0,-1,r2
+  24:	00 84 e0 47 	47e08400     add        0,r1,r2
+  28:	ff fe 00 40 	4000feff     add        r0,r1,255
+  2c:	ff 84 1f 40 	401f84ff     add        r0,255,r2
+  30:	00 84 e0 47 	47e08400     add        0,r1,r2
+  34:	00 ff 00 40 	4000ff00     add        r0,r1,-256
+  38:	00 85 1f 40 	401f8500     add        r0,-256,r2
+  3c:	00 84 e0 47 	47e08400     add        0,r1,r2
+  40:	00 fc 00 40 	4000fc00     add        r0,r1,0x100
+  44:	00 01 00 00 
+  48:	00 04 1f 40 	401f0400     add        r0,0xffff_feff,r2
+  4c:	ff fe ff ff 
+  50:	ff fc 1f 40 	401ffcff     add        r0,255,0x100
+  54:	00 01 00 00 
+  58:	ff 7e 1f 40 	401f7eff     add        r0,0x100,255
+  5c:	00 01 00 00 
+  60:	00 fc 00 40 	4000fc00     add        r0,r1,0
+  64:	00 00 00 00 
+			64: R_ARC_32	foo
+  68:	00 84 00 40 	40008400     add        r0,r1,r2
+  6c:	00 0a 62 40 	40620a00     add        r3,r4,r5
+  70:	01 90 c3 40 	40c39001     add.z      r6,r7,r8
+  74:	01 16 25 41 	41251601     add.z      r9,r10,r11
+  78:	02 9c 86 41 	41869c02     add.nz     r12,r13,r14
+  7c:	02 22 e8 41 	41e82202     add.nz     r15,r16,r17
+  80:	03 a8 49 42 	4249a803     add.p      r18,r19,r20
+  84:	03 2e ab 42 	42ab2e03     add.p      r21,r22,r23
+  88:	04 b4 0c 43 	430cb404     add.n      r24,r25,gp
+  8c:	04 3a 6e 43 	436e3a04     add.n      fp,sp,ilink1
+  90:	05 c0 cf 43 	43cfc005     add.c      ilink2,blink,r32
+  94:	05 46 31 44 	44314605     add.c      r33,r34,r35
+  98:	05 cc 92 44 	4492cc05     add.c      r36,r37,r38
+  9c:	06 52 f4 44 	44f45206     add.nc     r39,r40,r41
+  a0:	06 d8 55 45 	4555d806     add.nc     r42,r43,r44
+  a4:	06 5e b7 45 	45b75e06     add.nc     r45,r46,r47
+  a8:	07 e4 18 46 	4618e407     add.v      r48,r49,r50
+  ac:	07 6a 1a 47 	471a6a07     add.v      r56,r52,r53
+  b0:	08 f0 1b 47 	471bf008     add.nv     r56,r55,r56
+  b4:	08 76 1d 47 	471d7608     add.nv     r56,r58,r59
+  b8:	09 00 9e 47 	479e0009     add.gt     lp_count,lp_count,r0
+  bc:	0a 7c 00 40 	40007c0a     add.ge     r0,r0,0
+  c0:	00 00 00 00 
+  c4:	0b 02 3f 40 	403f020b     add.lt     r1,1,r1
+  c8:	01 00 00 00 
+  cc:	0d 06 7f 40 	407f060d     add.hi     r3,3,r3
+  d0:	03 00 00 00 
+  d4:	0e 08 df 47 	47df080e     add.ls     0,4,r4
+  d8:	04 00 00 00 
+  dc:	0f fc c2 47 	47c2fc0f     add.pnz    0,r5,5
+  e0:	05 00 00 00 
+  e4:	00 85 00 40 	40008500     add.f      r0,r1,r2
+  e8:	01 fa 00 40 	4000fa01     add.f      r0,r1,1
+  ec:	01 84 1e 40 	401e8401     add.f      r0,1,r2
+  f0:	00 85 e0 47 	47e08500     add.f      0,r1,r2
+  f4:	00 fd 00 40 	4000fd00     add.f      r0,r1,0x200
+  f8:	00 02 00 00 
+  fc:	00 05 1f 40 	401f0500     add.f      r0,0x200,r2
+ 100:	00 02 00 00 
+ 104:	01 85 00 40 	40008501     add.z.f    r0,r1,r2
+ 108:	02 fd 00 40 	4000fd02     add.nz.f   r0,r1,0
+ 10c:	00 00 00 00 
+ 110:	0b 05 1f 40 	401f050b     add.lt.f   r0,0,r2
+ 114:	00 00 00 00 
+ 118:	09 85 c0 47 	47c08509     add.gt.f   0,r1,r2
+ 11c:	00 00 00 00 	00000000                
+ 120:	0c fd 00 40 	4000fd0c     add.le.f   r0,r1,0x200
+ 124:	00 02 00 00 
+ 128:	0a 05 1f 40 	401f050a     add.ge.f   r0,0x200,r2
+ 12c:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/add.s b/gas/testsuite/gas/arc/add.s
new file mode 100644
index 0000000..8e74971
--- /dev/null
+++ b/gas/testsuite/gas/arc/add.s
@@ -0,0 +1,68 @@
+# add test
+
+	add r0,r1,r2
+	add r26,fp,sp
+	add ilink1,ilink2,blink
+	add r56,r59,lp_count
+
+	add r0,r1,0
+	add r0,0,r2
+	add 0,r1,r2
+	add r0,r1,-1
+	add r0,-1,r2
+	add -1,r1,r2
+	add r0,r1,255
+	add r0,255,r2
+	add 255,r1,r2
+	add r0,r1,-256
+	add r0,-256,r2
+	add -256,r1,r2
+
+	add r0,r1,256
+	add r0,-257,r2
+
+	add r0,255,256
+	add r0,256,255
+
+	add r0,r1,foo
+
+	add.al r0,r1,r2
+	add.ra r3,r4,r5
+	add.eq r6,r7,r8
+	add.z r9,r10,r11
+	add.ne r12,r13,r14
+	add.nz r15,r16,r17
+	add.pl r18,r19,r20
+	add.p r21,r22,r23
+	add.mi r24,r25,r26
+	add.n r27,r28,r29
+	add.cs r30,r31,r32
+	add.c r33,r34,r35
+	add.lo r36,r37,r38
+	add.cc r39,r40,r41
+	add.nc r42,r43,r44
+	add.hs r45,r46,r47
+	add.vs r48,r49,r50
+	add.v r56,r52,r53
+	add.vc r56,r55,r56
+	add.nv r56,r58,r59
+	add.gt r60,r60,r0
+	add.ge r0,r0,0
+	add.lt r1,1,r1
+	add.hi r3,3,r3
+	add.ls 4,4,r4
+	add.pnz 5,r5,5
+
+	add.f r0,r1,r2
+	add.f r0,r1,1
+	add.f r0,1,r2
+	add.f 0,r1,r2
+	add.f r0,r1,512
+	add.f r0,512,r2
+
+	add.eq.f r0,r1,r2
+	add.ne.f r0,r1,0
+	add.lt.f r0,0,r2
+	add.gt.f 0,r1,r2
+	add.le.f r0,r1,512
+	add.ge.f r0,512,r2
diff --git a/gas/testsuite/gas/arc/and.d b/gas/testsuite/gas/arc/and.d
new file mode 100644
index 0000000..5fca082
--- /dev/null
+++ b/gas/testsuite/gas/arc/and.d
@@ -0,0 +1,85 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 84 00 60 	60008400     and        r0,r1,r2
+   4:	00 b8 4d 63 	634db800     and        gp,fp,sp
+   8:	00 3e af 63 	63af3e00     and        ilink1,ilink2,blink
+   c:	00 f8 1d 67 	671df800     and        r56,r59,lp_count
+  10:	00 fe 00 60 	6000fe00     and        r0,r1,0
+  14:	00 84 1f 60 	601f8400     and        r0,0,r2
+  18:	00 84 e0 67 	67e08400     and        0,r1,r2
+  1c:	ff ff 00 60 	6000ffff     and        r0,r1,-1
+  20:	ff 85 1f 60 	601f85ff     and        r0,-1,r2
+  24:	00 84 e0 67 	67e08400     and        0,r1,r2
+  28:	ff fe 00 60 	6000feff     and        r0,r1,255
+  2c:	ff 84 1f 60 	601f84ff     and        r0,255,r2
+  30:	00 84 e0 67 	67e08400     and        0,r1,r2
+  34:	00 ff 00 60 	6000ff00     and        r0,r1,-256
+  38:	00 85 1f 60 	601f8500     and        r0,-256,r2
+  3c:	00 84 e0 67 	67e08400     and        0,r1,r2
+  40:	00 fc 00 60 	6000fc00     and        r0,r1,0x100
+  44:	00 01 00 00 
+  48:	00 04 1f 60 	601f0400     and        r0,0xffff_feff,r2
+  4c:	ff fe ff ff 
+  50:	ff fc 1f 60 	601ffcff     and        r0,255,0x100
+  54:	00 01 00 00 
+  58:	ff 7e 1f 60 	601f7eff     and        r0,0x100,255
+  5c:	00 01 00 00 
+  60:	00 fc 00 60 	6000fc00     and        r0,r1,0
+  64:	00 00 00 00 
+			64: R_ARC_32	foo
+  68:	00 84 00 60 	60008400     and        r0,r1,r2
+  6c:	00 0a 62 60 	60620a00     and        r3,r4,r5
+  70:	01 90 c3 60 	60c39001     and.z      r6,r7,r8
+  74:	01 16 25 61 	61251601     and.z      r9,r10,r11
+  78:	02 9c 86 61 	61869c02     and.nz     r12,r13,r14
+  7c:	02 22 e8 61 	61e82202     and.nz     r15,r16,r17
+  80:	03 a8 49 62 	6249a803     and.p      r18,r19,r20
+  84:	03 2e ab 62 	62ab2e03     and.p      r21,r22,r23
+  88:	04 b4 0c 63 	630cb404     and.n      r24,r25,gp
+  8c:	04 3a 6e 63 	636e3a04     and.n      fp,sp,ilink1
+  90:	05 c0 cf 63 	63cfc005     and.c      ilink2,blink,r32
+  94:	05 46 31 64 	64314605     and.c      r33,r34,r35
+  98:	05 cc 92 64 	6492cc05     and.c      r36,r37,r38
+  9c:	06 52 f4 64 	64f45206     and.nc     r39,r40,r41
+  a0:	06 d8 55 65 	6555d806     and.nc     r42,r43,r44
+  a4:	06 5e b7 65 	65b75e06     and.nc     r45,r46,r47
+  a8:	07 e4 18 66 	6618e407     and.v      r48,r49,r50
+  ac:	07 6a 1a 67 	671a6a07     and.v      r56,r52,r53
+  b0:	08 f0 1b 67 	671bf008     and.nv     r56,r55,r56
+  b4:	08 76 1d 67 	671d7608     and.nv     r56,r58,r59
+  b8:	09 00 9e 67 	679e0009     and.gt     lp_count,lp_count,r0
+  bc:	0a 7c 00 60 	60007c0a     and.ge     r0,r0,0
+  c0:	00 00 00 00 
+  c4:	0b 02 3f 60 	603f020b     and.lt     r1,1,r1
+  c8:	01 00 00 00 
+  cc:	0d 06 7f 60 	607f060d     and.hi     r3,3,r3
+  d0:	03 00 00 00 
+  d4:	0e 08 df 67 	67df080e     and.ls     0,4,r4
+  d8:	04 00 00 00 
+  dc:	0f fc c2 67 	67c2fc0f     and.pnz    0,r5,5
+  e0:	05 00 00 00 
+  e4:	00 85 00 60 	60008500     and.f      r0,r1,r2
+  e8:	01 fa 00 60 	6000fa01     and.f      r0,r1,1
+  ec:	01 84 1e 60 	601e8401     and.f      r0,1,r2
+  f0:	00 85 e0 67 	67e08500     and.f      0,r1,r2
+  f4:	00 fd 00 60 	6000fd00     and.f      r0,r1,0x200
+  f8:	00 02 00 00 
+  fc:	00 05 1f 60 	601f0500     and.f      r0,0x200,r2
+ 100:	00 02 00 00 
+ 104:	01 85 00 60 	60008501     and.z.f    r0,r1,r2
+ 108:	02 fd 00 60 	6000fd02     and.nz.f   r0,r1,0
+ 10c:	00 00 00 00 
+ 110:	0b 05 1f 60 	601f050b     and.lt.f   r0,0,r2
+ 114:	00 00 00 00 
+ 118:	09 85 c0 67 	67c08509     and.gt.f   0,r1,r2
+ 11c:	00 00 00 00 	00000000                
+ 120:	0c fd 00 60 	6000fd0c     and.le.f   r0,r1,0x200
+ 124:	00 02 00 00 
+ 128:	0a 05 1f 60 	601f050a     and.ge.f   r0,0x200,r2
+ 12c:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/and.s b/gas/testsuite/gas/arc/and.s
new file mode 100644
index 0000000..ddd7865
--- /dev/null
+++ b/gas/testsuite/gas/arc/and.s
@@ -0,0 +1,68 @@
+# and test
+
+	and r0,r1,r2
+	and r26,fp,sp
+	and ilink1,ilink2,blink
+	and r56,r59,lp_count
+
+	and r0,r1,0
+	and r0,0,r2
+	and 0,r1,r2
+	and r0,r1,-1
+	and r0,-1,r2
+	and -1,r1,r2
+	and r0,r1,255
+	and r0,255,r2
+	and 255,r1,r2
+	and r0,r1,-256
+	and r0,-256,r2
+	and -256,r1,r2
+
+	and r0,r1,256
+	and r0,-257,r2
+
+	and r0,255,256
+	and r0,256,255
+
+	and r0,r1,foo
+
+	and.al r0,r1,r2
+	and.ra r3,r4,r5
+	and.eq r6,r7,r8
+	and.z r9,r10,r11
+	and.ne r12,r13,r14
+	and.nz r15,r16,r17
+	and.pl r18,r19,r20
+	and.p r21,r22,r23
+	and.mi r24,r25,r26
+	and.n r27,r28,r29
+	and.cs r30,r31,r32
+	and.c r33,r34,r35
+	and.lo r36,r37,r38
+	and.cc r39,r40,r41
+	and.nc r42,r43,r44
+	and.hs r45,r46,r47
+	and.vs r48,r49,r50
+	and.v r56,r52,r53
+	and.vc r56,r55,r56
+	and.nv r56,r58,r59
+	and.gt r60,r60,r0
+	and.ge r0,r0,0
+	and.lt r1,1,r1
+	and.hi r3,3,r3
+	and.ls 4,4,r4
+	and.pnz 5,r5,5
+
+	and.f r0,r1,r2
+	and.f r0,r1,1
+	and.f r0,1,r2
+	and.f 0,r1,r2
+	and.f r0,r1,512
+	and.f r0,512,r2
+
+	and.eq.f r0,r1,r2
+	and.ne.f r0,r1,0
+	and.lt.f r0,0,r2
+	and.gt.f 0,r1,r2
+	and.le.f r0,r1,512
+	and.ge.f r0,512,r2
diff --git a/gas/testsuite/gas/arc/arc.exp b/gas/testsuite/gas/arc/arc.exp
index b098453..2e115f9 100644
--- a/gas/testsuite/gas/arc/arc.exp
+++ b/gas/testsuite/gas/arc/arc.exp
@@ -1,114 +1,45 @@
-# ARC gas testsuite
-
-# Test an insn from a template .s/.d.
-# The best way to create the .d file is to run the tests without it, let
-# dejagnu crash, run as.new on the just built .s file, run objdump -dr on
-# the result of that, copy the result into the .d file, and edit in the
-# necessary patterns (@OC@, etc.).  Sounds complicated but it's easy.  The
-# catch is that we assume a working assembler is used to build it.  That's
-# obviously not entirely kosher, but once the .d file is created one can
-# verify it's contents over time.
-#
-# Template patterns:
-# @OC@ - placeholder for the opcode
-# @IC+?@ - place holder for the insn code
-# @I3+??@ - place holder for the operation code of code 3 insns.
-
-proc test_template_insn { cpu tmpl opcode icode } {
-    global srcdir subdir objdir
-
-    # Change @OC@ in the template file to $opcode
-
-    set in_fd [open $srcdir/$subdir/$tmpl.s r]
-    set out_fd [open $objdir/$opcode.s w]
-    # FIXME: check return codes
-
-    puts $out_fd "\t.cpu $cpu\n"
-    while { [gets $in_fd line] >= 0 } {
-	regsub "@OC@" $line $opcode line
-	puts $out_fd $line
-    }
-
-    close $in_fd
-    close $out_fd
-
-    # Create output template.
-
-    set in_fd [open $srcdir/$subdir/$tmpl.d r]
-    set out_fd [open $objdir/$opcode.d w]
-    # FIXME: check return codes
-
-    while { [gets $in_fd line] >= 0 } {
-	regsub "@OC@" $line $opcode line
-	#send_user "$line\n"
-	if [string match "*@IC+?@*" $line] {
-	    # Insert the opcode.  It occupies the top 5 bits.
-	    regexp "^(.*)@IC\\+(.)@(.*)$" $line junk leftpart n rightpart
-	    set n [expr ($icode << 3) + $n]
-	    set n [format "%02x" $n]
-	    puts $out_fd "$leftpart$n$rightpart"
-	} elseif [string match "*@I3+??@*" $line] {
-	    # Insert insn 3 code (register C field)
-	    # b15=8/0, b8=1/0 (their respective hex values in the objdump)
-	    regexp "^(.*)@I3\\+(.)(.)@(.*)$" $line junk leftpart b15 b8 rightpart
-	    set n [expr ($icode << 1) + ($b15 << 4) + ($b8 << 0)]
-	    set n [format "%02x" $n]
-	    puts $out_fd "$leftpart$n$rightpart"
-	} else {
-	    puts $out_fd $line
-	}
-    }
-
-    close $in_fd
-    close $out_fd
-
-    # Finally, run the test.
-
-    run_dump_test $objdir/$opcode
-
-    # "make clean" won't delete these, so for now we must.
-    catch "exec rm -f $objdir/$opcode.s $objdir/$opcode.d"
+# ARC base instruction set (to arc8)
+if [istarget arc*-*-*] then {
+    run_dump_test ld
+    run_dump_test ld2
+    run_dump_test st
+
+    # Specially encoded/single operand instructions
+    run_dump_test flag
+    run_dump_test brk
+    run_dump_test sleep
+    run_dump_test swi
+    run_dump_test asr
+    run_dump_test lsr
+    run_dump_test ror
+    run_dump_test rrc
+    run_dump_test sexb
+    run_dump_test sexw
+    run_dump_test extb
+    run_dump_test extw
+
+    run_dump_test b
+    run_dump_test bl
+    run_dump_test lp
+    run_dump_test j
+    run_dump_test jl
+    run_dump_test add
+    run_dump_test asl
+    # FIXME: ??? `lsl' gets dumped as `asl'
+    # run_dump_test lsl
+    run_dump_test adc
+    run_dump_test rlc
+    run_dump_test sub
+    run_dump_test sbc
+    run_dump_test and
+    run_dump_test mov
+    run_dump_test or
+    run_dump_test bic
+    run_dump_test xor
+    run_dump_test nop
 }
 
-# Run the tests.
-
+# ARC library extensions
 if [istarget arc*-*-*] then {
-
-    test_template_insn base math adc 9
-    test_template_insn base math add 8
-    test_template_insn base math and 12
-    test_template_insn base math bic 14
-    test_template_insn base math or 13
-    test_template_insn base math sbc 11
-    test_template_insn base math sub 10
-    test_template_insn base math xor 15
-
-    test_template_insn base alias mov 12
-    test_template_insn base alias rlc 9
-    test_template_insn base alias asl 8
-# `lsl' gets dumped as `asl' so this must be tested elsewhere.
-#   test_template_insn base alias lsl 8
-
-    test_template_insn base sshift asr 1
-    test_template_insn base sshift lsr 2
-    test_template_insn base sshift ror 3
-    test_template_insn base sshift rrc 4
-
-    test_template_insn base branch b 4
-    test_template_insn base branch bl 5
-    test_template_insn base branch lp 6
-
-    run_dump_test "j"
-
-    test_template_insn base insn3 sexb 5
-    test_template_insn base insn3 sexw 6
-    test_template_insn base insn3 extb 7
-    test_template_insn base insn3 extw 8
-
-    run_dump_test "flag"
-#    run_dump_test "nop"
-
-    run_dump_test "ld"
-    run_dump_test "st"
-
+    # *TODO*
 }
diff --git a/gas/testsuite/gas/arc/asl.d b/gas/testsuite/gas/arc/asl.d
new file mode 100644
index 0000000..89aea0e
--- /dev/null
+++ b/gas/testsuite/gas/arc/asl.d
@@ -0,0 +1,68 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 82 00 40 	40008200     asl        r0,r1
+   4:	00 38 6e 43 	436e3800     asl        fp,sp
+   8:	00 fe 1f 40 	401ffe00     asl        r0,0
+   c:	ff ff 3f 40 	403fffff     asl        r1,-1
+  10:	00 04 e1 47 	47e10400     asl        0,r2
+  14:	00 86 e1 47 	47e18600     asl        0,r3
+  18:	ff fe 9f 40 	409ffeff     asl        r4,255
+  1c:	00 8a e2 47 	47e28a00     asl        0,r5
+  20:	00 ff df 40 	40dfff00     asl        r6,-256
+  24:	00 8e e3 47 	47e38e00     asl        0,r7
+  28:	00 7c 1f 41 	411f7c00     asl        r8,0x100
+  2c:	00 01 00 00 
+  30:	00 7c 3f 41 	413f7c00     asl        r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 7c 7f 41 	417f7c00     asl        r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 7c ff 47 	47ff7c00     asl        0,0x100
+  44:	00 01 00 00 
+  48:	00 7c 1f 40 	401f7c00     asl        r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	00 82 00 40 	40008200     asl        r0,r1
+  54:	00 08 62 40 	40620800     asl        r3,r4
+  58:	01 8e c3 40 	40c38e01     asl.z      r6,r7
+  5c:	01 14 25 41 	41251401     asl.z      r9,r10
+  60:	02 9a 86 41 	41869a02     asl.nz     r12,r13
+  64:	02 20 e8 41 	41e82002     asl.nz     r15,r16
+  68:	03 a6 49 42 	4249a603     asl.p      r18,r19
+  6c:	03 2c ab 42 	42ab2c03     asl.p      r21,r22
+  70:	04 b2 0c 43 	430cb204     asl.n      r24,r25
+  74:	04 38 6e 43 	436e3804     asl.n      fp,sp
+  78:	05 be cf 43 	43cfbe05     asl.c      ilink2,blink
+  7c:	05 44 31 44 	44314405     asl.c      r33,r34
+  80:	05 ca 92 44 	4492ca05     asl.c      r36,r37
+  84:	06 50 f4 44 	44f45006     asl.nc     r39,r40
+  88:	06 d6 55 45 	4555d606     asl.nc     r42,r43
+  8c:	06 5c b7 45 	45b75c06     asl.nc     r45,r46
+  90:	07 e2 18 46 	4618e207     asl.v      r48,r49
+  94:	07 64 39 46 	46396407     asl.v      r49,r50
+  98:	08 ee 3b 46 	463bee08     asl.nv     r49,r55
+  9c:	08 74 3d 46 	463d7408     asl.nv     r49,r58
+  a0:	09 78 9e 47 	479e7809     asl.gt     lp_count,lp_count
+  a4:	0a 7c 1f 40 	401f7c0a     asl.ge     r0,0
+  a8:	00 00 00 00 
+  ac:	0c 7c df 47 	47df7c0c     asl.le     0,2
+  b0:	02 00 00 00 
+  b4:	0d 86 61 40 	4061860d     asl.hi     r3,r3
+  b8:	0e 08 82 40 	4082080e     asl.ls     r4,r4
+  bc:	0f 8a a2 40 	40a28a0f     asl.pnz    r5,r5
+  c0:	00 83 00 40 	40008300     asl.f      r0,r1
+  c4:	01 fa 5e 40 	405efa01     asl.f      r2,1
+  c8:	00 87 e1 47 	47e18700     asl.f      0,r3
+  cc:	00 09 e2 47 	47e20900     asl.f      0,r4
+  d0:	00 7d bf 40 	40bf7d00     asl.f      r5,0x200
+  d4:	00 02 00 00 
+  d8:	00 7d df 47 	47df7d00     asl.f      0,0x200
+  dc:	00 02 00 00 
+  e0:	01 83 00 40 	40008301     asl.z.f    r0,r1
+  e4:	02 7d 3f 40 	403f7d02     asl.nz.f   r1,0
+  e8:	00 00 00 00 
diff --git a/gas/testsuite/gas/arc/asl.s b/gas/testsuite/gas/arc/asl.s
new file mode 100644
index 0000000..f931458
--- /dev/null
+++ b/gas/testsuite/gas/arc/asl.s
@@ -0,0 +1,58 @@
+# asl test
+
+	asl r0,r1
+	asl fp,sp
+
+	asl r0,0
+	asl r1,-1
+	asl 0,r2
+	asl -1,r3
+	asl r4,255
+	asl 255,r5
+	asl r6,-256
+	asl -256,r7
+
+	asl r8,256
+	asl r9,-257
+	asl r11,0x42424242
+
+	asl 255,256
+
+	asl r0,foo
+
+	asl.al r0,r1
+	asl.ra r3,r4
+	asl.eq r6,r7
+	asl.z r9,r10
+	asl.ne r12,r13
+	asl.nz r15,r16
+	asl.pl r18,r19
+	asl.p r21,r22
+	asl.mi r24,r25
+	asl.n r27,r28
+	asl.cs r30,r31
+	asl.c r33,r34
+	asl.lo r36,r37
+	asl.cc r39,r40
+	asl.nc r42,r43
+	asl.hs r45,r46
+	asl.vs r48,r49
+	asl.v r49,r50
+	asl.vc r49,r55
+	asl.nv r49,r58
+	asl.gt r60,r60
+	asl.ge r0,0
+	asl.le 2,2
+	asl.hi r3,r3
+	asl.ls r4,r4
+	asl.pnz r5,r5
+
+	asl.f r0,r1
+	asl.f r2,1
+	asl.f 1,r3
+	asl.f 0,r4
+	asl.f r5,512
+	asl.f 512,512
+
+	asl.eq.f r0,r1
+	asl.ne.f r1,0
diff --git a/gas/testsuite/gas/arc/asr.d b/gas/testsuite/gas/arc/asr.d
new file mode 100644
index 0000000..bb4c96e
--- /dev/null
+++ b/gas/testsuite/gas/arc/asr.d
@@ -0,0 +1,51 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 82 00 18 	18008200     asr        r0,r1
+   4:	00 02 6e 1b 	1b6e0200     asr        fp,sp
+   8:	00 82 1f 18 	181f8200     asr        r0,0
+   c:	ff 83 3f 18 	183f83ff     asr        r1,-1
+  10:	00 02 e1 1f 	1fe10200     asr        0,r2
+  14:	00 82 e1 1f 	1fe18200     asr        0,r3
+  18:	ff 82 9f 18 	189f82ff     asr        r4,255
+  1c:	00 82 e2 1f 	1fe28200     asr        0,r5
+  20:	00 83 df 18 	18df8300     asr        r6,-256
+  24:	00 82 e3 1f 	1fe38200     asr        0,r7
+  28:	00 02 1f 19 	191f0200     asr        r8,0x100
+  2c:	00 01 00 00 
+  30:	00 02 3f 19 	193f0200     asr        r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 02 7f 19 	197f0200     asr        r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 02 ff 1f 	1fff0200     asr        0,0x100
+  44:	00 01 00 00 
+  48:	00 02 1f 18 	181f0200     asr        r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	01 82 45 19 	19458201     asr.z      r10,r11
+  54:	02 82 86 19 	19868202     asr.nz     r12,r13
+  58:	0b 02 df 19 	19df020b     asr.lt     r14,0
+  5c:	00 00 00 00 
+  60:	09 02 ff 19 	19ff0209     asr.gt     r15,0x200
+  64:	00 02 00 00 
+  68:	00 83 00 18 	18008300     asr.f      r0,r1
+  6c:	01 82 5e 18 	185e8201     asr.f      r2,1
+  70:	00 03 e2 1f 	1fe20300     asr.f      0,r4
+  74:	00 03 bf 18 	18bf0300     asr.f      r5,0x200
+  78:	00 02 00 00 
+  7c:	00 03 df 1f 	1fdf0300     asr.f      0,0x200
+  80:	00 02 00 00 
+  84:	01 83 00 18 	18008301     asr.z.f    r0,r1
+  88:	02 03 3f 18 	183f0302     asr.nz.f   r1,0
+  8c:	00 00 00 00 
+  90:	0b 03 c1 1f 	1fc1030b     asr.lt.f   0,r2
+  94:	00 00 00 00 	00000000                
+  98:	0c 03 1f 18 	181f030c     asr.le.f   r0,0x200
+  9c:	00 02 00 00 
+  a0:	04 03 df 1f 	1fdf0304     asr.n.f    0,0x200
+  a4:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/asr.s b/gas/testsuite/gas/arc/asr.s
new file mode 100644
index 0000000..9998b34
--- /dev/null
+++ b/gas/testsuite/gas/arc/asr.s
@@ -0,0 +1,38 @@
+# asr test
+
+	asr r0,r1
+	asr fp,sp
+
+	asr r0,0
+	asr r1,-1
+	asr 0,r2
+	asr -1,r3
+	asr r4,255
+	asr 255,r5
+	asr r6,-256
+	asr -256,r7
+
+	asr r8,256
+	asr r9,-257
+	asr r11,0x42424242
+
+	asr 255,256
+
+	asr r0,foo
+
+	asr.eq r10,r11
+	asr.ne r12,r13
+	asr.lt r14,0
+	asr.gt r15,512
+
+	asr.f r0,r1
+	asr.f r2,1
+	asr.f 0,r4
+	asr.f r5,512
+	asr.f 512,512
+
+	asr.eq.f r0,r1
+	asr.ne.f r1,0
+	asr.lt.f 0,r2
+	asr.le.f r0,512
+	asr.n.f 512,512
diff --git a/gas/testsuite/gas/arc/b.d b/gas/testsuite/gas/arc/b.d
new file mode 100644
index 0000000..8c2eb01
--- /dev/null
+++ b/gas/testsuite/gas/arc/b.d
@@ -0,0 +1,76 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <text_label>:
+   0:	80 ff ff 27 	27ffff80     b          0 <text_label>
+
+   4:	00 ff ff 27 	27ffff00     b          0 <text_label>
+
+   8:	80 fe ff 27 	27fffe80     b          0 <text_label>
+
+   c:	01 fe ff 27 	27fffe01     bz         0 <text_label>
+
+  10:	81 fd ff 27 	27fffd81     bz         0 <text_label>
+
+  14:	02 fd ff 27 	27fffd02     bnz        0 <text_label>
+
+  18:	82 fc ff 27 	27fffc82     bnz        0 <text_label>
+
+  1c:	03 fc ff 27 	27fffc03     bp         0 <text_label>
+
+  20:	83 fb ff 27 	27fffb83     bp         0 <text_label>
+
+  24:	04 fb ff 27 	27fffb04     bn         0 <text_label>
+
+  28:	84 fa ff 27 	27fffa84     bn         0 <text_label>
+
+  2c:	05 fa ff 27 	27fffa05     bc         0 <text_label>
+
+  30:	85 f9 ff 27 	27fff985     bc         0 <text_label>
+
+  34:	05 f9 ff 27 	27fff905     bc         0 <text_label>
+
+  38:	86 f8 ff 27 	27fff886     bnc        0 <text_label>
+
+  3c:	06 f8 ff 27 	27fff806     bnc        0 <text_label>
+
+  40:	86 f7 ff 27 	27fff786     bnc        0 <text_label>
+
+  44:	07 f7 ff 27 	27fff707     bv         0 <text_label>
+
+  48:	87 f6 ff 27 	27fff687     bv         0 <text_label>
+
+  4c:	08 f6 ff 27 	27fff608     bnv        0 <text_label>
+
+  50:	88 f5 ff 27 	27fff588     bnv        0 <text_label>
+
+  54:	09 f5 ff 27 	27fff509     bgt        0 <text_label>
+
+  58:	8a f4 ff 27 	27fff48a     bge        0 <text_label>
+
+  5c:	0b f4 ff 27 	27fff40b     blt        0 <text_label>
+
+  60:	8c f3 ff 27 	27fff38c     ble        0 <text_label>
+
+  64:	0d f3 ff 27 	27fff30d     bhi        0 <text_label>
+
+  68:	8e f2 ff 27 	27fff28e     bls        0 <text_label>
+
+  6c:	0f f2 ff 27 	27fff20f     bpnz       0 <text_label>
+
+  70:	a0 f1 ff 27 	27fff1a0     b.d        0 <text_label>
+
+  74:	00 f1 ff 27 	27fff100     b          0 <text_label>
+
+  78:	c0 f0 ff 27 	27fff0c0     b.jd       0 <text_label>
+
+  7c:	21 f0 ff 27 	27fff021     bz.d       0 <text_label>
+
+  80:	82 ef ff 27 	27ffef82     bnz        0 <text_label>
+
+  84:	46 ef ff 27 	27ffef46     bnc.jd     0 <text_label>
+
diff --git a/gas/testsuite/gas/arc/b.s b/gas/testsuite/gas/arc/b.s
new file mode 100644
index 0000000..a215fe4
--- /dev/null
+++ b/gas/testsuite/gas/arc/b.s
@@ -0,0 +1,40 @@
+# b test
+	
+text_label:
+
+	b	text_label
+	bal	text_label
+	bra	text_label
+	beq	text_label
+	bz	text_label
+	bne	text_label
+	bnz	text_label
+	bpl	text_label
+	bp	text_label
+	bmi	text_label
+	bn	text_label
+	bcs	text_label
+	bc	text_label
+	blo	text_label
+	bcc	text_label
+	bnc	text_label
+	bhs	text_label
+	bvs	text_label
+	bv	text_label
+	bvc	text_label
+	bnv	text_label
+	bgt	text_label
+	bge	text_label
+	blt	text_label
+	ble	text_label
+	bhi	text_label
+	bls	text_label
+	bpnz	text_label
+
+	b.d	text_label
+	b.nd	text_label
+	b.jd	text_label
+
+	beq.d	text_label
+	bne.nd	text_label
+	bcc.jd	text_label
diff --git a/gas/testsuite/gas/arc/bic.d b/gas/testsuite/gas/arc/bic.d
new file mode 100644
index 0000000..5b2a233
--- /dev/null
+++ b/gas/testsuite/gas/arc/bic.d
@@ -0,0 +1,85 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 84 00 70 	70008400     bic        r0,r1,r2
+   4:	00 b8 4d 73 	734db800     bic        gp,fp,sp
+   8:	00 3e af 73 	73af3e00     bic        ilink1,ilink2,blink
+   c:	00 f8 1d 77 	771df800     bic        r56,r59,lp_count
+  10:	00 fe 00 70 	7000fe00     bic        r0,r1,0
+  14:	00 84 1f 70 	701f8400     bic        r0,0,r2
+  18:	00 84 e0 77 	77e08400     bic        0,r1,r2
+  1c:	ff ff 00 70 	7000ffff     bic        r0,r1,-1
+  20:	ff 85 1f 70 	701f85ff     bic        r0,-1,r2
+  24:	00 84 e0 77 	77e08400     bic        0,r1,r2
+  28:	ff fe 00 70 	7000feff     bic        r0,r1,255
+  2c:	ff 84 1f 70 	701f84ff     bic        r0,255,r2
+  30:	00 84 e0 77 	77e08400     bic        0,r1,r2
+  34:	00 ff 00 70 	7000ff00     bic        r0,r1,-256
+  38:	00 85 1f 70 	701f8500     bic        r0,-256,r2
+  3c:	00 84 e0 77 	77e08400     bic        0,r1,r2
+  40:	00 fc 00 70 	7000fc00     bic        r0,r1,0x100
+  44:	00 01 00 00 
+  48:	00 04 1f 70 	701f0400     bic        r0,0xffff_feff,r2
+  4c:	ff fe ff ff 
+  50:	ff fc 1f 70 	701ffcff     bic        r0,255,0x100
+  54:	00 01 00 00 
+  58:	ff 7e 1f 70 	701f7eff     bic        r0,0x100,255
+  5c:	00 01 00 00 
+  60:	00 fc 00 70 	7000fc00     bic        r0,r1,0
+  64:	00 00 00 00 
+			64: R_ARC_32	foo
+  68:	00 84 00 70 	70008400     bic        r0,r1,r2
+  6c:	00 0a 62 70 	70620a00     bic        r3,r4,r5
+  70:	01 90 c3 70 	70c39001     bic.z      r6,r7,r8
+  74:	01 16 25 71 	71251601     bic.z      r9,r10,r11
+  78:	02 9c 86 71 	71869c02     bic.nz     r12,r13,r14
+  7c:	02 22 e8 71 	71e82202     bic.nz     r15,r16,r17
+  80:	03 a8 49 72 	7249a803     bic.p      r18,r19,r20
+  84:	03 2e ab 72 	72ab2e03     bic.p      r21,r22,r23
+  88:	04 b4 0c 73 	730cb404     bic.n      r24,r25,gp
+  8c:	04 3a 6e 73 	736e3a04     bic.n      fp,sp,ilink1
+  90:	05 c0 cf 73 	73cfc005     bic.c      ilink2,blink,r32
+  94:	05 46 31 74 	74314605     bic.c      r33,r34,r35
+  98:	05 cc 92 74 	7492cc05     bic.c      r36,r37,r38
+  9c:	06 52 f4 74 	74f45206     bic.nc     r39,r40,r41
+  a0:	06 d8 55 75 	7555d806     bic.nc     r42,r43,r44
+  a4:	06 5e b7 75 	75b75e06     bic.nc     r45,r46,r47
+  a8:	07 e4 18 76 	7618e407     bic.v      r48,r49,r50
+  ac:	07 6a 1a 77 	771a6a07     bic.v      r56,r52,r53
+  b0:	08 f0 1b 77 	771bf008     bic.nv     r56,r55,r56
+  b4:	08 76 1d 77 	771d7608     bic.nv     r56,r58,r59
+  b8:	09 00 9e 77 	779e0009     bic.gt     lp_count,lp_count,r0
+  bc:	0a 7c 00 70 	70007c0a     bic.ge     r0,r0,0
+  c0:	00 00 00 00 
+  c4:	0b 02 3f 70 	703f020b     bic.lt     r1,1,r1
+  c8:	01 00 00 00 
+  cc:	0d 06 7f 70 	707f060d     bic.hi     r3,3,r3
+  d0:	03 00 00 00 
+  d4:	0e 08 df 77 	77df080e     bic.ls     0,4,r4
+  d8:	04 00 00 00 
+  dc:	0f fc c2 77 	77c2fc0f     bic.pnz    0,r5,5
+  e0:	05 00 00 00 
+  e4:	00 85 00 70 	70008500     bic.f      r0,r1,r2
+  e8:	01 fa 00 70 	7000fa01     bic.f      r0,r1,1
+  ec:	01 84 1e 70 	701e8401     bic.f      r0,1,r2
+  f0:	00 85 e0 77 	77e08500     bic.f      0,r1,r2
+  f4:	00 fd 00 70 	7000fd00     bic.f      r0,r1,0x200
+  f8:	00 02 00 00 
+  fc:	00 05 1f 70 	701f0500     bic.f      r0,0x200,r2
+ 100:	00 02 00 00 
+ 104:	01 85 00 70 	70008501     bic.z.f    r0,r1,r2
+ 108:	02 fd 00 70 	7000fd02     bic.nz.f   r0,r1,0
+ 10c:	00 00 00 00 
+ 110:	0b 05 1f 70 	701f050b     bic.lt.f   r0,0,r2
+ 114:	00 00 00 00 
+ 118:	09 85 c0 77 	77c08509     bic.gt.f   0,r1,r2
+ 11c:	00 00 00 00 	00000000                
+ 120:	0c fd 00 70 	7000fd0c     bic.le.f   r0,r1,0x200
+ 124:	00 02 00 00 
+ 128:	0a 05 1f 70 	701f050a     bic.ge.f   r0,0x200,r2
+ 12c:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/bic.s b/gas/testsuite/gas/arc/bic.s
new file mode 100644
index 0000000..fc5eb19
--- /dev/null
+++ b/gas/testsuite/gas/arc/bic.s
@@ -0,0 +1,68 @@
+# bic test
+
+	bic r0,r1,r2
+	bic r26,fp,sp
+	bic ilink1,ilink2,blink
+	bic r56,r59,lp_count
+
+	bic r0,r1,0
+	bic r0,0,r2
+	bic 0,r1,r2
+	bic r0,r1,-1
+	bic r0,-1,r2
+	bic -1,r1,r2
+	bic r0,r1,255
+	bic r0,255,r2
+	bic 255,r1,r2
+	bic r0,r1,-256
+	bic r0,-256,r2
+	bic -256,r1,r2
+
+	bic r0,r1,256
+	bic r0,-257,r2
+
+	bic r0,255,256
+	bic r0,256,255
+
+	bic r0,r1,foo
+
+	bic.al r0,r1,r2
+	bic.ra r3,r4,r5
+	bic.eq r6,r7,r8
+	bic.z r9,r10,r11
+	bic.ne r12,r13,r14
+	bic.nz r15,r16,r17
+	bic.pl r18,r19,r20
+	bic.p r21,r22,r23
+	bic.mi r24,r25,r26
+	bic.n r27,r28,r29
+	bic.cs r30,r31,r32
+	bic.c r33,r34,r35
+	bic.lo r36,r37,r38
+	bic.cc r39,r40,r41
+	bic.nc r42,r43,r44
+	bic.hs r45,r46,r47
+	bic.vs r48,r49,r50
+	bic.v r56,r52,r53
+	bic.vc r56,r55,r56
+	bic.nv r56,r58,r59
+	bic.gt r60,r60,r0
+	bic.ge r0,r0,0
+	bic.lt r1,1,r1
+	bic.hi r3,3,r3
+	bic.ls 4,4,r4
+	bic.pnz 5,r5,5
+
+	bic.f r0,r1,r2
+	bic.f r0,r1,1
+	bic.f r0,1,r2
+	bic.f 0,r1,r2
+	bic.f r0,r1,512
+	bic.f r0,512,r2
+
+	bic.eq.f r0,r1,r2
+	bic.ne.f r0,r1,0
+	bic.lt.f r0,0,r2
+	bic.gt.f 0,r1,r2
+	bic.le.f r0,r1,512
+	bic.ge.f r0,512,r2
diff --git a/gas/testsuite/gas/arc/bl.d b/gas/testsuite/gas/arc/bl.d
new file mode 100644
index 0000000..0cc19db
--- /dev/null
+++ b/gas/testsuite/gas/arc/bl.d
@@ -0,0 +1,76 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <text_label>:
+   0:	80 ff ff 2f 	2fffff80     bl         0 <text_label>
+
+   4:	00 ff ff 2f 	2fffff00     bl         0 <text_label>
+
+   8:	80 fe ff 2f 	2ffffe80     bl         0 <text_label>
+
+   c:	01 fe ff 2f 	2ffffe01     blz        0 <text_label>
+
+  10:	81 fd ff 2f 	2ffffd81     blz        0 <text_label>
+
+  14:	02 fd ff 2f 	2ffffd02     blnz       0 <text_label>
+
+  18:	82 fc ff 2f 	2ffffc82     blnz       0 <text_label>
+
+  1c:	03 fc ff 2f 	2ffffc03     blp        0 <text_label>
+
+  20:	83 fb ff 2f 	2ffffb83     blp        0 <text_label>
+
+  24:	04 fb ff 2f 	2ffffb04     bln        0 <text_label>
+
+  28:	84 fa ff 2f 	2ffffa84     bln        0 <text_label>
+
+  2c:	05 fa ff 2f 	2ffffa05     blc        0 <text_label>
+
+  30:	85 f9 ff 2f 	2ffff985     blc        0 <text_label>
+
+  34:	05 f9 ff 2f 	2ffff905     blc        0 <text_label>
+
+  38:	86 f8 ff 2f 	2ffff886     blnc       0 <text_label>
+
+  3c:	06 f8 ff 2f 	2ffff806     blnc       0 <text_label>
+
+  40:	86 f7 ff 2f 	2ffff786     blnc       0 <text_label>
+
+  44:	07 f7 ff 2f 	2ffff707     blv        0 <text_label>
+
+  48:	87 f6 ff 2f 	2ffff687     blv        0 <text_label>
+
+  4c:	08 f6 ff 2f 	2ffff608     blnv       0 <text_label>
+
+  50:	88 f5 ff 2f 	2ffff588     blnv       0 <text_label>
+
+  54:	09 f5 ff 2f 	2ffff509     blgt       0 <text_label>
+
+  58:	8a f4 ff 2f 	2ffff48a     blge       0 <text_label>
+
+  5c:	0b f4 ff 2f 	2ffff40b     bllt       0 <text_label>
+
+  60:	8c f3 ff 2f 	2ffff38c     blle       0 <text_label>
+
+  64:	0d f3 ff 2f 	2ffff30d     blhi       0 <text_label>
+
+  68:	8e f2 ff 2f 	2ffff28e     blls       0 <text_label>
+
+  6c:	0f f2 ff 2f 	2ffff20f     blpnz      0 <text_label>
+
+  70:	a0 f1 ff 2f 	2ffff1a0     bl.d       0 <text_label>
+
+  74:	00 f1 ff 2f 	2ffff100     bl         0 <text_label>
+
+  78:	c0 f0 ff 2f 	2ffff0c0     bl.jd      0 <text_label>
+
+  7c:	21 f0 ff 2f 	2ffff021     blz.d      0 <text_label>
+
+  80:	82 ef ff 2f 	2fffef82     blnz       0 <text_label>
+
+  84:	46 ef ff 2f 	2fffef46     blnc.jd    0 <text_label>
+
diff --git a/gas/testsuite/gas/arc/bl.s b/gas/testsuite/gas/arc/bl.s
new file mode 100644
index 0000000..8181f39
--- /dev/null
+++ b/gas/testsuite/gas/arc/bl.s
@@ -0,0 +1,40 @@
+# bl test
+	
+text_label:
+
+	bl	text_label
+	blal	text_label
+	blra	text_label
+	bleq	text_label
+	blz	text_label
+	blne	text_label
+	blnz	text_label
+	blpl	text_label
+	blp	text_label
+	blmi	text_label
+	bln	text_label
+	blcs	text_label
+	blc	text_label
+	bllo	text_label
+	blcc	text_label
+	blnc	text_label
+	blhs	text_label
+	blvs	text_label
+	blv	text_label
+	blvc	text_label
+	blnv	text_label
+	blgt	text_label
+	blge	text_label
+	bllt	text_label
+	blle	text_label
+	blhi	text_label
+	blls	text_label
+	blpnz	text_label
+
+	bl.d	text_label
+	bl.nd	text_label
+	bl.jd	text_label
+
+	bleq.d	text_label
+	blne.nd	text_label
+	blcc.jd	text_label
diff --git a/gas/testsuite/gas/arc/brk.d b/gas/testsuite/gas/arc/brk.d
new file mode 100644
index 0000000..70f9e4f
--- /dev/null
+++ b/gas/testsuite/gas/arc/brk.d
@@ -0,0 +1,11 @@
+#as: -EL -marc7
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 84 00 40 	40008400     add        r0,r1,r2
+   4:	00 fe ff 1f 	1ffffe00     brk        
+   8:	00 0a 62 50 	50620a00     sub        r3,r4,r5
diff --git a/gas/testsuite/gas/arc/brk.s b/gas/testsuite/gas/arc/brk.s
new file mode 100644
index 0000000..00b0761
--- /dev/null
+++ b/gas/testsuite/gas/arc/brk.s
@@ -0,0 +1,7 @@
+# brk test
+
+main:
+
+	add	r0,r1,r2	
+	brk
+	sub	r3,r4,r5
diff --git a/gas/testsuite/gas/arc/extb.d b/gas/testsuite/gas/arc/extb.d
new file mode 100644
index 0000000..1ceca8a
--- /dev/null
+++ b/gas/testsuite/gas/arc/extb.d
@@ -0,0 +1,51 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 8e 00 18 	18008e00     extb       r0,r1
+   4:	00 0e 6e 1b 	1b6e0e00     extb       fp,sp
+   8:	00 8e 1f 18 	181f8e00     extb       r0,0
+   c:	ff 8f 3f 18 	183f8fff     extb       r1,-1
+  10:	00 0e e1 1f 	1fe10e00     extb       0,r2
+  14:	00 8e e1 1f 	1fe18e00     extb       0,r3
+  18:	ff 8e 9f 18 	189f8eff     extb       r4,255
+  1c:	00 8e e2 1f 	1fe28e00     extb       0,r5
+  20:	00 8f df 18 	18df8f00     extb       r6,-256
+  24:	00 8e e3 1f 	1fe38e00     extb       0,r7
+  28:	00 0e 1f 19 	191f0e00     extb       r8,0x100
+  2c:	00 01 00 00 
+  30:	00 0e 3f 19 	193f0e00     extb       r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 0e 7f 19 	197f0e00     extb       r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 0e ff 1f 	1fff0e00     extb       0,0x100
+  44:	00 01 00 00 
+  48:	00 0e 1f 18 	181f0e00     extb       r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	01 8e 45 19 	19458e01     extb.z     r10,r11
+  54:	02 8e 86 19 	19868e02     extb.nz    r12,r13
+  58:	0b 0e df 19 	19df0e0b     extb.lt    r14,0
+  5c:	00 00 00 00 
+  60:	09 0e ff 19 	19ff0e09     extb.gt    r15,0x200
+  64:	00 02 00 00 
+  68:	00 8f 00 18 	18008f00     extb.f     r0,r1
+  6c:	01 8e 5e 18 	185e8e01     extb.f     r2,1
+  70:	00 0f e2 1f 	1fe20f00     extb.f     0,r4
+  74:	00 0f bf 18 	18bf0f00     extb.f     r5,0x200
+  78:	00 02 00 00 
+  7c:	00 0f df 1f 	1fdf0f00     extb.f     0,0x200
+  80:	00 02 00 00 
+  84:	01 8f 00 18 	18008f01     extb.z.f   r0,r1
+  88:	02 0f 3f 18 	183f0f02     extb.nz.f  r1,0
+  8c:	00 00 00 00 
+  90:	0b 0f c1 1f 	1fc10f0b     extb.lt.f  0,r2
+  94:	00 00 00 00 	00000000                
+  98:	0c 0f 1f 18 	181f0f0c     extb.le.f  r0,0x200
+  9c:	00 02 00 00 
+  a0:	04 0f df 1f 	1fdf0f04     extb.n.f   0,0x200
+  a4:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/extb.s b/gas/testsuite/gas/arc/extb.s
new file mode 100644
index 0000000..e872975
--- /dev/null
+++ b/gas/testsuite/gas/arc/extb.s
@@ -0,0 +1,38 @@
+# extb test
+
+	extb r0,r1
+	extb fp,sp
+
+	extb r0,0
+	extb r1,-1
+	extb 0,r2
+	extb -1,r3
+	extb r4,255
+	extb 255,r5
+	extb r6,-256
+	extb -256,r7
+
+	extb r8,256
+	extb r9,-257
+	extb r11,0x42424242
+
+	extb 255,256
+
+	extb r0,foo
+
+	extb.eq r10,r11
+	extb.ne r12,r13
+	extb.lt r14,0
+	extb.gt r15,512
+
+	extb.f r0,r1
+	extb.f r2,1
+	extb.f 0,r4
+	extb.f r5,512
+	extb.f 512,512
+
+	extb.eq.f r0,r1
+	extb.ne.f r1,0
+	extb.lt.f 0,r2
+	extb.le.f r0,512
+	extb.n.f 512,512
diff --git a/gas/testsuite/gas/arc/extw.d b/gas/testsuite/gas/arc/extw.d
new file mode 100644
index 0000000..500f2fa
--- /dev/null
+++ b/gas/testsuite/gas/arc/extw.d
@@ -0,0 +1,51 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 90 00 18 	18009000     extw       r0,r1
+   4:	00 10 6e 1b 	1b6e1000     extw       fp,sp
+   8:	00 90 1f 18 	181f9000     extw       r0,0
+   c:	ff 91 3f 18 	183f91ff     extw       r1,-1
+  10:	00 10 e1 1f 	1fe11000     extw       0,r2
+  14:	00 90 e1 1f 	1fe19000     extw       0,r3
+  18:	ff 90 9f 18 	189f90ff     extw       r4,255
+  1c:	00 90 e2 1f 	1fe29000     extw       0,r5
+  20:	00 91 df 18 	18df9100     extw       r6,-256
+  24:	00 90 e3 1f 	1fe39000     extw       0,r7
+  28:	00 10 1f 19 	191f1000     extw       r8,0x100
+  2c:	00 01 00 00 
+  30:	00 10 3f 19 	193f1000     extw       r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 10 7f 19 	197f1000     extw       r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 10 ff 1f 	1fff1000     extw       0,0x100
+  44:	00 01 00 00 
+  48:	00 10 1f 18 	181f1000     extw       r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	01 90 45 19 	19459001     extw.z     r10,r11
+  54:	02 90 86 19 	19869002     extw.nz    r12,r13
+  58:	0b 10 df 19 	19df100b     extw.lt    r14,0
+  5c:	00 00 00 00 
+  60:	09 10 ff 19 	19ff1009     extw.gt    r15,0x200
+  64:	00 02 00 00 
+  68:	00 91 00 18 	18009100     extw.f     r0,r1
+  6c:	01 90 5e 18 	185e9001     extw.f     r2,1
+  70:	00 11 e2 1f 	1fe21100     extw.f     0,r4
+  74:	00 11 bf 18 	18bf1100     extw.f     r5,0x200
+  78:	00 02 00 00 
+  7c:	00 11 df 1f 	1fdf1100     extw.f     0,0x200
+  80:	00 02 00 00 
+  84:	01 91 00 18 	18009101     extw.z.f   r0,r1
+  88:	02 11 3f 18 	183f1102     extw.nz.f  r1,0
+  8c:	00 00 00 00 
+  90:	0b 11 c1 1f 	1fc1110b     extw.lt.f  0,r2
+  94:	00 00 00 00 	00000000                
+  98:	0c 11 1f 18 	181f110c     extw.le.f  r0,0x200
+  9c:	00 02 00 00 
+  a0:	04 11 df 1f 	1fdf1104     extw.n.f   0,0x200
+  a4:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/extw.s b/gas/testsuite/gas/arc/extw.s
new file mode 100644
index 0000000..060a8e3
--- /dev/null
+++ b/gas/testsuite/gas/arc/extw.s
@@ -0,0 +1,38 @@
+# extw test
+
+	extw r0,r1
+	extw fp,sp
+
+	extw r0,0
+	extw r1,-1
+	extw 0,r2
+	extw -1,r3
+	extw r4,255
+	extw 255,r5
+	extw r6,-256
+	extw -256,r7
+
+	extw r8,256
+	extw r9,-257
+	extw r11,0x42424242
+
+	extw 255,256
+
+	extw r0,foo
+
+	extw.eq r10,r11
+	extw.ne r12,r13
+	extw.lt r14,0
+	extw.gt r15,512
+
+	extw.f r0,r1
+	extw.f r2,1
+	extw.f 0,r4
+	extw.f r5,512
+	extw.f 512,512
+
+	extw.eq.f r0,r1
+	extw.ne.f r1,0
+	extw.lt.f 0,r2
+	extw.le.f r0,512
+	extw.n.f 512,512
diff --git a/gas/testsuite/gas/arc/flag.d b/gas/testsuite/gas/arc/flag.d
index 68f36d3..55c59de 100644
--- a/gas/testsuite/gas/arc/flag.d
+++ b/gas/testsuite/gas/arc/flag.d
@@ -1,29 +1,38 @@
-#objdump: -dr
-#name: flag
-
-# Test the flag macro.
+#as: -EL
+#objdump: -dr -EL
 
 .*: +file format elf32-.*arc
 
-No symbols in "a.out".
 Disassembly of section .text:
-00000000 1fa00000	flag r0
-00000004 1fbf8001	flag 1
-00000008 1fbf8002	flag 2
-0000000c 1fbf8004	flag 4
-00000010 1fbf8008	flag 8
-00000014 1fbf8010	flag 16
-00000018 1fbf8020	flag 32
-0000001c 1fbf8040	flag 64
-00000020 1fbf8080	flag 128
-00000024 1fbf0000	flag -2147483647
-0000002c 1fa0000b	flag.lt r0
-00000030 1fbf0009	flag.gt 1
-00000038 1fbf0009	flag.gt 2
-00000040 1fbf0009	flag.gt 4
-00000048 1fbf0009	flag.gt 8
-00000050 1fbf0009	flag.gt 16
-00000058 1fbf0009	flag.gt 32
-00000060 1fbf0009	flag.gt 64
-00000068 1fbf0009	flag.gt 128
-00000070 1fbf000a	flag.ge -2147483647
+
+00000000 <.text>:
+   0:	00 00 a0 1f 	1fa00000     flag       r0
+   4:	01 80 bf 1f 	1fbf8001     flag       1
+   8:	02 80 bf 1f 	1fbf8002     flag       2
+   c:	04 80 bf 1f 	1fbf8004     flag       4
+  10:	08 80 bf 1f 	1fbf8008     flag       8
+  14:	10 80 bf 1f 	1fbf8010     flag       16
+  18:	20 80 bf 1f 	1fbf8020     flag       32
+  1c:	40 80 bf 1f 	1fbf8040     flag       64
+  20:	80 80 bf 1f 	1fbf8080     flag       128
+  24:	00 00 bf 1f 	1fbf0000     flag       0x8000_0001
+  28:	01 00 00 80 
+  2c:	0b 00 a0 1f 	1fa0000b     flag.lt    r0
+  30:	09 00 bf 1f 	1fbf0009     flag.gt    1
+  34:	01 00 00 00 
+  38:	09 00 bf 1f 	1fbf0009     flag.gt    2
+  3c:	02 00 00 00 
+  40:	09 00 bf 1f 	1fbf0009     flag.gt    4
+  44:	04 00 00 00 
+  48:	09 00 bf 1f 	1fbf0009     flag.gt    8
+  4c:	08 00 00 00 
+  50:	09 00 bf 1f 	1fbf0009     flag.gt    16
+  54:	10 00 00 00 
+  58:	09 00 bf 1f 	1fbf0009     flag.gt    32
+  5c:	20 00 00 00 
+  60:	09 00 bf 1f 	1fbf0009     flag.gt    64
+  64:	40 00 00 00 
+  68:	09 00 bf 1f 	1fbf0009     flag.gt    128
+  6c:	80 00 00 00 
+  70:	0a 00 bf 1f 	1fbf000a     flag.ge    0x8000_0001
+  74:	01 00 00 80 
diff --git a/gas/testsuite/gas/arc/j.d b/gas/testsuite/gas/arc/j.d
index af103f0..87e8004 100644
--- a/gas/testsuite/gas/arc/j.d
+++ b/gas/testsuite/gas/arc/j.d
@@ -1,75 +1,127 @@
-#objdump: -dr
-#name: j
-
-# Test the j insn.
+#as: -EL
+#objdump: -dr -EL
 
 .*: +file format elf32-.*arc
 
 Disassembly of section .text:
-00000000 <text_label> 38000000	j r0
-00000004 <text_label\+4> 38000020	j.d r0
-00000008 <text_label\+8> 38000040	j.jd r0
-0000000c <text_label\+c> 38000000	j r0
-00000010 <text_label\+10> 38008000	j r1
-00000014 <text_label\+14> 38008020	j.d r1
-00000018 <text_label\+18> 38008040	j.jd r1
-0000001c <text_label\+1c> 38008000	j r1
-00000020 <text_label\+20> 381f0000	j 0
-		RELOC: 00000024 R_ARC_32 .text
-00000028 <text_label\+28> 381f0000	j 0
-		RELOC: 0000002c R_ARC_32 .text
-00000030 <text_label\+30> 381f0000	j 0
-		RELOC: 00000034 R_ARC_32 .text
-00000038 <text_label\+38> 381f0001	jeq 0
-		RELOC: 0000003c R_ARC_32 .text
-00000040 <text_label\+40> 381f0001	jeq 0
-		RELOC: 00000044 R_ARC_32 .text
-00000048 <text_label\+48> 381f0002	jne 0
-		RELOC: 0000004c R_ARC_32 .text
-00000050 <text_label\+50> 381f0002	jne 0
-		RELOC: 00000054 R_ARC_32 .text
-00000058 <text_label\+58> 381f0003	jp 0
-		RELOC: 0000005c R_ARC_32 .text
-00000060 <text_label\+60> 381f0003	jp 0
-		RELOC: 00000064 R_ARC_32 .text
-00000068 <text_label\+68> 381f0004	jn 0
-		RELOC: 0000006c R_ARC_32 .text
-00000070 <text_label\+70> 381f0004	jn 0
-		RELOC: 00000074 R_ARC_32 .text
-00000078 <text_label\+78> 381f0005	jc 0
-		RELOC: 0000007c R_ARC_32 .text
-00000080 <text_label\+80> 381f0005	jc 0
-		RELOC: 00000084 R_ARC_32 .text
-00000088 <text_label\+88> 381f0005	jc 0
-		RELOC: 0000008c R_ARC_32 .text
-00000090 <text_label\+90> 381f0006	jnc 0
-		RELOC: 00000094 R_ARC_32 .text
-00000098 <text_label\+98> 381f0006	jnc 0
-		RELOC: 0000009c R_ARC_32 .text
-000000a0 <text_label\+a0> 381f0006	jnc 0
-		RELOC: 000000a4 R_ARC_32 .text
-000000a8 <text_label\+a8> 381f0007	jv 0
-		RELOC: 000000ac R_ARC_32 .text
-000000b0 <text_label\+b0> 381f0007	jv 0
-		RELOC: 000000b4 R_ARC_32 .text
-000000b8 <text_label\+b8> 381f0008	jnv 0
-		RELOC: 000000bc R_ARC_32 .text
-000000c0 <text_label\+c0> 381f0008	jnv 0
-		RELOC: 000000c4 R_ARC_32 .text
-000000c8 <text_label\+c8> 381f0009	jgt 0
-		RELOC: 000000cc R_ARC_32 .text
-000000d0 <text_label\+d0> 381f000a	jge 0
-		RELOC: 000000d4 R_ARC_32 .text
-000000d8 <text_label\+d8> 381f000b	jlt 0
-		RELOC: 000000dc R_ARC_32 .text
-000000e0 <text_label\+e0> 381f000c	jle 0
-		RELOC: 000000e4 R_ARC_32 .text
-000000e8 <text_label\+e8> 381f000d	jhi 0
-		RELOC: 000000ec R_ARC_32 .text
-000000f0 <text_label\+f0> 381f000e	jls 0
-		RELOC: 000000f4 R_ARC_32 .text
-000000f8 <text_label\+f8> 381f000f	jpnz 0
-		RELOC: 000000fc R_ARC_32 .text
-00000100 <text_label\+100> 381f0000	j 0
-		RELOC: 00000104 R_ARC_32 external_text_label
-00000108 <text_label\+108> 381f0000	j 0
+
+00000000 <text_label>:
+   0:	00 00 1f 38 	381f0000     j          0 <text_label>
+
+   4:	00 00 00 00 
+			4: R_ARC_B26	.text
+   8:	00 00 1f 38 	381f0000     j          0 <text_label>
+
+   c:	00 00 00 00 
+			c: R_ARC_B26	.text
+  10:	00 00 1f 38 	381f0000     j          0 <text_label>
+
+  14:	00 00 00 00 
+			14: R_ARC_B26	.text
+  18:	01 00 1f 38 	381f0001     jz         0 <text_label>
+
+  1c:	00 00 00 00 
+			1c: R_ARC_B26	.text
+  20:	01 00 1f 38 	381f0001     jz         0 <text_label>
+
+  24:	00 00 00 00 
+			24: R_ARC_B26	.text
+  28:	02 00 1f 38 	381f0002     jnz        0 <text_label>
+
+  2c:	00 00 00 00 
+			2c: R_ARC_B26	.text
+  30:	02 00 1f 38 	381f0002     jnz        0 <text_label>
+
+  34:	00 00 00 00 
+			34: R_ARC_B26	.text
+  38:	03 00 1f 38 	381f0003     jp         0 <text_label>
+
+  3c:	00 00 00 00 
+			3c: R_ARC_B26	.text
+  40:	03 00 1f 38 	381f0003     jp         0 <text_label>
+
+  44:	00 00 00 00 
+			44: R_ARC_B26	.text
+  48:	04 00 1f 38 	381f0004     jn         0 <text_label>
+
+  4c:	00 00 00 00 
+			4c: R_ARC_B26	.text
+  50:	04 00 1f 38 	381f0004     jn         0 <text_label>
+
+  54:	00 00 00 00 
+			54: R_ARC_B26	.text
+  58:	05 00 1f 38 	381f0005     jc         0 <text_label>
+
+  5c:	00 00 00 00 
+			5c: R_ARC_B26	.text
+  60:	05 00 1f 38 	381f0005     jc         0 <text_label>
+
+  64:	00 00 00 00 
+			64: R_ARC_B26	.text
+  68:	05 00 1f 38 	381f0005     jc         0 <text_label>
+
+  6c:	00 00 00 00 
+			6c: R_ARC_B26	.text
+  70:	06 00 1f 38 	381f0006     jnc        0 <text_label>
+
+  74:	00 00 00 00 
+			74: R_ARC_B26	.text
+  78:	06 00 1f 38 	381f0006     jnc        0 <text_label>
+
+  7c:	00 00 00 00 
+			7c: R_ARC_B26	.text
+  80:	06 00 1f 38 	381f0006     jnc        0 <text_label>
+
+  84:	00 00 00 00 
+			84: R_ARC_B26	.text
+  88:	07 00 1f 38 	381f0007     jv         0 <text_label>
+
+  8c:	00 00 00 00 
+			8c: R_ARC_B26	.text
+  90:	07 00 1f 38 	381f0007     jv         0 <text_label>
+
+  94:	00 00 00 00 
+			94: R_ARC_B26	.text
+  98:	08 00 1f 38 	381f0008     jnv        0 <text_label>
+
+  9c:	00 00 00 00 
+			9c: R_ARC_B26	.text
+  a0:	08 00 1f 38 	381f0008     jnv        0 <text_label>
+
+  a4:	00 00 00 00 
+			a4: R_ARC_B26	.text
+  a8:	09 00 1f 38 	381f0009     jgt        0 <text_label>
+
+  ac:	00 00 00 00 
+			ac: R_ARC_B26	.text
+  b0:	0a 00 1f 38 	381f000a     jge        0 <text_label>
+
+  b4:	00 00 00 00 
+			b4: R_ARC_B26	.text
+  b8:	0b 00 1f 38 	381f000b     jlt        0 <text_label>
+
+  bc:	00 00 00 00 
+			bc: R_ARC_B26	.text
+  c0:	0c 00 1f 38 	381f000c     jle        0 <text_label>
+
+  c4:	00 00 00 00 
+			c4: R_ARC_B26	.text
+  c8:	0d 00 1f 38 	381f000d     jhi        0 <text_label>
+
+  cc:	00 00 00 00 
+			cc: R_ARC_B26	.text
+  d0:	0e 00 1f 38 	381f000e     jls        0 <text_label>
+
+  d4:	00 00 00 00 
+			d4: R_ARC_B26	.text
+  d8:	0f 00 1f 38 	381f000f     jpnz       0 <text_label>
+
+  dc:	00 00 00 00 
+			dc: R_ARC_B26	.text
+  e0:	00 00 1f 38 	381f0000     j          0 <text_label>
+
+  e4:	00 00 00 00 
+			e4: R_ARC_B26	external_text_label
+  e8:	00 00 1f 38 	381f0000     j          0 <text_label>
+
+  ec:	00 00 00 00 
diff --git a/gas/testsuite/gas/arc/j.s b/gas/testsuite/gas/arc/j.s
index 0161af2..64abbf5 100644
--- a/gas/testsuite/gas/arc/j.s
+++ b/gas/testsuite/gas/arc/j.s
@@ -1,15 +1,6 @@
 # j test
 	
 text_label:	
-	j	r0
-	j.d	r0
-	j.jd	r0
-	j.nd	r0
-
-	j.f	[r1]
-	j.d.f	[r1]
-	j.jd.f	[r1]
-	j.nd.f	[r1]
 
 	j	text_label
 	jal	text_label
diff --git a/gas/testsuite/gas/arc/jl.d b/gas/testsuite/gas/arc/jl.d
new file mode 100644
index 0000000..3701f9a
--- /dev/null
+++ b/gas/testsuite/gas/arc/jl.d
@@ -0,0 +1,25 @@
+#as: -EL -marc6
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <text_label>:
+   0:	40 02 1f 38 	381f0240     jl         0 <text_label>
+
+   4:	00 00 00 00 
+			4: R_ARC_B26	.text
+   8:	40 03 1f 38 	381f0340     jl.f       0 <text_label>
+
+   c:	00 00 00 00 
+			c: R_ARC_B26	.text
+  10:	02 82 00 38 	38008202     jlnz       \[r1\]
+  14:	40 02 1f 38 	381f0240     jl         0 <text_label>
+
+  18:	00 00 00 00 
+			18: R_ARC_B26	.text
+  1c:	40 03 1f 38 	381f0340     jl.f       0 <text_label>
+
+  20:	00 00 00 00 
+			20: R_ARC_B26	.text
diff --git a/gas/testsuite/gas/arc/jl.s b/gas/testsuite/gas/arc/jl.s
new file mode 100644
index 0000000..74a9e20
--- /dev/null
+++ b/gas/testsuite/gas/arc/jl.s
@@ -0,0 +1,9 @@
+# jl test
+
+text_label:
+
+	jl	text_label
+	jl.f	text_label
+	jlnz.nd	[r1]
+	jlal	text_label
+	jlal.f	text_label
diff --git a/gas/testsuite/gas/arc/ld.d b/gas/testsuite/gas/arc/ld.d
index d6dd0a1..b989f8b 100644
--- a/gas/testsuite/gas/arc/ld.d
+++ b/gas/testsuite/gas/arc/ld.d
@@ -1,30 +1,13 @@
-#objdump: -dr
-#name: ld/lr
-
-# Test the ld/lr insn.
+#as: -EL
+#objdump: -dr -EL
 
 .*: +file format elf32-.*arc
 
 Disassembly of section .text:
-00000000 08008000	ld r0,\[r1\]
-00000004 00418800	ld r2,\[r3,r4\]
-00000008 08a30001	ld r5,\[r6,1\]
-0000000c 08e401ff	ld r7,\[r8,-1\]
-00000010 092500ff	ld r9,\[r10,255\]
-00000014 09660100	ld r11,\[r12,-256\]
-00000018 01a77c00	ld r13,\[r14,256\]
-00000020 01e87c00	ld r15,\[r16,-257\]
-00000028 023f3800	ld r17,\[305419896,sp\]
-00000030 0a7f0000	ld r19,\[0\]
-		RELOC: 00000034 R_ARC_32 foo
-00000038 0a9f0000	ld r20,\[4\]
-		RELOC: 0000003c R_ARC_32 foo
-00000040 081f8400	ldb r0,\[0\]
-00000044 081f8800	ldw r0,\[0\]
-00000048 081f8200	ld.x r0,\[0\]
-0000004c 081f9000	ld.a r0,\[0\]
-00000050 081fc000	ld.di r0,\[0\]
-00000054 08005600	ldb.x.a.di r0,\[r0\]
-00000058 0800a000	lr r0,\[r1\]
-0000005c 085fa000	lr r2,\[status\]
-00000060 087f2000	lr r3,\[305419896\]
+
+00000000 <.text>:
+   0:	00 84 00 00 	00008400     ld         r0,\[r1,r2\]
+   4:	02 84 00 00 	00008402     ldb        r0,\[r1,r2\]
+   8:	08 88 21 00 	00218808     ld.a       r1,\[r3,r4\]
+   c:	05 06 21 00 	00210605     ldw.x      r1,\[r2,r3\]
+  10:	0d 88 41 00 	0041880d     ldw.x.a    r2,\[r3,r4\]
diff --git a/gas/testsuite/gas/arc/ld.s b/gas/testsuite/gas/arc/ld.s
index aa26719..36edf9c 100644
--- a/gas/testsuite/gas/arc/ld.s
+++ b/gas/testsuite/gas/arc/ld.s
@@ -1,24 +1,7 @@
-# ld/lr test
+# ld test
 	
-	ld	r0,[r1]
-	ld	r2,[r3,r4]
-	ld	r5,[r6,1]
-	ld	r7,[r8,-1]
-	ld	r9,[r10,255]
-	ld	r11,[r12,-256]
-	ld	r13,[r14,256]
-	ld	r15,[r16,-257]
-	ld	r17,[0x12345678,r28]
-	ld	r19,[foo]
-	ld	r20,[foo+4]
-
-	ldb	r0,[0]
-	ldw	r0,[0]
-	ld.x	r0,[0]
-	ld.a	r0,[0]
-	ld.di	r0,[0]
-	ldb.x.a.di r0,[r0]
-
-	lr	r0,[r1]
-	lr	r2,[status]
-	lr	r3,[0x12345678]
+	ld	r0,[r1,r2]
+	ldb	r0,[r1,r2]
+	ld.a	r1,[r3,r4]
+	ldw.x	r1,[r2,r3]
+	ldw.x.a	r2,[r3,r4]
diff --git a/gas/testsuite/gas/arc/ld2.d b/gas/testsuite/gas/arc/ld2.d
new file mode 100644
index 0000000..1f1df97
--- /dev/null
+++ b/gas/testsuite/gas/arc/ld2.d
@@ -0,0 +1,21 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 80 00 08 	08008000     ld         r0,\[r1\]
+   4:	01 00 a3 08 	08a30001     ld         r5,\[r6,1\]
+   8:	00 00 7f 0a 	0a7f0000     ld         r19,\[0\]
+   c:	00 00 00 00 
+			c: R_ARC_32	foo
+  10:	0a 10 81 08 	0881100a     ld.a       r4,\[r2,10\]
+  14:	00 00 3f 08 	083f0000     ld         r1,\[0x384\]
+  18:	84 03 00 00 
+  1c:	0f 84 41 08 	0841840f     ldb        r2,\[r3,15\]
+  20:	fe 09 62 08 	086209fe     ldw        r3,\[r4,-2\]
+  24:	00 20 21 08 	08212000     lr         r1,\[r2\]
+  28:	14 a0 3f 08 	083fa014     lr         r1,\[0x14\]
+  2c:	00 a0 1f 08 	081fa000     lr         r0,\[status\]
diff --git a/gas/testsuite/gas/arc/ld2.s b/gas/testsuite/gas/arc/ld2.s
new file mode 100644
index 0000000..c18556a
--- /dev/null
+++ b/gas/testsuite/gas/arc/ld2.s
@@ -0,0 +1,13 @@
+# ld/lr test
+
+	ld	r0,[r1]
+	ld	r5,[r6,1]
+	ld	r19,[foo]
+	ld.a	r4,[r2,10]
+	ld	r1,[900]
+	ldb	r2,[r3,15]
+	ldw	r3,[r4,-2]
+	
+	lr	r1,[r2]
+	lr	r1,[20]
+	lr	r0,[status]
diff --git a/gas/testsuite/gas/arc/lp.d b/gas/testsuite/gas/arc/lp.d
new file mode 100644
index 0000000..3b1827c
--- /dev/null
+++ b/gas/testsuite/gas/arc/lp.d
@@ -0,0 +1,76 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <text_label>:
+   0:	80 ff ff 37 	37ffff80     lp         0 <text_label>
+
+   4:	00 ff ff 37 	37ffff00     lp         0 <text_label>
+
+   8:	80 fe ff 37 	37fffe80     lp         0 <text_label>
+
+   c:	01 fe ff 37 	37fffe01     lpz        0 <text_label>
+
+  10:	81 fd ff 37 	37fffd81     lpz        0 <text_label>
+
+  14:	02 fd ff 37 	37fffd02     lpnz       0 <text_label>
+
+  18:	82 fc ff 37 	37fffc82     lpnz       0 <text_label>
+
+  1c:	03 fc ff 37 	37fffc03     lpp        0 <text_label>
+
+  20:	83 fb ff 37 	37fffb83     lpp        0 <text_label>
+
+  24:	04 fb ff 37 	37fffb04     lpn        0 <text_label>
+
+  28:	84 fa ff 37 	37fffa84     lpn        0 <text_label>
+
+  2c:	05 fa ff 37 	37fffa05     lpc        0 <text_label>
+
+  30:	85 f9 ff 37 	37fff985     lpc        0 <text_label>
+
+  34:	05 f9 ff 37 	37fff905     lpc        0 <text_label>
+
+  38:	86 f8 ff 37 	37fff886     lpnc       0 <text_label>
+
+  3c:	06 f8 ff 37 	37fff806     lpnc       0 <text_label>
+
+  40:	86 f7 ff 37 	37fff786     lpnc       0 <text_label>
+
+  44:	07 f7 ff 37 	37fff707     lpv        0 <text_label>
+
+  48:	87 f6 ff 37 	37fff687     lpv        0 <text_label>
+
+  4c:	08 f6 ff 37 	37fff608     lpnv       0 <text_label>
+
+  50:	88 f5 ff 37 	37fff588     lpnv       0 <text_label>
+
+  54:	09 f5 ff 37 	37fff509     lpgt       0 <text_label>
+
+  58:	8a f4 ff 37 	37fff48a     lpge       0 <text_label>
+
+  5c:	0b f4 ff 37 	37fff40b     lplt       0 <text_label>
+
+  60:	8c f3 ff 37 	37fff38c     lple       0 <text_label>
+
+  64:	0d f3 ff 37 	37fff30d     lphi       0 <text_label>
+
+  68:	8e f2 ff 37 	37fff28e     lpls       0 <text_label>
+
+  6c:	0f f2 ff 37 	37fff20f     lppnz      0 <text_label>
+
+  70:	a0 f1 ff 37 	37fff1a0     lp.d       0 <text_label>
+
+  74:	00 f1 ff 37 	37fff100     lp         0 <text_label>
+
+  78:	c0 f0 ff 37 	37fff0c0     lp.jd      0 <text_label>
+
+  7c:	21 f0 ff 37 	37fff021     lpz.d      0 <text_label>
+
+  80:	82 ef ff 37 	37ffef82     lpnz       0 <text_label>
+
+  84:	46 ef ff 37 	37ffef46     lpnc.jd    0 <text_label>
+
diff --git a/gas/testsuite/gas/arc/lp.s b/gas/testsuite/gas/arc/lp.s
new file mode 100644
index 0000000..1913976
--- /dev/null
+++ b/gas/testsuite/gas/arc/lp.s
@@ -0,0 +1,40 @@
+# lp test
+	
+text_label:
+
+	lp	text_label
+	lpal	text_label
+	lpra	text_label
+	lpeq	text_label
+	lpz	text_label
+	lpne	text_label
+	lpnz	text_label
+	lppl	text_label
+	lpp	text_label
+	lpmi	text_label
+	lpn	text_label
+	lpcs	text_label
+	lpc	text_label
+	lplo	text_label
+	lpcc	text_label
+	lpnc	text_label
+	lphs	text_label
+	lpvs	text_label
+	lpv	text_label
+	lpvc	text_label
+	lpnv	text_label
+	lpgt	text_label
+	lpge	text_label
+	lplt	text_label
+	lple	text_label
+	lphi	text_label
+	lpls	text_label
+	lppnz	text_label
+
+	lp.d	text_label
+	lp.nd	text_label
+	lp.jd	text_label
+
+	lpeq.d	text_label
+	lpne.nd	text_label
+	lpcc.jd	text_label
diff --git a/gas/testsuite/gas/arc/lsr.d b/gas/testsuite/gas/arc/lsr.d
new file mode 100644
index 0000000..27247a2
--- /dev/null
+++ b/gas/testsuite/gas/arc/lsr.d
@@ -0,0 +1,51 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 84 00 18 	18008400     lsr        r0,r1
+   4:	00 04 6e 1b 	1b6e0400     lsr        fp,sp
+   8:	00 84 1f 18 	181f8400     lsr        r0,0
+   c:	ff 85 3f 18 	183f85ff     lsr        r1,-1
+  10:	00 04 e1 1f 	1fe10400     lsr        0,r2
+  14:	00 84 e1 1f 	1fe18400     lsr        0,r3
+  18:	ff 84 9f 18 	189f84ff     lsr        r4,255
+  1c:	00 84 e2 1f 	1fe28400     lsr        0,r5
+  20:	00 85 df 18 	18df8500     lsr        r6,-256
+  24:	00 84 e3 1f 	1fe38400     lsr        0,r7
+  28:	00 04 1f 19 	191f0400     lsr        r8,0x100
+  2c:	00 01 00 00 
+  30:	00 04 3f 19 	193f0400     lsr        r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 04 7f 19 	197f0400     lsr        r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 04 ff 1f 	1fff0400     lsr        0,0x100
+  44:	00 01 00 00 
+  48:	00 04 1f 18 	181f0400     lsr        r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	01 84 45 19 	19458401     lsr.z      r10,r11
+  54:	02 84 86 19 	19868402     lsr.nz     r12,r13
+  58:	0b 04 df 19 	19df040b     lsr.lt     r14,0
+  5c:	00 00 00 00 
+  60:	09 04 ff 19 	19ff0409     lsr.gt     r15,0x200
+  64:	00 02 00 00 
+  68:	00 85 00 18 	18008500     lsr.f      r0,r1
+  6c:	01 84 5e 18 	185e8401     lsr.f      r2,1
+  70:	00 05 e2 1f 	1fe20500     lsr.f      0,r4
+  74:	00 05 bf 18 	18bf0500     lsr.f      r5,0x200
+  78:	00 02 00 00 
+  7c:	00 05 df 1f 	1fdf0500     lsr.f      0,0x200
+  80:	00 02 00 00 
+  84:	01 85 00 18 	18008501     lsr.z.f    r0,r1
+  88:	02 05 3f 18 	183f0502     lsr.nz.f   r1,0
+  8c:	00 00 00 00 
+  90:	0b 05 c1 1f 	1fc1050b     lsr.lt.f   0,r2
+  94:	00 00 00 00 	00000000                
+  98:	0c 05 1f 18 	181f050c     lsr.le.f   r0,0x200
+  9c:	00 02 00 00 
+  a0:	04 05 df 1f 	1fdf0504     lsr.n.f    0,0x200
+  a4:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/lsr.s b/gas/testsuite/gas/arc/lsr.s
new file mode 100644
index 0000000..3f539d8
--- /dev/null
+++ b/gas/testsuite/gas/arc/lsr.s
@@ -0,0 +1,38 @@
+# lsr test
+
+	lsr r0,r1
+	lsr fp,sp
+
+	lsr r0,0
+	lsr r1,-1
+	lsr 0,r2
+	lsr -1,r3
+	lsr r4,255
+	lsr 255,r5
+	lsr r6,-256
+	lsr -256,r7
+
+	lsr r8,256
+	lsr r9,-257
+	lsr r11,0x42424242
+
+	lsr 255,256
+
+	lsr r0,foo
+
+	lsr.eq r10,r11
+	lsr.ne r12,r13
+	lsr.lt r14,0
+	lsr.gt r15,512
+
+	lsr.f r0,r1
+	lsr.f r2,1
+	lsr.f 0,r4
+	lsr.f r5,512
+	lsr.f 512,512
+
+	lsr.eq.f r0,r1
+	lsr.ne.f r1,0
+	lsr.lt.f 0,r2
+	lsr.le.f r0,512
+	lsr.n.f 512,512
diff --git a/gas/testsuite/gas/arc/mov.d b/gas/testsuite/gas/arc/mov.d
new file mode 100644
index 0000000..cff11d7
--- /dev/null
+++ b/gas/testsuite/gas/arc/mov.d
@@ -0,0 +1,68 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 82 00 60 	60008200     mov        r0,r1
+   4:	00 38 6e 63 	636e3800     mov        fp,sp
+   8:	00 fe 1f 60 	601ffe00     mov        r0,0
+   c:	ff ff 3f 60 	603fffff     mov        r1,-1
+  10:	00 04 e1 67 	67e10400     mov        0,r2
+  14:	00 86 e1 67 	67e18600     mov        0,r3
+  18:	ff fe 9f 60 	609ffeff     mov        r4,255
+  1c:	00 8a e2 67 	67e28a00     mov        0,r5
+  20:	00 ff df 60 	60dfff00     mov        r6,-256
+  24:	00 8e e3 67 	67e38e00     mov        0,r7
+  28:	00 7c 1f 61 	611f7c00     mov        r8,0x100
+  2c:	00 01 00 00 
+  30:	00 7c 3f 61 	613f7c00     mov        r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 7c 7f 61 	617f7c00     mov        r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 7c ff 67 	67ff7c00     mov        0,0x100
+  44:	00 01 00 00 
+  48:	00 7c 1f 60 	601f7c00     mov        r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	00 82 00 60 	60008200     mov        r0,r1
+  54:	00 08 62 60 	60620800     mov        r3,r4
+  58:	01 8e c3 60 	60c38e01     mov.z      r6,r7
+  5c:	01 14 25 61 	61251401     mov.z      r9,r10
+  60:	02 9a 86 61 	61869a02     mov.nz     r12,r13
+  64:	02 20 e8 61 	61e82002     mov.nz     r15,r16
+  68:	03 a6 49 62 	6249a603     mov.p      r18,r19
+  6c:	03 2c ab 62 	62ab2c03     mov.p      r21,r22
+  70:	04 b2 0c 63 	630cb204     mov.n      r24,r25
+  74:	04 38 6e 63 	636e3804     mov.n      fp,sp
+  78:	05 be cf 63 	63cfbe05     mov.c      ilink2,blink
+  7c:	05 44 31 64 	64314405     mov.c      r33,r34
+  80:	05 ca 92 64 	6492ca05     mov.c      r36,r37
+  84:	06 50 f4 64 	64f45006     mov.nc     r39,r40
+  88:	06 d6 55 65 	6555d606     mov.nc     r42,r43
+  8c:	06 5c b7 65 	65b75c06     mov.nc     r45,r46
+  90:	07 e2 18 66 	6618e207     mov.v      r48,r49
+  94:	07 64 39 66 	66396407     mov.v      r49,r50
+  98:	08 ee 3b 66 	663bee08     mov.nv     r49,r55
+  9c:	08 74 3d 66 	663d7408     mov.nv     r49,r58
+  a0:	09 78 9e 67 	679e7809     mov.gt     lp_count,lp_count
+  a4:	0a 7c 1f 60 	601f7c0a     mov.ge     r0,0
+  a8:	00 00 00 00 
+  ac:	0c 7c df 67 	67df7c0c     mov.le     0,2
+  b0:	02 00 00 00 
+  b4:	0d 86 61 60 	6061860d     mov.hi     r3,r3
+  b8:	0e 08 82 60 	6082080e     mov.ls     r4,r4
+  bc:	0f 8a a2 60 	60a28a0f     mov.pnz    r5,r5
+  c0:	00 83 00 60 	60008300     mov.f      r0,r1
+  c4:	01 fa 5e 60 	605efa01     mov.f      r2,1
+  c8:	00 87 e1 67 	67e18700     mov.f      0,r3
+  cc:	00 09 e2 67 	67e20900     mov.f      0,r4
+  d0:	00 7d bf 60 	60bf7d00     mov.f      r5,0x200
+  d4:	00 02 00 00 
+  d8:	00 7d df 67 	67df7d00     mov.f      0,0x200
+  dc:	00 02 00 00 
+  e0:	01 83 00 60 	60008301     mov.z.f    r0,r1
+  e4:	02 7d 3f 60 	603f7d02     mov.nz.f   r1,0
+  e8:	00 00 00 00 
diff --git a/gas/testsuite/gas/arc/mov.s b/gas/testsuite/gas/arc/mov.s
new file mode 100644
index 0000000..fdee0b7
--- /dev/null
+++ b/gas/testsuite/gas/arc/mov.s
@@ -0,0 +1,58 @@
+# mov test
+
+	mov r0,r1
+	mov fp,sp
+
+	mov r0,0
+	mov r1,-1
+	mov 0,r2
+	mov -1,r3
+	mov r4,255
+	mov 255,r5
+	mov r6,-256
+	mov -256,r7
+
+	mov r8,256
+	mov r9,-257
+	mov r11,0x42424242
+
+	mov 255,256
+
+	mov r0,foo
+
+	mov.al r0,r1
+	mov.ra r3,r4
+	mov.eq r6,r7
+	mov.z r9,r10
+	mov.ne r12,r13
+	mov.nz r15,r16
+	mov.pl r18,r19
+	mov.p r21,r22
+	mov.mi r24,r25
+	mov.n r27,r28
+	mov.cs r30,r31
+	mov.c r33,r34
+	mov.lo r36,r37
+	mov.cc r39,r40
+	mov.nc r42,r43
+	mov.hs r45,r46
+	mov.vs r48,r49
+	mov.v r49,r50
+	mov.vc r49,r55
+	mov.nv r49,r58
+	mov.gt r60,r60
+	mov.ge r0,0
+	mov.le 2,2
+	mov.hi r3,r3
+	mov.ls r4,r4
+	mov.pnz r5,r5
+
+	mov.f r0,r1
+	mov.f r2,1
+	mov.f 1,r3
+	mov.f 0,r4
+	mov.f r5,512
+	mov.f 512,512
+
+	mov.eq.f r0,r1
+	mov.ne.f r1,0
diff --git a/gas/testsuite/gas/arc/nop.d b/gas/testsuite/gas/arc/nop.d
new file mode 100644
index 0000000..1a714cd
--- /dev/null
+++ b/gas/testsuite/gas/arc/nop.d
@@ -0,0 +1,9 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	ff ff ff 7f 	7fffffff     nop        
diff --git a/gas/testsuite/gas/arc/nop.s b/gas/testsuite/gas/arc/nop.s
new file mode 100644
index 0000000..02b2681
--- /dev/null
+++ b/gas/testsuite/gas/arc/nop.s
@@ -0,0 +1,3 @@
+# nop test
+
+	nop
diff --git a/gas/testsuite/gas/arc/or.d b/gas/testsuite/gas/arc/or.d
new file mode 100644
index 0000000..11e6f3c
--- /dev/null
+++ b/gas/testsuite/gas/arc/or.d
@@ -0,0 +1,85 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 84 00 68 	68008400     or         r0,r1,r2
+   4:	00 b8 4d 6b 	6b4db800     or         gp,fp,sp
+   8:	00 3e af 6b 	6baf3e00     or         ilink1,ilink2,blink
+   c:	00 f8 1d 6f 	6f1df800     or         r56,r59,lp_count
+  10:	00 fe 00 68 	6800fe00     or         r0,r1,0
+  14:	00 84 1f 68 	681f8400     or         r0,0,r2
+  18:	00 84 e0 6f 	6fe08400     or         0,r1,r2
+  1c:	ff ff 00 68 	6800ffff     or         r0,r1,-1
+  20:	ff 85 1f 68 	681f85ff     or         r0,-1,r2
+  24:	00 84 e0 6f 	6fe08400     or         0,r1,r2
+  28:	ff fe 00 68 	6800feff     or         r0,r1,255
+  2c:	ff 84 1f 68 	681f84ff     or         r0,255,r2
+  30:	00 84 e0 6f 	6fe08400     or         0,r1,r2
+  34:	00 ff 00 68 	6800ff00     or         r0,r1,-256
+  38:	00 85 1f 68 	681f8500     or         r0,-256,r2
+  3c:	00 84 e0 6f 	6fe08400     or         0,r1,r2
+  40:	00 fc 00 68 	6800fc00     or         r0,r1,0x100
+  44:	00 01 00 00 
+  48:	00 04 1f 68 	681f0400     or         r0,0xffff_feff,r2
+  4c:	ff fe ff ff 
+  50:	ff fc 1f 68 	681ffcff     or         r0,255,0x100
+  54:	00 01 00 00 
+  58:	ff 7e 1f 68 	681f7eff     or         r0,0x100,255
+  5c:	00 01 00 00 
+  60:	00 fc 00 68 	6800fc00     or         r0,r1,0
+  64:	00 00 00 00 
+			64: R_ARC_32	foo
+  68:	00 84 00 68 	68008400     or         r0,r1,r2
+  6c:	00 0a 62 68 	68620a00     or         r3,r4,r5
+  70:	01 90 c3 68 	68c39001     or.z       r6,r7,r8
+  74:	01 16 25 69 	69251601     or.z       r9,r10,r11
+  78:	02 9c 86 69 	69869c02     or.nz      r12,r13,r14
+  7c:	02 22 e8 69 	69e82202     or.nz      r15,r16,r17
+  80:	03 a8 49 6a 	6a49a803     or.p       r18,r19,r20
+  84:	03 2e ab 6a 	6aab2e03     or.p       r21,r22,r23
+  88:	04 b4 0c 6b 	6b0cb404     or.n       r24,r25,gp
+  8c:	04 3a 6e 6b 	6b6e3a04     or.n       fp,sp,ilink1
+  90:	05 c0 cf 6b 	6bcfc005     or.c       ilink2,blink,r32
+  94:	05 46 31 6c 	6c314605     or.c       r33,r34,r35
+  98:	05 cc 92 6c 	6c92cc05     or.c       r36,r37,r38
+  9c:	06 52 f4 6c 	6cf45206     or.nc      r39,r40,r41
+  a0:	06 d8 55 6d 	6d55d806     or.nc      r42,r43,r44
+  a4:	06 5e b7 6d 	6db75e06     or.nc      r45,r46,r47
+  a8:	07 e4 18 6e 	6e18e407     or.v       r48,r49,r50
+  ac:	07 6a 1a 6f 	6f1a6a07     or.v       r56,r52,r53
+  b0:	08 f0 1b 6f 	6f1bf008     or.nv      r56,r55,r56
+  b4:	08 76 1d 6f 	6f1d7608     or.nv      r56,r58,r59
+  b8:	09 00 9e 6f 	6f9e0009     or.gt      lp_count,lp_count,r0
+  bc:	0a 7c 00 68 	68007c0a     or.ge      r0,r0,0
+  c0:	00 00 00 00 
+  c4:	0b 02 3f 68 	683f020b     or.lt      r1,1,r1
+  c8:	01 00 00 00 
+  cc:	0d 06 7f 68 	687f060d     or.hi      r3,3,r3
+  d0:	03 00 00 00 
+  d4:	0e 08 df 6f 	6fdf080e     or.ls      0,4,r4
+  d8:	04 00 00 00 
+  dc:	0f fc c2 6f 	6fc2fc0f     or.pnz     0,r5,5
+  e0:	05 00 00 00 
+  e4:	00 85 00 68 	68008500     or.f       r0,r1,r2
+  e8:	01 fa 00 68 	6800fa01     or.f       r0,r1,1
+  ec:	01 84 1e 68 	681e8401     or.f       r0,1,r2
+  f0:	00 85 e0 6f 	6fe08500     or.f       0,r1,r2
+  f4:	00 fd 00 68 	6800fd00     or.f       r0,r1,0x200
+  f8:	00 02 00 00 
+  fc:	00 05 1f 68 	681f0500     or.f       r0,0x200,r2
+ 100:	00 02 00 00 
+ 104:	01 85 00 68 	68008501     or.z.f     r0,r1,r2
+ 108:	02 fd 00 68 	6800fd02     or.nz.f    r0,r1,0
+ 10c:	00 00 00 00 
+ 110:	0b 05 1f 68 	681f050b     or.lt.f    r0,0,r2
+ 114:	00 00 00 00 
+ 118:	09 85 c0 6f 	6fc08509     or.gt.f    0,r1,r2
+ 11c:	00 00 00 00 	00000000                
+ 120:	0c fd 00 68 	6800fd0c     or.le.f    r0,r1,0x200
+ 124:	00 02 00 00 
+ 128:	0a 05 1f 68 	681f050a     or.ge.f    r0,0x200,r2
+ 12c:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/or.s b/gas/testsuite/gas/arc/or.s
new file mode 100644
index 0000000..e363352
--- /dev/null
+++ b/gas/testsuite/gas/arc/or.s
@@ -0,0 +1,68 @@
+# or test
+
+	or r0,r1,r2
+	or r26,fp,sp
+	or ilink1,ilink2,blink
+	or r56,r59,lp_count
+
+	or r0,r1,0
+	or r0,0,r2
+	or 0,r1,r2
+	or r0,r1,-1
+	or r0,-1,r2
+	or -1,r1,r2
+	or r0,r1,255
+	or r0,255,r2
+	or 255,r1,r2
+	or r0,r1,-256
+	or r0,-256,r2
+	or -256,r1,r2
+
+	or r0,r1,256
+	or r0,-257,r2
+
+	or r0,255,256
+	or r0,256,255
+
+	or r0,r1,foo
+
+	or.al r0,r1,r2
+	or.ra r3,r4,r5
+	or.eq r6,r7,r8
+	or.z r9,r10,r11
+	or.ne r12,r13,r14
+	or.nz r15,r16,r17
+	or.pl r18,r19,r20
+	or.p r21,r22,r23
+	or.mi r24,r25,r26
+	or.n r27,r28,r29
+	or.cs r30,r31,r32
+	or.c r33,r34,r35
+	or.lo r36,r37,r38
+	or.cc r39,r40,r41
+	or.nc r42,r43,r44
+	or.hs r45,r46,r47
+	or.vs r48,r49,r50
+	or.v r56,r52,r53
+	or.vc r56,r55,r56
+	or.nv r56,r58,r59
+	or.gt r60,r60,r0
+	or.ge r0,r0,0
+	or.lt r1,1,r1
+	or.hi r3,3,r3
+	or.ls 4,4,r4
+	or.pnz 5,r5,5
+
+	or.f r0,r1,r2
+	or.f r0,r1,1
+	or.f r0,1,r2
+	or.f 0,r1,r2
+	or.f r0,r1,512
+	or.f r0,512,r2
+
+	or.eq.f r0,r1,r2
+	or.ne.f r0,r1,0
+	or.lt.f r0,0,r2
+	or.gt.f 0,r1,r2
+	or.le.f r0,r1,512
+	or.ge.f r0,512,r2
diff --git a/gas/testsuite/gas/arc/rlc.d b/gas/testsuite/gas/arc/rlc.d
new file mode 100644
index 0000000..e83ddc4
--- /dev/null
+++ b/gas/testsuite/gas/arc/rlc.d
@@ -0,0 +1,68 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 82 00 48 	48008200     rlc        r0,r1
+   4:	00 38 6e 4b 	4b6e3800     rlc        fp,sp
+   8:	00 fe 1f 48 	481ffe00     rlc        r0,0
+   c:	ff ff 3f 48 	483fffff     rlc        r1,-1
+  10:	00 04 e1 4f 	4fe10400     rlc        0,r2
+  14:	00 86 e1 4f 	4fe18600     rlc        0,r3
+  18:	ff fe 9f 48 	489ffeff     rlc        r4,255
+  1c:	00 8a e2 4f 	4fe28a00     rlc        0,r5
+  20:	00 ff df 48 	48dfff00     rlc        r6,-256
+  24:	00 8e e3 4f 	4fe38e00     rlc        0,r7
+  28:	00 7c 1f 49 	491f7c00     rlc        r8,0x100
+  2c:	00 01 00 00 
+  30:	00 7c 3f 49 	493f7c00     rlc        r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 7c 7f 49 	497f7c00     rlc        r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 7c ff 4f 	4fff7c00     rlc        0,0x100
+  44:	00 01 00 00 
+  48:	00 7c 1f 48 	481f7c00     rlc        r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	00 82 00 48 	48008200     rlc        r0,r1
+  54:	00 08 62 48 	48620800     rlc        r3,r4
+  58:	01 8e c3 48 	48c38e01     rlc.z      r6,r7
+  5c:	01 14 25 49 	49251401     rlc.z      r9,r10
+  60:	02 9a 86 49 	49869a02     rlc.nz     r12,r13
+  64:	02 20 e8 49 	49e82002     rlc.nz     r15,r16
+  68:	03 a6 49 4a 	4a49a603     rlc.p      r18,r19
+  6c:	03 2c ab 4a 	4aab2c03     rlc.p      r21,r22
+  70:	04 b2 0c 4b 	4b0cb204     rlc.n      r24,r25
+  74:	04 38 6e 4b 	4b6e3804     rlc.n      fp,sp
+  78:	05 be cf 4b 	4bcfbe05     rlc.c      ilink2,blink
+  7c:	05 44 31 4c 	4c314405     rlc.c      r33,r34
+  80:	05 ca 92 4c 	4c92ca05     rlc.c      r36,r37
+  84:	06 50 f4 4c 	4cf45006     rlc.nc     r39,r40
+  88:	06 d6 55 4d 	4d55d606     rlc.nc     r42,r43
+  8c:	06 5c b7 4d 	4db75c06     rlc.nc     r45,r46
+  90:	07 e2 18 4e 	4e18e207     rlc.v      r48,r49
+  94:	07 64 39 4e 	4e396407     rlc.v      r49,r50
+  98:	08 ee 3b 4e 	4e3bee08     rlc.nv     r49,r55
+  9c:	08 74 3d 4e 	4e3d7408     rlc.nv     r49,r58
+  a0:	09 78 9e 4f 	4f9e7809     rlc.gt     lp_count,lp_count
+  a4:	0a 7c 1f 48 	481f7c0a     rlc.ge     r0,0
+  a8:	00 00 00 00 
+  ac:	0c 7c df 4f 	4fdf7c0c     rlc.le     0,2
+  b0:	02 00 00 00 
+  b4:	0d 86 61 48 	4861860d     rlc.hi     r3,r3
+  b8:	0e 08 82 48 	4882080e     rlc.ls     r4,r4
+  bc:	0f 8a a2 48 	48a28a0f     rlc.pnz    r5,r5
+  c0:	00 83 00 48 	48008300     rlc.f      r0,r1
+  c4:	01 fa 5e 48 	485efa01     rlc.f      r2,1
+  c8:	00 87 e1 4f 	4fe18700     rlc.f      0,r3
+  cc:	00 09 e2 4f 	4fe20900     rlc.f      0,r4
+  d0:	00 7d bf 48 	48bf7d00     rlc.f      r5,0x200
+  d4:	00 02 00 00 
+  d8:	00 7d df 4f 	4fdf7d00     rlc.f      0,0x200
+  dc:	00 02 00 00 
+  e0:	01 83 00 48 	48008301     rlc.z.f    r0,r1
+  e4:	02 7d 3f 48 	483f7d02     rlc.nz.f   r1,0
+  e8:	00 00 00 00 
diff --git a/gas/testsuite/gas/arc/rlc.s b/gas/testsuite/gas/arc/rlc.s
new file mode 100644
index 0000000..3e5d093
--- /dev/null
+++ b/gas/testsuite/gas/arc/rlc.s
@@ -0,0 +1,58 @@
+# rlc test
+
+	rlc r0,r1
+	rlc fp,sp
+
+	rlc r0,0
+	rlc r1,-1
+	rlc 0,r2
+	rlc -1,r3
+	rlc r4,255
+	rlc 255,r5
+	rlc r6,-256
+	rlc -256,r7
+
+	rlc r8,256
+	rlc r9,-257
+	rlc r11,0x42424242
+
+	rlc 255,256
+
+	rlc r0,foo
+
+	rlc.al r0,r1
+	rlc.ra r3,r4
+	rlc.eq r6,r7
+	rlc.z r9,r10
+	rlc.ne r12,r13
+	rlc.nz r15,r16
+	rlc.pl r18,r19
+	rlc.p r21,r22
+	rlc.mi r24,r25
+	rlc.n r27,r28
+	rlc.cs r30,r31
+	rlc.c r33,r34
+	rlc.lo r36,r37
+	rlc.cc r39,r40
+	rlc.nc r42,r43
+	rlc.hs r45,r46
+	rlc.vs r48,r49
+	rlc.v r49,r50
+	rlc.vc r49,r55
+	rlc.nv r49,r58
+	rlc.gt r60,r60
+	rlc.ge r0,0
+	rlc.le 2,2
+	rlc.hi r3,r3
+	rlc.ls r4,r4
+	rlc.pnz r5,r5
+
+	rlc.f r0,r1
+	rlc.f r2,1
+	rlc.f 1,r3
+	rlc.f 0,r4
+	rlc.f r5,512
+	rlc.f 512,512
+
+	rlc.eq.f r0,r1
+	rlc.ne.f r1,0
diff --git a/gas/testsuite/gas/arc/ror.d b/gas/testsuite/gas/arc/ror.d
new file mode 100644
index 0000000..691736b
--- /dev/null
+++ b/gas/testsuite/gas/arc/ror.d
@@ -0,0 +1,51 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 86 00 18 	18008600     ror        r0,r1
+   4:	00 06 6e 1b 	1b6e0600     ror        fp,sp
+   8:	00 86 1f 18 	181f8600     ror        r0,0
+   c:	ff 87 3f 18 	183f87ff     ror        r1,-1
+  10:	00 06 e1 1f 	1fe10600     ror        0,r2
+  14:	00 86 e1 1f 	1fe18600     ror        0,r3
+  18:	ff 86 9f 18 	189f86ff     ror        r4,255
+  1c:	00 86 e2 1f 	1fe28600     ror        0,r5
+  20:	00 87 df 18 	18df8700     ror        r6,-256
+  24:	00 86 e3 1f 	1fe38600     ror        0,r7
+  28:	00 06 1f 19 	191f0600     ror        r8,0x100
+  2c:	00 01 00 00 
+  30:	00 06 3f 19 	193f0600     ror        r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 06 7f 19 	197f0600     ror        r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 06 ff 1f 	1fff0600     ror        0,0x100
+  44:	00 01 00 00 
+  48:	00 06 1f 18 	181f0600     ror        r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	01 86 45 19 	19458601     ror.z      r10,r11
+  54:	02 86 86 19 	19868602     ror.nz     r12,r13
+  58:	0b 06 df 19 	19df060b     ror.lt     r14,0
+  5c:	00 00 00 00 
+  60:	09 06 ff 19 	19ff0609     ror.gt     r15,0x200
+  64:	00 02 00 00 
+  68:	00 87 00 18 	18008700     ror.f      r0,r1
+  6c:	01 86 5e 18 	185e8601     ror.f      r2,1
+  70:	00 07 e2 1f 	1fe20700     ror.f      0,r4
+  74:	00 07 bf 18 	18bf0700     ror.f      r5,0x200
+  78:	00 02 00 00 
+  7c:	00 07 df 1f 	1fdf0700     ror.f      0,0x200
+  80:	00 02 00 00 
+  84:	01 87 00 18 	18008701     ror.z.f    r0,r1
+  88:	02 07 3f 18 	183f0702     ror.nz.f   r1,0
+  8c:	00 00 00 00 
+  90:	0b 07 c1 1f 	1fc1070b     ror.lt.f   0,r2
+  94:	00 00 00 00 	00000000                
+  98:	0c 07 1f 18 	181f070c     ror.le.f   r0,0x200
+  9c:	00 02 00 00 
+  a0:	04 07 df 1f 	1fdf0704     ror.n.f    0,0x200
+  a4:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/ror.s b/gas/testsuite/gas/arc/ror.s
new file mode 100644
index 0000000..de23351
--- /dev/null
+++ b/gas/testsuite/gas/arc/ror.s
@@ -0,0 +1,38 @@
+# ror test
+
+	ror r0,r1
+	ror fp,sp
+
+	ror r0,0
+	ror r1,-1
+	ror 0,r2
+	ror -1,r3
+	ror r4,255
+	ror 255,r5
+	ror r6,-256
+	ror -256,r7
+
+	ror r8,256
+	ror r9,-257
+	ror r11,0x42424242
+
+	ror 255,256
+
+	ror r0,foo
+
+	ror.eq r10,r11
+	ror.ne r12,r13
+	ror.lt r14,0
+	ror.gt r15,512
+
+	ror.f r0,r1
+	ror.f r2,1
+	ror.f 0,r4
+	ror.f r5,512
+	ror.f 512,512
+
+	ror.eq.f r0,r1
+	ror.ne.f r1,0
+	ror.lt.f 0,r2
+	ror.le.f r0,512
+	ror.n.f 512,512
diff --git a/gas/testsuite/gas/arc/rrc.d b/gas/testsuite/gas/arc/rrc.d
new file mode 100644
index 0000000..9c702cb
--- /dev/null
+++ b/gas/testsuite/gas/arc/rrc.d
@@ -0,0 +1,51 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 88 00 18 	18008800     rrc        r0,r1
+   4:	00 08 6e 1b 	1b6e0800     rrc        fp,sp
+   8:	00 88 1f 18 	181f8800     rrc        r0,0
+   c:	ff 89 3f 18 	183f89ff     rrc        r1,-1
+  10:	00 08 e1 1f 	1fe10800     rrc        0,r2
+  14:	00 88 e1 1f 	1fe18800     rrc        0,r3
+  18:	ff 88 9f 18 	189f88ff     rrc        r4,255
+  1c:	00 88 e2 1f 	1fe28800     rrc        0,r5
+  20:	00 89 df 18 	18df8900     rrc        r6,-256
+  24:	00 88 e3 1f 	1fe38800     rrc        0,r7
+  28:	00 08 1f 19 	191f0800     rrc        r8,0x100
+  2c:	00 01 00 00 
+  30:	00 08 3f 19 	193f0800     rrc        r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 08 7f 19 	197f0800     rrc        r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 08 ff 1f 	1fff0800     rrc        0,0x100
+  44:	00 01 00 00 
+  48:	00 08 1f 18 	181f0800     rrc        r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	01 88 45 19 	19458801     rrc.z      r10,r11
+  54:	02 88 86 19 	19868802     rrc.nz     r12,r13
+  58:	0b 08 df 19 	19df080b     rrc.lt     r14,0
+  5c:	00 00 00 00 
+  60:	09 08 ff 19 	19ff0809     rrc.gt     r15,0x200
+  64:	00 02 00 00 
+  68:	00 89 00 18 	18008900     rrc.f      r0,r1
+  6c:	01 88 5e 18 	185e8801     rrc.f      r2,1
+  70:	00 09 e2 1f 	1fe20900     rrc.f      0,r4
+  74:	00 09 bf 18 	18bf0900     rrc.f      r5,0x200
+  78:	00 02 00 00 
+  7c:	00 09 df 1f 	1fdf0900     rrc.f      0,0x200
+  80:	00 02 00 00 
+  84:	01 89 00 18 	18008901     rrc.z.f    r0,r1
+  88:	02 09 3f 18 	183f0902     rrc.nz.f   r1,0
+  8c:	00 00 00 00 
+  90:	0b 09 c1 1f 	1fc1090b     rrc.lt.f   0,r2
+  94:	00 00 00 00 	00000000                
+  98:	0c 09 1f 18 	181f090c     rrc.le.f   r0,0x200
+  9c:	00 02 00 00 
+  a0:	04 09 df 1f 	1fdf0904     rrc.n.f    0,0x200
+  a4:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/rrc.s b/gas/testsuite/gas/arc/rrc.s
new file mode 100644
index 0000000..c0e1780
--- /dev/null
+++ b/gas/testsuite/gas/arc/rrc.s
@@ -0,0 +1,38 @@
+# rrc test
+
+	rrc r0,r1
+	rrc fp,sp
+
+	rrc r0,0
+	rrc r1,-1
+	rrc 0,r2
+	rrc -1,r3
+	rrc r4,255
+	rrc 255,r5
+	rrc r6,-256
+	rrc -256,r7
+
+	rrc r8,256
+	rrc r9,-257
+	rrc r11,0x42424242
+
+	rrc 255,256
+
+	rrc r0,foo
+
+	rrc.eq r10,r11
+	rrc.ne r12,r13
+	rrc.lt r14,0
+	rrc.gt r15,512
+
+	rrc.f r0,r1
+	rrc.f r2,1
+	rrc.f 0,r4
+	rrc.f r5,512
+	rrc.f 512,512
+
+	rrc.eq.f r0,r1
+	rrc.ne.f r1,0
+	rrc.lt.f 0,r2
+	rrc.le.f r0,512
+	rrc.n.f 512,512
diff --git a/gas/testsuite/gas/arc/sbc.d b/gas/testsuite/gas/arc/sbc.d
new file mode 100644
index 0000000..7fa0490
--- /dev/null
+++ b/gas/testsuite/gas/arc/sbc.d
@@ -0,0 +1,85 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 84 00 58 	58008400     sbc        r0,r1,r2
+   4:	00 b8 4d 5b 	5b4db800     sbc        gp,fp,sp
+   8:	00 3e af 5b 	5baf3e00     sbc        ilink1,ilink2,blink
+   c:	00 f8 1d 5f 	5f1df800     sbc        r56,r59,lp_count
+  10:	00 fe 00 58 	5800fe00     sbc        r0,r1,0
+  14:	00 84 1f 58 	581f8400     sbc        r0,0,r2
+  18:	00 84 e0 5f 	5fe08400     sbc        0,r1,r2
+  1c:	ff ff 00 58 	5800ffff     sbc        r0,r1,-1
+  20:	ff 85 1f 58 	581f85ff     sbc        r0,-1,r2
+  24:	00 84 e0 5f 	5fe08400     sbc        0,r1,r2
+  28:	ff fe 00 58 	5800feff     sbc        r0,r1,255
+  2c:	ff 84 1f 58 	581f84ff     sbc        r0,255,r2
+  30:	00 84 e0 5f 	5fe08400     sbc        0,r1,r2
+  34:	00 ff 00 58 	5800ff00     sbc        r0,r1,-256
+  38:	00 85 1f 58 	581f8500     sbc        r0,-256,r2
+  3c:	00 84 e0 5f 	5fe08400     sbc        0,r1,r2
+  40:	00 fc 00 58 	5800fc00     sbc        r0,r1,0x100
+  44:	00 01 00 00 
+  48:	00 04 1f 58 	581f0400     sbc        r0,0xffff_feff,r2
+  4c:	ff fe ff ff 
+  50:	ff fc 1f 58 	581ffcff     sbc        r0,255,0x100
+  54:	00 01 00 00 
+  58:	ff 7e 1f 58 	581f7eff     sbc        r0,0x100,255
+  5c:	00 01 00 00 
+  60:	00 fc 00 58 	5800fc00     sbc        r0,r1,0
+  64:	00 00 00 00 
+			64: R_ARC_32	foo
+  68:	00 84 00 58 	58008400     sbc        r0,r1,r2
+  6c:	00 0a 62 58 	58620a00     sbc        r3,r4,r5
+  70:	01 90 c3 58 	58c39001     sbc.z      r6,r7,r8
+  74:	01 16 25 59 	59251601     sbc.z      r9,r10,r11
+  78:	02 9c 86 59 	59869c02     sbc.nz     r12,r13,r14
+  7c:	02 22 e8 59 	59e82202     sbc.nz     r15,r16,r17
+  80:	03 a8 49 5a 	5a49a803     sbc.p      r18,r19,r20
+  84:	03 2e ab 5a 	5aab2e03     sbc.p      r21,r22,r23
+  88:	04 b4 0c 5b 	5b0cb404     sbc.n      r24,r25,gp
+  8c:	04 3a 6e 5b 	5b6e3a04     sbc.n      fp,sp,ilink1
+  90:	05 c0 cf 5b 	5bcfc005     sbc.c      ilink2,blink,r32
+  94:	05 46 31 5c 	5c314605     sbc.c      r33,r34,r35
+  98:	05 cc 92 5c 	5c92cc05     sbc.c      r36,r37,r38
+  9c:	06 52 f4 5c 	5cf45206     sbc.nc     r39,r40,r41
+  a0:	06 d8 55 5d 	5d55d806     sbc.nc     r42,r43,r44
+  a4:	06 5e b7 5d 	5db75e06     sbc.nc     r45,r46,r47
+  a8:	07 e4 18 5e 	5e18e407     sbc.v      r48,r49,r50
+  ac:	07 6a 1a 5f 	5f1a6a07     sbc.v      r56,r52,r53
+  b0:	08 f0 1b 5f 	5f1bf008     sbc.nv     r56,r55,r56
+  b4:	08 76 1d 5f 	5f1d7608     sbc.nv     r56,r58,r59
+  b8:	09 00 9e 5f 	5f9e0009     sbc.gt     lp_count,lp_count,r0
+  bc:	0a 7c 00 58 	58007c0a     sbc.ge     r0,r0,0
+  c0:	00 00 00 00 
+  c4:	0b 02 3f 58 	583f020b     sbc.lt     r1,1,r1
+  c8:	01 00 00 00 
+  cc:	0d 06 7f 58 	587f060d     sbc.hi     r3,3,r3
+  d0:	03 00 00 00 
+  d4:	0e 08 df 5f 	5fdf080e     sbc.ls     0,4,r4
+  d8:	04 00 00 00 
+  dc:	0f fc c2 5f 	5fc2fc0f     sbc.pnz    0,r5,5
+  e0:	05 00 00 00 
+  e4:	00 85 00 58 	58008500     sbc.f      r0,r1,r2
+  e8:	01 fa 00 58 	5800fa01     sbc.f      r0,r1,1
+  ec:	01 84 1e 58 	581e8401     sbc.f      r0,1,r2
+  f0:	00 85 e0 5f 	5fe08500     sbc.f      0,r1,r2
+  f4:	00 fd 00 58 	5800fd00     sbc.f      r0,r1,0x200
+  f8:	00 02 00 00 
+  fc:	00 05 1f 58 	581f0500     sbc.f      r0,0x200,r2
+ 100:	00 02 00 00 
+ 104:	01 85 00 58 	58008501     sbc.z.f    r0,r1,r2
+ 108:	02 fd 00 58 	5800fd02     sbc.nz.f   r0,r1,0
+ 10c:	00 00 00 00 
+ 110:	0b 05 1f 58 	581f050b     sbc.lt.f   r0,0,r2
+ 114:	00 00 00 00 
+ 118:	09 85 c0 5f 	5fc08509     sbc.gt.f   0,r1,r2
+ 11c:	00 00 00 00 	00000000                
+ 120:	0c fd 00 58 	5800fd0c     sbc.le.f   r0,r1,0x200
+ 124:	00 02 00 00 
+ 128:	0a 05 1f 58 	581f050a     sbc.ge.f   r0,0x200,r2
+ 12c:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/sbc.s b/gas/testsuite/gas/arc/sbc.s
new file mode 100644
index 0000000..8eb9646
--- /dev/null
+++ b/gas/testsuite/gas/arc/sbc.s
@@ -0,0 +1,68 @@
+# sbc test
+
+	sbc r0,r1,r2
+	sbc r26,fp,sp
+	sbc ilink1,ilink2,blink
+	sbc r56,r59,lp_count
+
+	sbc r0,r1,0
+	sbc r0,0,r2
+	sbc 0,r1,r2
+	sbc r0,r1,-1
+	sbc r0,-1,r2
+	sbc -1,r1,r2
+	sbc r0,r1,255
+	sbc r0,255,r2
+	sbc 255,r1,r2
+	sbc r0,r1,-256
+	sbc r0,-256,r2
+	sbc -256,r1,r2
+
+	sbc r0,r1,256
+	sbc r0,-257,r2
+
+	sbc r0,255,256
+	sbc r0,256,255
+
+	sbc r0,r1,foo
+
+	sbc.al r0,r1,r2
+	sbc.ra r3,r4,r5
+	sbc.eq r6,r7,r8
+	sbc.z r9,r10,r11
+	sbc.ne r12,r13,r14
+	sbc.nz r15,r16,r17
+	sbc.pl r18,r19,r20
+	sbc.p r21,r22,r23
+	sbc.mi r24,r25,r26
+	sbc.n r27,r28,r29
+	sbc.cs r30,r31,r32
+	sbc.c r33,r34,r35
+	sbc.lo r36,r37,r38
+	sbc.cc r39,r40,r41
+	sbc.nc r42,r43,r44
+	sbc.hs r45,r46,r47
+	sbc.vs r48,r49,r50
+	sbc.v r56,r52,r53
+	sbc.vc r56,r55,r56
+	sbc.nv r56,r58,r59
+	sbc.gt r60,r60,r0
+	sbc.ge r0,r0,0
+	sbc.lt r1,1,r1
+	sbc.hi r3,3,r3
+	sbc.ls 4,4,r4
+	sbc.pnz 5,r5,5
+
+	sbc.f r0,r1,r2
+	sbc.f r0,r1,1
+	sbc.f r0,1,r2
+	sbc.f 0,r1,r2
+	sbc.f r0,r1,512
+	sbc.f r0,512,r2
+
+	sbc.eq.f r0,r1,r2
+	sbc.ne.f r0,r1,0
+	sbc.lt.f r0,0,r2
+	sbc.gt.f 0,r1,r2
+	sbc.le.f r0,r1,512
+	sbc.ge.f r0,512,r2
diff --git a/gas/testsuite/gas/arc/sexb.d b/gas/testsuite/gas/arc/sexb.d
new file mode 100644
index 0000000..96d35d6
--- /dev/null
+++ b/gas/testsuite/gas/arc/sexb.d
@@ -0,0 +1,51 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 8a 00 18 	18008a00     sexb       r0,r1
+   4:	00 0a 6e 1b 	1b6e0a00     sexb       fp,sp
+   8:	00 8a 1f 18 	181f8a00     sexb       r0,0
+   c:	ff 8b 3f 18 	183f8bff     sexb       r1,-1
+  10:	00 0a e1 1f 	1fe10a00     sexb       0,r2
+  14:	00 8a e1 1f 	1fe18a00     sexb       0,r3
+  18:	ff 8a 9f 18 	189f8aff     sexb       r4,255
+  1c:	00 8a e2 1f 	1fe28a00     sexb       0,r5
+  20:	00 8b df 18 	18df8b00     sexb       r6,-256
+  24:	00 8a e3 1f 	1fe38a00     sexb       0,r7
+  28:	00 0a 1f 19 	191f0a00     sexb       r8,0x100
+  2c:	00 01 00 00 
+  30:	00 0a 3f 19 	193f0a00     sexb       r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 0a 7f 19 	197f0a00     sexb       r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 0a ff 1f 	1fff0a00     sexb       0,0x100
+  44:	00 01 00 00 
+  48:	00 0a 1f 18 	181f0a00     sexb       r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	01 8a 45 19 	19458a01     sexb.z     r10,r11
+  54:	02 8a 86 19 	19868a02     sexb.nz    r12,r13
+  58:	0b 0a df 19 	19df0a0b     sexb.lt    r14,0
+  5c:	00 00 00 00 
+  60:	09 0a ff 19 	19ff0a09     sexb.gt    r15,0x200
+  64:	00 02 00 00 
+  68:	00 8b 00 18 	18008b00     sexb.f     r0,r1
+  6c:	01 8a 5e 18 	185e8a01     sexb.f     r2,1
+  70:	00 0b e2 1f 	1fe20b00     sexb.f     0,r4
+  74:	00 0b bf 18 	18bf0b00     sexb.f     r5,0x200
+  78:	00 02 00 00 
+  7c:	00 0b df 1f 	1fdf0b00     sexb.f     0,0x200
+  80:	00 02 00 00 
+  84:	01 8b 00 18 	18008b01     sexb.z.f   r0,r1
+  88:	02 0b 3f 18 	183f0b02     sexb.nz.f  r1,0
+  8c:	00 00 00 00 
+  90:	0b 0b c1 1f 	1fc10b0b     sexb.lt.f  0,r2
+  94:	00 00 00 00 	00000000                
+  98:	0c 0b 1f 18 	181f0b0c     sexb.le.f  r0,0x200
+  9c:	00 02 00 00 
+  a0:	04 0b df 1f 	1fdf0b04     sexb.n.f   0,0x200
+  a4:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/sexb.s b/gas/testsuite/gas/arc/sexb.s
new file mode 100644
index 0000000..a2afc3b
--- /dev/null
+++ b/gas/testsuite/gas/arc/sexb.s
@@ -0,0 +1,38 @@
+# sexb test
+
+	sexb r0,r1
+	sexb fp,sp
+
+	sexb r0,0
+	sexb r1,-1
+	sexb 0,r2
+	sexb -1,r3
+	sexb r4,255
+	sexb 255,r5
+	sexb r6,-256
+	sexb -256,r7
+
+	sexb r8,256
+	sexb r9,-257
+	sexb r11,0x42424242
+
+	sexb 255,256
+
+	sexb r0,foo
+
+	sexb.eq r10,r11
+	sexb.ne r12,r13
+	sexb.lt r14,0
+	sexb.gt r15,512
+
+	sexb.f r0,r1
+	sexb.f r2,1
+	sexb.f 0,r4
+	sexb.f r5,512
+	sexb.f 512,512
+
+	sexb.eq.f r0,r1
+	sexb.ne.f r1,0
+	sexb.lt.f 0,r2
+	sexb.le.f r0,512
+	sexb.n.f 512,512
diff --git a/gas/testsuite/gas/arc/sexw.d b/gas/testsuite/gas/arc/sexw.d
new file mode 100644
index 0000000..7b6a612
--- /dev/null
+++ b/gas/testsuite/gas/arc/sexw.d
@@ -0,0 +1,51 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 8c 00 18 	18008c00     sexw       r0,r1
+   4:	00 0c 6e 1b 	1b6e0c00     sexw       fp,sp
+   8:	00 8c 1f 18 	181f8c00     sexw       r0,0
+   c:	ff 8d 3f 18 	183f8dff     sexw       r1,-1
+  10:	00 0c e1 1f 	1fe10c00     sexw       0,r2
+  14:	00 8c e1 1f 	1fe18c00     sexw       0,r3
+  18:	ff 8c 9f 18 	189f8cff     sexw       r4,255
+  1c:	00 8c e2 1f 	1fe28c00     sexw       0,r5
+  20:	00 8d df 18 	18df8d00     sexw       r6,-256
+  24:	00 8c e3 1f 	1fe38c00     sexw       0,r7
+  28:	00 0c 1f 19 	191f0c00     sexw       r8,0x100
+  2c:	00 01 00 00 
+  30:	00 0c 3f 19 	193f0c00     sexw       r9,0xffff_feff
+  34:	ff fe ff ff 
+  38:	00 0c 7f 19 	197f0c00     sexw       r11,0x4242_4242
+  3c:	42 42 42 42 
+  40:	00 0c ff 1f 	1fff0c00     sexw       0,0x100
+  44:	00 01 00 00 
+  48:	00 0c 1f 18 	181f0c00     sexw       r0,0
+  4c:	00 00 00 00 
+			4c: R_ARC_32	foo
+  50:	01 8c 45 19 	19458c01     sexw.z     r10,r11
+  54:	02 8c 86 19 	19868c02     sexw.nz    r12,r13
+  58:	0b 0c df 19 	19df0c0b     sexw.lt    r14,0
+  5c:	00 00 00 00 
+  60:	09 0c ff 19 	19ff0c09     sexw.gt    r15,0x200
+  64:	00 02 00 00 
+  68:	00 8d 00 18 	18008d00     sexw.f     r0,r1
+  6c:	01 8c 5e 18 	185e8c01     sexw.f     r2,1
+  70:	00 0d e2 1f 	1fe20d00     sexw.f     0,r4
+  74:	00 0d bf 18 	18bf0d00     sexw.f     r5,0x200
+  78:	00 02 00 00 
+  7c:	00 0d df 1f 	1fdf0d00     sexw.f     0,0x200
+  80:	00 02 00 00 
+  84:	01 8d 00 18 	18008d01     sexw.z.f   r0,r1
+  88:	02 0d 3f 18 	183f0d02     sexw.nz.f  r1,0
+  8c:	00 00 00 00 
+  90:	0b 0d c1 1f 	1fc10d0b     sexw.lt.f  0,r2
+  94:	00 00 00 00 	00000000                
+  98:	0c 0d 1f 18 	181f0d0c     sexw.le.f  r0,0x200
+  9c:	00 02 00 00 
+  a0:	04 0d df 1f 	1fdf0d04     sexw.n.f   0,0x200
+  a4:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/sexw.s b/gas/testsuite/gas/arc/sexw.s
new file mode 100644
index 0000000..6d05dab
--- /dev/null
+++ b/gas/testsuite/gas/arc/sexw.s
@@ -0,0 +1,38 @@
+# sexw test
+
+	sexw r0,r1
+	sexw fp,sp
+
+	sexw r0,0
+	sexw r1,-1
+	sexw 0,r2
+	sexw -1,r3
+	sexw r4,255
+	sexw 255,r5
+	sexw r6,-256
+	sexw -256,r7
+
+	sexw r8,256
+	sexw r9,-257
+	sexw r11,0x42424242
+
+	sexw 255,256
+
+	sexw r0,foo
+
+	sexw.eq r10,r11
+	sexw.ne r12,r13
+	sexw.lt r14,0
+	sexw.gt r15,512
+
+	sexw.f r0,r1
+	sexw.f r2,1
+	sexw.f 0,r4
+	sexw.f r5,512
+	sexw.f 512,512
+
+	sexw.eq.f r0,r1
+	sexw.ne.f r1,0
+	sexw.lt.f 0,r2
+	sexw.le.f r0,512
+	sexw.n.f 512,512
diff --git a/gas/testsuite/gas/arc/sleep.d b/gas/testsuite/gas/arc/sleep.d
new file mode 100644
index 0000000..b6262f6
--- /dev/null
+++ b/gas/testsuite/gas/arc/sleep.d
@@ -0,0 +1,11 @@
+#as: -EL -marc7
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 84 00 40 	40008400     add        r0,r1,r2
+   4:	01 fe ff 1f 	1ffffe01     sleep      
+   8:	00 0a 62 50 	50620a00     sub        r3,r4,r5
diff --git a/gas/testsuite/gas/arc/sleep.s b/gas/testsuite/gas/arc/sleep.s
new file mode 100644
index 0000000..c5797fe
--- /dev/null
+++ b/gas/testsuite/gas/arc/sleep.s
@@ -0,0 +1,6 @@
+# sleep test
+
+main:
+	add	r0,r1,r2
+	sleep
+	sub	r3,r4,r5
diff --git a/gas/testsuite/gas/arc/st.d b/gas/testsuite/gas/arc/st.d
index cca99a8..0ed6b80 100644
--- a/gas/testsuite/gas/arc/st.d
+++ b/gas/testsuite/gas/arc/st.d
@@ -1,25 +1,27 @@
-#objdump: -dr
-#name: st/sr
-
-# Test the st/sr insn.
+#as: -EL
+#objdump: -dr -EL
 
 .*: +file format elf32-.*arc
 
 Disassembly of section .text:
-00000000 10008000	st r0,\[r1\]
-00000004 10030a01	st r5,\[r6,1\]
-00000008 10040fff	st r7,\[r8,-1\]
-0000000c 100512ff	st r9,\[r10,255\]
-00000010 10061700	st r11,\[r12,-256\]
-00000014 101f2600	st r19,\[0\]
-		RELOC: 00000018 R_ARC_32 foo
-0000001c 101f2800	st r20,\[4\]
-		RELOC: 00000020 R_ARC_32 foo
-00000024 105f0000	stb r0,\[0\]
-0000002c 109f0000	stw r0,\[0\]
-00000034 111f0000	st.a r0,\[0\]
-0000003c 141f0000	st.di r0,\[0\]
-00000044 15400000	stb.a.di r0,\[r0\]
-00000048 12008000	sr r0,\[r1\]
-0000004c 121f8400	sr r2,\[status\]
-00000050 121f0600	sr r3,\[305419896\]
+
+00000000 <.text>:
+   0:	00 02 01 10 	10010200     st         r1,\[r2\]
+   4:	0e 02 01 10 	1001020e     st         r1,\[r2,14\]
+   8:	00 02 41 10 	10410200     stb        r1,\[r2\]
+   c:	0e 82 01 11 	1101820e     st.a       r1,\[r3,14\]
+  10:	02 02 81 11 	11810202     stw.a      r1,\[r2,2\]
+  14:	00 02 1f 10 	101f0200     st         r1,\[0x384\]
+  18:	84 03 00 00 
+  1c:	00 7e 41 10 	10417e00     stb        0,\[r2\]
+  20:	f8 7f 01 10 	10017ff8     st         -8,\[r2,-8\]
+  24:	50 7e 1f 10 	101f7e50     st         80,\[0x2ee\]
+  28:	9e 02 00 00 
+  2c:	00 04 1f 10 	101f0400     st         r2,\[0\]
+  30:	00 00 00 00 
+			30: R_ARC_32	foo
+  34:	02 02 01 14 	14010202     st.di      r1,\[r2,2\]
+  38:	03 02 01 15 	15010203     st.a.di    r1,\[r2,3\]
+  3c:	04 02 81 15 	15810204     stw.a.di   r1,\[r2,4\]
+  40:	00 02 01 12 	12010200     sr         r1,\[r2\]
+  44:	0e 82 1f 12 	121f820e     sr         r1,\[0xe\]
diff --git a/gas/testsuite/gas/arc/st.s b/gas/testsuite/gas/arc/st.s
index 10af198..2754d27 100644
--- a/gas/testsuite/gas/arc/st.s
+++ b/gas/testsuite/gas/arc/st.s
@@ -1,19 +1,18 @@
-# st/sr test
-	
-	st	r0,[r1]
-	st	r5,[r6,1]
-	st	r7,[r8,-1]
-	st	r9,[r10,255]
-	st	r11,[r12,-256]
-	st	r19,[foo]
-	st	r20,[foo+4]
-
-	stb	r0,[0]
-	stw	r0,[0]
-	st.a	r0,[0]
-	st.di	r0,[0]
-	stb.a.di r0,[r0]
+# st test
 
-	sr	r0,[r1]
-	sr	r2,[status]
-	sr	r3,[0x12345678]
+	st	r1,[r2]
+	st	r1,[r2,14]
+	stb	r1,[r2]
+	st.a	r1,[r3,14]
+	stw.a	r1,[r2,2]
+	st	r1,[900]
+	stb	0,[r2]
+	st	-8,[r2,-8]
+	st	80,[750]
+	st	r2,[foo]
+	st.di	r1,[r2,2]
+	st.a.di	r1,[r2,3]
+	stw.a.di r1,[r2,4]
+	
+	sr	r1,[r2]
+	sr	r1,[14]
diff --git a/gas/testsuite/gas/arc/sub.d b/gas/testsuite/gas/arc/sub.d
new file mode 100644
index 0000000..e1c333d0
--- /dev/null
+++ b/gas/testsuite/gas/arc/sub.d
@@ -0,0 +1,85 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 84 00 50 	50008400     sub        r0,r1,r2
+   4:	00 b8 4d 53 	534db800     sub        gp,fp,sp
+   8:	00 3e af 53 	53af3e00     sub        ilink1,ilink2,blink
+   c:	00 f8 1d 57 	571df800     sub        r56,r59,lp_count
+  10:	00 fe 00 50 	5000fe00     sub        r0,r1,0
+  14:	00 84 1f 50 	501f8400     sub        r0,0,r2
+  18:	00 84 e0 57 	57e08400     sub        0,r1,r2
+  1c:	ff ff 00 50 	5000ffff     sub        r0,r1,-1
+  20:	ff 85 1f 50 	501f85ff     sub        r0,-1,r2
+  24:	00 84 e0 57 	57e08400     sub        0,r1,r2
+  28:	ff fe 00 50 	5000feff     sub        r0,r1,255
+  2c:	ff 84 1f 50 	501f84ff     sub        r0,255,r2
+  30:	00 84 e0 57 	57e08400     sub        0,r1,r2
+  34:	00 ff 00 50 	5000ff00     sub        r0,r1,-256
+  38:	00 85 1f 50 	501f8500     sub        r0,-256,r2
+  3c:	00 84 e0 57 	57e08400     sub        0,r1,r2
+  40:	00 fc 00 50 	5000fc00     sub        r0,r1,0x100
+  44:	00 01 00 00 
+  48:	00 04 1f 50 	501f0400     sub        r0,0xffff_feff,r2
+  4c:	ff fe ff ff 
+  50:	ff fc 1f 50 	501ffcff     sub        r0,255,0x100
+  54:	00 01 00 00 
+  58:	ff 7e 1f 50 	501f7eff     sub        r0,0x100,255
+  5c:	00 01 00 00 
+  60:	00 fc 00 50 	5000fc00     sub        r0,r1,0
+  64:	00 00 00 00 
+			64: R_ARC_32	foo
+  68:	00 84 00 50 	50008400     sub        r0,r1,r2
+  6c:	00 0a 62 50 	50620a00     sub        r3,r4,r5
+  70:	01 90 c3 50 	50c39001     sub.z      r6,r7,r8
+  74:	01 16 25 51 	51251601     sub.z      r9,r10,r11
+  78:	02 9c 86 51 	51869c02     sub.nz     r12,r13,r14
+  7c:	02 22 e8 51 	51e82202     sub.nz     r15,r16,r17
+  80:	03 a8 49 52 	5249a803     sub.p      r18,r19,r20
+  84:	03 2e ab 52 	52ab2e03     sub.p      r21,r22,r23
+  88:	04 b4 0c 53 	530cb404     sub.n      r24,r25,gp
+  8c:	04 3a 6e 53 	536e3a04     sub.n      fp,sp,ilink1
+  90:	05 c0 cf 53 	53cfc005     sub.c      ilink2,blink,r32
+  94:	05 46 31 54 	54314605     sub.c      r33,r34,r35
+  98:	05 cc 92 54 	5492cc05     sub.c      r36,r37,r38
+  9c:	06 52 f4 54 	54f45206     sub.nc     r39,r40,r41
+  a0:	06 d8 55 55 	5555d806     sub.nc     r42,r43,r44
+  a4:	06 5e b7 55 	55b75e06     sub.nc     r45,r46,r47
+  a8:	07 e4 18 56 	5618e407     sub.v      r48,r49,r50
+  ac:	07 6a 1a 57 	571a6a07     sub.v      r56,r52,r53
+  b0:	08 f0 1b 57 	571bf008     sub.nv     r56,r55,r56
+  b4:	08 76 1d 57 	571d7608     sub.nv     r56,r58,r59
+  b8:	09 00 9e 57 	579e0009     sub.gt     lp_count,lp_count,r0
+  bc:	0a 7c 00 50 	50007c0a     sub.ge     r0,r0,0
+  c0:	00 00 00 00 
+  c4:	0b 02 3f 50 	503f020b     sub.lt     r1,1,r1
+  c8:	01 00 00 00 
+  cc:	0d 06 7f 50 	507f060d     sub.hi     r3,3,r3
+  d0:	03 00 00 00 
+  d4:	0e 08 df 57 	57df080e     sub.ls     0,4,r4
+  d8:	04 00 00 00 
+  dc:	0f fc c2 57 	57c2fc0f     sub.pnz    0,r5,5
+  e0:	05 00 00 00 
+  e4:	00 85 00 50 	50008500     sub.f      r0,r1,r2
+  e8:	01 fa 00 50 	5000fa01     sub.f      r0,r1,1
+  ec:	01 84 1e 50 	501e8401     sub.f      r0,1,r2
+  f0:	00 85 e0 57 	57e08500     sub.f      0,r1,r2
+  f4:	00 fd 00 50 	5000fd00     sub.f      r0,r1,0x200
+  f8:	00 02 00 00 
+  fc:	00 05 1f 50 	501f0500     sub.f      r0,0x200,r2
+ 100:	00 02 00 00 
+ 104:	01 85 00 50 	50008501     sub.z.f    r0,r1,r2
+ 108:	02 fd 00 50 	5000fd02     sub.nz.f   r0,r1,0
+ 10c:	00 00 00 00 
+ 110:	0b 05 1f 50 	501f050b     sub.lt.f   r0,0,r2
+ 114:	00 00 00 00 
+ 118:	09 85 c0 57 	57c08509     sub.gt.f   0,r1,r2
+ 11c:	00 00 00 00 	00000000                
+ 120:	0c fd 00 50 	5000fd0c     sub.le.f   r0,r1,0x200
+ 124:	00 02 00 00 
+ 128:	0a 05 1f 50 	501f050a     sub.ge.f   r0,0x200,r2
+ 12c:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/sub.s b/gas/testsuite/gas/arc/sub.s
new file mode 100644
index 0000000..6dd5009
--- /dev/null
+++ b/gas/testsuite/gas/arc/sub.s
@@ -0,0 +1,68 @@
+# sub test
+
+	sub r0,r1,r2
+	sub r26,fp,sp
+	sub ilink1,ilink2,blink
+	sub r56,r59,lp_count
+
+	sub r0,r1,0
+	sub r0,0,r2
+	sub 0,r1,r2
+	sub r0,r1,-1
+	sub r0,-1,r2
+	sub -1,r1,r2
+	sub r0,r1,255
+	sub r0,255,r2
+	sub 255,r1,r2
+	sub r0,r1,-256
+	sub r0,-256,r2
+	sub -256,r1,r2
+
+	sub r0,r1,256
+	sub r0,-257,r2
+
+	sub r0,255,256
+	sub r0,256,255
+
+	sub r0,r1,foo
+
+	sub.al r0,r1,r2
+	sub.ra r3,r4,r5
+	sub.eq r6,r7,r8
+	sub.z r9,r10,r11
+	sub.ne r12,r13,r14
+	sub.nz r15,r16,r17
+	sub.pl r18,r19,r20
+	sub.p r21,r22,r23
+	sub.mi r24,r25,r26
+	sub.n r27,r28,r29
+	sub.cs r30,r31,r32
+	sub.c r33,r34,r35
+	sub.lo r36,r37,r38
+	sub.cc r39,r40,r41
+	sub.nc r42,r43,r44
+	sub.hs r45,r46,r47
+	sub.vs r48,r49,r50
+	sub.v r56,r52,r53
+	sub.vc r56,r55,r56
+	sub.nv r56,r58,r59
+	sub.gt r60,r60,r0
+	sub.ge r0,r0,0
+	sub.lt r1,1,r1
+	sub.hi r3,3,r3
+	sub.ls 4,4,r4
+	sub.pnz 5,r5,5
+
+	sub.f r0,r1,r2
+	sub.f r0,r1,1
+	sub.f r0,1,r2
+	sub.f 0,r1,r2
+	sub.f r0,r1,512
+	sub.f r0,512,r2
+
+	sub.eq.f r0,r1,r2
+	sub.ne.f r0,r1,0
+	sub.lt.f r0,0,r2
+	sub.gt.f 0,r1,r2
+	sub.le.f r0,r1,512
+	sub.ge.f r0,512,r2
diff --git a/gas/testsuite/gas/arc/swi.d b/gas/testsuite/gas/arc/swi.d
new file mode 100644
index 0000000..58654ec
--- /dev/null
+++ b/gas/testsuite/gas/arc/swi.d
@@ -0,0 +1,11 @@
+#as: -EL -marc8
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 84 00 40 	40008400     add        r0,r1,r2
+   4:	02 fe ff 1f 	1ffffe02     swi        
+   8:	00 0a 62 50 	50620a00     sub        r3,r4,r5
diff --git a/gas/testsuite/gas/arc/swi.s b/gas/testsuite/gas/arc/swi.s
new file mode 100644
index 0000000..ce0d7fe
--- /dev/null
+++ b/gas/testsuite/gas/arc/swi.s
@@ -0,0 +1,6 @@
+# swi test
+
+main:
+	add	r0,r1,r2
+	swi
+	sub	r3,r4,r5
diff --git a/gas/testsuite/gas/arc/warn.exp b/gas/testsuite/gas/arc/warn.exp
index 79ff126..e544ea5 100644
--- a/gas/testsuite/gas/arc/warn.exp
+++ b/gas/testsuite/gas/arc/warn.exp
@@ -1,13 +1,8 @@
 # Test assembler warnings.
 
 if [istarget arc*-*-*] {
-
     load_lib gas-dg.exp
-
     dg-init
-
     dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/warn*.s]] "" ""
-
     dg-finish
-
 }
diff --git a/gas/testsuite/gas/arc/warn.s b/gas/testsuite/gas/arc/warn.s
index 6fcb437..060a74e 100644
--- a/gas/testsuite/gas/arc/warn.s
+++ b/gas/testsuite/gas/arc/warn.s
@@ -3,12 +3,9 @@
 ; { dg-do assemble { target arc-*-* } }
 
 	b.d foo
-	mov r0,256	; { dg-warning "8 byte instruction in delay slot" "8 byte insn in delay slot" }
+	mov r0,256	; { dg-warning "8 byte instruction in delay slot" "8 byte instruction in delay slot" }
 
-	j.d foo		; { dg-warning "8 byte jump instruction with delay slot" "8 byte jump with delay slot" }
+	j.d foo		; { dg-warning "8 byte jump instruction with delay slot" "8 byte jump instruction with delay slot" }
 	mov r0,r1
 
-	sub.f 0,r0,r2
-	beq foo		; { dg-warning "conditional branch follows set of flags" "cc set/branch nop test" }
-
 foo:
diff --git a/gas/testsuite/gas/arc/xor.d b/gas/testsuite/gas/arc/xor.d
new file mode 100644
index 0000000..46fdedd
--- /dev/null
+++ b/gas/testsuite/gas/arc/xor.d
@@ -0,0 +1,85 @@
+#as: -EL
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 84 00 78 	78008400     xor        r0,r1,r2
+   4:	00 b8 4d 7b 	7b4db800     xor        gp,fp,sp
+   8:	00 3e af 7b 	7baf3e00     xor        ilink1,ilink2,blink
+   c:	00 f8 1d 7f 	7f1df800     xor        r56,r59,lp_count
+  10:	00 fe 00 78 	7800fe00     xor        r0,r1,0
+  14:	00 84 1f 78 	781f8400     xor        r0,0,r2
+  18:	00 84 e0 7f 	7fe08400     xor        0,r1,r2
+  1c:	ff ff 00 78 	7800ffff     xor        r0,r1,-1
+  20:	ff 85 1f 78 	781f85ff     xor        r0,-1,r2
+  24:	00 84 e0 7f 	7fe08400     xor        0,r1,r2
+  28:	ff fe 00 78 	7800feff     xor        r0,r1,255
+  2c:	ff 84 1f 78 	781f84ff     xor        r0,255,r2
+  30:	00 84 e0 7f 	7fe08400     xor        0,r1,r2
+  34:	00 ff 00 78 	7800ff00     xor        r0,r1,-256
+  38:	00 85 1f 78 	781f8500     xor        r0,-256,r2
+  3c:	00 84 e0 7f 	7fe08400     xor        0,r1,r2
+  40:	00 fc 00 78 	7800fc00     xor        r0,r1,0x100
+  44:	00 01 00 00 
+  48:	00 04 1f 78 	781f0400     xor        r0,0xffff_feff,r2
+  4c:	ff fe ff ff 
+  50:	ff fc 1f 78 	781ffcff     xor        r0,255,0x100
+  54:	00 01 00 00 
+  58:	ff 7e 1f 78 	781f7eff     xor        r0,0x100,255
+  5c:	00 01 00 00 
+  60:	00 fc 00 78 	7800fc00     xor        r0,r1,0
+  64:	00 00 00 00 
+			64: R_ARC_32	foo
+  68:	00 84 00 78 	78008400     xor        r0,r1,r2
+  6c:	00 0a 62 78 	78620a00     xor        r3,r4,r5
+  70:	01 90 c3 78 	78c39001     xor.z      r6,r7,r8
+  74:	01 16 25 79 	79251601     xor.z      r9,r10,r11
+  78:	02 9c 86 79 	79869c02     xor.nz     r12,r13,r14
+  7c:	02 22 e8 79 	79e82202     xor.nz     r15,r16,r17
+  80:	03 a8 49 7a 	7a49a803     xor.p      r18,r19,r20
+  84:	03 2e ab 7a 	7aab2e03     xor.p      r21,r22,r23
+  88:	04 b4 0c 7b 	7b0cb404     xor.n      r24,r25,gp
+  8c:	04 3a 6e 7b 	7b6e3a04     xor.n      fp,sp,ilink1
+  90:	05 c0 cf 7b 	7bcfc005     xor.c      ilink2,blink,r32
+  94:	05 46 31 7c 	7c314605     xor.c      r33,r34,r35
+  98:	05 cc 92 7c 	7c92cc05     xor.c      r36,r37,r38
+  9c:	06 52 f4 7c 	7cf45206     xor.nc     r39,r40,r41
+  a0:	06 d8 55 7d 	7d55d806     xor.nc     r42,r43,r44
+  a4:	06 5e b7 7d 	7db75e06     xor.nc     r45,r46,r47
+  a8:	07 e4 18 7e 	7e18e407     xor.v      r48,r49,r50
+  ac:	07 6a 1a 7f 	7f1a6a07     xor.v      r56,r52,r53
+  b0:	08 f0 1b 7f 	7f1bf008     xor.nv     r56,r55,r56
+  b4:	08 76 1d 7f 	7f1d7608     xor.nv     r56,r58,r59
+  b8:	09 00 9e 7f 	7f9e0009     xor.gt     lp_count,lp_count,r0
+  bc:	0a 7c 00 78 	78007c0a     xor.ge     r0,r0,0
+  c0:	00 00 00 00 
+  c4:	0b 02 3f 78 	783f020b     xor.lt     r1,1,r1
+  c8:	01 00 00 00 
+  cc:	0d 06 7f 78 	787f060d     xor.hi     r3,3,r3
+  d0:	03 00 00 00 
+  d4:	0e 08 df 7f 	7fdf080e     xor.ls     0,4,r4
+  d8:	04 00 00 00 
+  dc:	0f fc c2 7f 	7fc2fc0f     xor.pnz    0,r5,5
+  e0:	05 00 00 00 
+  e4:	00 85 00 78 	78008500     xor.f      r0,r1,r2
+  e8:	01 fa 00 78 	7800fa01     xor.f      r0,r1,1
+  ec:	01 84 1e 78 	781e8401     xor.f      r0,1,r2
+  f0:	00 85 e0 7f 	7fe08500     xor.f      0,r1,r2
+  f4:	00 fd 00 78 	7800fd00     xor.f      r0,r1,0x200
+  f8:	00 02 00 00 
+  fc:	00 05 1f 78 	781f0500     xor.f      r0,0x200,r2
+ 100:	00 02 00 00 
+ 104:	01 85 00 78 	78008501     xor.z.f    r0,r1,r2
+ 108:	02 fd 00 78 	7800fd02     xor.nz.f   r0,r1,0
+ 10c:	00 00 00 00 
+ 110:	0b 05 1f 78 	781f050b     xor.lt.f   r0,0,r2
+ 114:	00 00 00 00 
+ 118:	09 85 c0 7f 	7fc08509     xor.gt.f   0,r1,r2
+ 11c:	00 00 00 00 	00000000                
+ 120:	0c fd 00 78 	7800fd0c     xor.le.f   r0,r1,0x200
+ 124:	00 02 00 00 
+ 128:	0a 05 1f 78 	781f050a     xor.ge.f   r0,0x200,r2
+ 12c:	00 02 00 00 
diff --git a/gas/testsuite/gas/arc/xor.s b/gas/testsuite/gas/arc/xor.s
new file mode 100644
index 0000000..090107a
--- /dev/null
+++ b/gas/testsuite/gas/arc/xor.s
@@ -0,0 +1,68 @@
+# xor test
+
+	xor r0,r1,r2
+	xor r26,fp,sp
+	xor ilink1,ilink2,blink
+	xor r56,r59,lp_count
+
+	xor r0,r1,0
+	xor r0,0,r2
+	xor 0,r1,r2
+	xor r0,r1,-1
+	xor r0,-1,r2
+	xor -1,r1,r2
+	xor r0,r1,255
+	xor r0,255,r2
+	xor 255,r1,r2
+	xor r0,r1,-256
+	xor r0,-256,r2
+	xor -256,r1,r2
+
+	xor r0,r1,256
+	xor r0,-257,r2
+
+	xor r0,255,256
+	xor r0,256,255
+
+	xor r0,r1,foo
+
+	xor.al r0,r1,r2
+	xor.ra r3,r4,r5
+	xor.eq r6,r7,r8
+	xor.z r9,r10,r11
+	xor.ne r12,r13,r14
+	xor.nz r15,r16,r17
+	xor.pl r18,r19,r20
+	xor.p r21,r22,r23
+	xor.mi r24,r25,r26
+	xor.n r27,r28,r29
+	xor.cs r30,r31,r32
+	xor.c r33,r34,r35
+	xor.lo r36,r37,r38
+	xor.cc r39,r40,r41
+	xor.nc r42,r43,r44
+	xor.hs r45,r46,r47
+	xor.vs r48,r49,r50
+	xor.v r56,r52,r53
+	xor.vc r56,r55,r56
+	xor.nv r56,r58,r59
+	xor.gt r60,r60,r0
+	xor.ge r0,r0,0
+	xor.lt r1,1,r1
+	xor.hi r3,3,r3
+	xor.ls 4,4,r4
+	xor.pnz 5,r5,5
+
+	xor.f r0,r1,r2
+	xor.f r0,r1,1
+	xor.f r0,1,r2
+	xor.f 0,r1,r2
+	xor.f r0,r1,512
+	xor.f r0,512,r2
+
+	xor.eq.f r0,r1,r2
+	xor.ne.f r0,r1,0
+	xor.lt.f r0,0,r2
+	xor.gt.f 0,r1,r2
+	xor.le.f r0,r1,512
+	xor.ge.f r0,512,r2
diff --git a/gas/testsuite/gas/ieee-fp/x930509a.exp b/gas/testsuite/gas/ieee-fp/x930509a.exp
index 88a2e13..4218c87 100644
--- a/gas/testsuite/gas/ieee-fp/x930509a.exp
+++ b/gas/testsuite/gas/ieee-fp/x930509a.exp
@@ -23,6 +23,6 @@ proc dotest {} {
 # float encoding is tested in c54x-specific tests.
 # No floating point support in assembly code for CRIS.
 if { ![istarget vax*-*-*] && ![istarget *c54x*-*-*]
-     && ![istarget cris-*-*] } then {
+     && ![istarget cris-*-*] && ![istarget arc*-*-*] } then {
     dotest
 }
diff --git a/gas/testsuite/gas/vtable/vtable.exp b/gas/testsuite/gas/vtable/vtable.exp
index 80a533c..f2235de 100644
--- a/gas/testsuite/gas/vtable/vtable.exp
+++ b/gas/testsuite/gas/vtable/vtable.exp
@@ -29,6 +29,11 @@ if { (   [istarget "*-*-elf*"] || [istarget "*-*-linux*"])
         return
     }
 
+    # not yet supported by ARC
+    if {[istarget "arc*-*-*"]} {
+      return
+    }
+
     run_dump_test "inherit0" 
     run_list_test "inherit1" "-al"
 
diff --git a/include/ChangeLog b/include/ChangeLog
index 9e658b2..39085a1 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* dis-asm.h (arc_get_disassembler): Correct declaration.
+
 2001-01-09  Philip Blundell  <philb@gnu.org>
 
 	* bin-bugs.h (REPORT_BUGS_TO): Set to `bug-binutils@gnu.org'.
diff --git a/include/dis-asm.h b/include/dis-asm.h
index 67432e2..5c9d8d8 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -174,7 +174,7 @@ extern int print_insn_h8300h		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_h8300s		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_h8500		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_alpha		PARAMS ((bfd_vma, disassemble_info*));
-extern disassembler_ftype arc_get_disassembler PARAMS ((int, int));
+extern disassembler_ftype arc_get_disassembler PARAMS ((void *));
 extern int print_insn_big_arm		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_little_arm	PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_sparc		PARAMS ((bfd_vma, disassemble_info*));
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 31ffd7c..05e73b8 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,8 +1,15 @@
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* arc.h (E_ARC_MACH_ARC5, E_ARC_MACH_ARC6, E_ARC_MACH_ARC7,
+	E_ARC_MACH_ARC8): New definitions for cpu types.
+
+	* common.h (EM_ARC): Change comment.
+
 2000-12-12  Nick Clifton  <nickc@redhat.com>
 
 	* mips.h: Fix formatting.
 
-Mon Dec 11 10:56:58 2000  Jeffrey A Law  (law@cygnus.com)
+2000-12-11  Jeffrey A Law  (law@cygnus.com)
 
 	* hppa.h (DT_HP_*): Define relative to OLD_DT_LOOS for hpux
 	compatibility.
diff --git a/include/elf/arc.h b/include/elf/arc.h
index 84483fb..a8d0a74 100644
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -26,6 +26,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #include "elf/reloc-macros.h"
 
 /* Relocations.  */
+
 START_RELOC_NUMBERS (elf_arc_reloc_type)
   RELOC_NUMBER (R_ARC_NONE, 0)
   RELOC_NUMBER (R_ARC_32, 1)
@@ -36,18 +37,20 @@ END_RELOC_NUMBERS (R_ARC_max)
 /* Processor specific flags for the ELF header e_flags field.  */
 
 /* Four bit ARC machine type field.  */
-#define EF_ARC_MACH		0x0000000f
+
+#define EF_ARC_MACH 0x0000000f
 
 /* Various CPU types.  */
-#define E_ARC_MACH_BASE		0x00000000
-#define E_ARC_MACH_UNUSED1	0x00000001
-#define E_ARC_MACH_UNUSED2	0x00000002
-#define E_ARC_MACH_UNUSED4	0x00000003
 
-/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.
-   Highly unlikely, but what the heck.  */
+#define E_ARC_MACH_ARC5 0
+#define E_ARC_MACH_ARC6 1	
+#define E_ARC_MACH_ARC7 2
+#define E_ARC_MACH_ARC8 3
+
+/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.  */
 
 /* File contains position independent code.  */
-#define EF_ARC_PIC		0x00000100
+
+#define EF_ARC_PIC 0x00000100
 
 #endif /* _ELF_ARC_H */
diff --git a/include/elf/common.h b/include/elf/common.h
index fc91da2..d127b9c 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -125,7 +125,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #define EM_SH	       42	/* Hitachi SH */
 #define EM_SPARCV9     43	/* SPARC v9 64-bit */
 #define EM_TRICORE     44       /* Siemens Tricore embedded processor */
-#define EM_ARC         45       /* Argonaut RISC Core, Argonaut Technologies Inc. */
+#define EM_ARC         45       /* ARC Cores */
 #define EM_H8_300      46       /* Hitachi H8/300 */
 #define EM_H8_300H     47       /* Hitachi H8/300H */
 #define EM_H8S         48       /* Hitachi H8S */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 2a545d5..b506b66 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,4 +1,12 @@
-Wed Jan 10 15:30:57 MET 2001  Jan Hubicka  <jh@suse.cz>
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New
+	definitions for masking cpu type.
+	(arc_ext_operand_value) New structure for storing extended
+	operands.
+	(ARC_OPERAND_*) Flags for operand values.
+
+2001-01-10  Jan Hubicka  <jh@suse.cz>
 
 	* i386.h (pinsrw): Add.
 	(pshufw): Remove.
@@ -17,16 +25,16 @@ Wed Jan 10 15:30:57 MET 2001  Jan Hubicka  <jh@suse.cz>
 	(CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
 	(CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
 
-Fri Jan  5 13:22:23 MET 2001  Jan Hubicka  <jh@suse.cz>
+2001-01-05  Jan Hubicka  <jh@suse.cz>
 
 	* i386.h (i386_optab): Make [sml]fence template to use immext field.
 
-Wed Jan  3 16:27:15 MET 2001  Jan Hubicka  <jh@suse.cz>
+2001-01-03  Jan Hubicka  <jh@suse.cz>
 
 	* i386.h (i386_optab): Fix 64bit pushf template; Add instructions
 	introduced by Pentium4
 
-Sat Dec 30 19:03:15 MET 2000  Jan Hubicka  <jh@suse.cz>
+2000-12-30  Jan Hubicka  <jh@suse.cz>
 
 	* i386.h (i386_optab): Add "rex*" instructions;
 	add swapgs; disable jmp/call far direct instructions for
@@ -37,7 +45,7 @@ Sat Dec 30 19:03:15 MET 2000  Jan Hubicka  <jh@suse.cz>
 	(*Suf): Add No_qSuf.
 	(q_Suf, wlq_Suf, bwlq_Suf): New.
 
-Wed Dec 20 14:22:03 MET 2000  Jan Hubicka  <jh@suse.cz>
+2000-12-20  Jan Hubicka  <jh@suse.cz>
 
 	* i386.h (i386_optab): Replace "Imm" with "EncImm".
 	(i386_regtab): Add flags field.
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index a1e0ca1..d396b2a 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -1,93 +1,110 @@
 /* Opcode table for the ARC.
-   Copyright 1994, 1995, 1997 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1997, 2000 Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
 
-This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
-the GNU Binutils.
+   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
+   the GNU Binutils.
 
-GAS/GDB is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   GAS/GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-GAS/GDB is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
-GNU General Public License for more details.
+   GAS/GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS or GDB; see the file COPYING.	If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
-You should have received a copy of the GNU General Public License
-along with GAS or GDB; see the file COPYING.	If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
 
 /* List of the various cpu types.
    The tables currently use bit masks to say whether the instruction or
    whatever is supported by a particular cpu.  This lets us have one entry
    apply to several cpus.
 
-   This duplicates bfd_mach_arc_xxx.  For now I wish to isolate this from bfd
-   and bfd from this.  Also note that these numbers are bit values as we want
-   to allow for things available on more than one ARC (but not necessarily all
-   ARCs).  */
-
-/* The `base' cpu must be 0 (table entries are omitted for the base cpu).
-   The cpu type is treated independently of endianness.
-   The complete `mach' number includes endianness.
+   The `base' cpu must be 0. The cpu type is treated independently of
+   endianness. The complete `mach' number includes endianness.
    These values are internal to opcodes/bfd/binutils/gas.  */
-#define ARC_MACH_BASE 0
-#define ARC_MACH_UNUSED1 1
-#define ARC_MACH_UNUSED2 2
-#define ARC_MACH_UNUSED4 4
+#define ARC_MACH_5 0
+#define ARC_MACH_6 1
+#define ARC_MACH_7 2
+#define ARC_MACH_8 4
+
 /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down.  */
-#define ARC_MACH_BIG 8
+#define ARC_MACH_BIG 16
 
 /* Mask of number of bits necessary to record cpu type.  */
-#define ARC_MACH_CPU_MASK 7
+#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
+
 /* Mask of number of bits necessary to record cpu type + endianness.  */
-#define ARC_MACH_MASK 15
+#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
 
 /* Type to denote an ARC instruction (at least a 32 bit unsigned int).  */
+
 typedef unsigned int arc_insn;
 
 struct arc_opcode {
-  char *syntax;			/* syntax of insn */
-  unsigned long mask, value;	/* recognize insn if (op&mask)==value */
-  int flags;			/* various flag bits */
+  char *syntax;              /* syntax of insn  */
+  unsigned long mask, value; /* recognize insn if (op&mask) == value  */
+  int flags;                 /* various flag bits  */
 
 /* Values for `flags'.  */
 
 /* Return CPU number, given flag bits.  */
 #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
+
 /* Return MACH number, given flag bits.  */
 #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
+
 /* First opcode flag bit available after machine mask.  */
-#define ARC_OPCODE_FLAG_START ((ARC_MACH_MASK + 1) << 0)
+#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
+
 /* This insn is a conditional branch.  */
 #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
-
-  /* These values are used to optimize assembly and disassembly.  Each insn is
-     on a list of related insns (same first letter for assembly, same insn code
-     for disassembly).  */
-  struct arc_opcode *next_asm;	/* Next instruction to try during assembly.  */
-  struct arc_opcode *next_dis;	/* Next instruction to try during disassembly.  */
-
-  /* Macros to create the hash values for the lists.  */
+#define SYNTAX_3OP             (ARC_OPCODE_COND_BRANCH << 1)
+#define SYNTAX_LENGTH          (SYNTAX_3OP                 )
+#define SYNTAX_2OP             (SYNTAX_3OP             << 1)
+#define OP1_MUST_BE_IMM        (SYNTAX_2OP             << 1)
+#define OP1_IMM_IMPLIED        (OP1_MUST_BE_IMM        << 1)
+#define SYNTAX_VALID           (OP1_IMM_IMPLIED        << 1)
+
+#define I(x) (((x) & 31) << 27)
+#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
+#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
+#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
+#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
+
+/* These values are used to optimize assembly and disassembly.  Each insn
+   is on a list of related insns (same first letter for assembly, same
+   insn code for disassembly).  */
+
+  struct arc_opcode *next_asm;	/* Next instr to try during assembly.  */
+  struct arc_opcode *next_dis;	/* Next instr to try during disassembly.  */
+
+/* Macros to create the hash values for the lists.  */
 #define ARC_HASH_OPCODE(string) \
   ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
 #define ARC_HASH_ICODE(insn) \
   ((unsigned int) (insn) >> 27)
 
-  /* Macros to access `next_asm', `next_dis' so users needn't care about the
-     underlying mechanism.  */
+ /* Macros to access `next_asm', `next_dis' so users needn't care about the
+    underlying mechanism.  */
 #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
 #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
 };
 
+/* this is an "insert at front" linked list per Metaware spec
+   that new definitions override older ones.  */
+struct arc_opcode *arc_ext_opcodes;
+
 struct arc_operand_value {
-  char *name;			/* eg: "eq" */
-  short value;			/* eg: 1 */
-  unsigned char type;		/* index into `arc_operands' */
-  unsigned char flags;		/* various flag bits */
+  char *name;          /* eg: "eq"  */
+  short value;         /* eg: 1  */
+  unsigned char type;  /* index into `arc_operands'  */
+  unsigned char flags; /* various flag bits  */
 
 /* Values for `flags'.  */
 
@@ -97,18 +114,23 @@ struct arc_operand_value {
 #define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
 };
 
+struct arc_ext_operand_value {
+  struct arc_ext_operand_value *next;
+  struct arc_operand_value operand;
+} *arc_ext_operands;
+
 struct arc_operand {
-  /* One of the insn format chars.  */
+/* One of the insn format chars.  */
   unsigned char fmt;
 
-  /* The number of bits in the operand (may be unused for a modifier).  */
+/* The number of bits in the operand (may be unused for a modifier).  */
   unsigned char bits;
 
-  /* How far the operand is left shifted in the instruction, or
-     the modifier's flag bit (may be unused for a modifier.  */
+/* How far the operand is left shifted in the instruction, or
+   the modifier's flag bit (may be unused for a modifier.  */
   unsigned char shift;
 
-  /* Various flag bits.  */
+/* Various flag bits.  */
   int flags;
 
 /* Values for `flags'.  */
@@ -150,6 +172,19 @@ struct arc_operand {
    in special ways.  */
 #define ARC_OPERAND_FAKE 0x100
 
+/* separate flags operand for j and jl instructions  */
+#define ARC_OPERAND_JUMPFLAGS 0x200
+
+/* allow warnings and errors to be issued after call to insert_xxxxxx  */
+#define ARC_OPERAND_WARN  0x400
+#define ARC_OPERAND_ERROR 0x800
+
+/* this is a load operand */
+#define ARC_OPERAND_LOAD  0x8000
+
+/* this is a store operand */
+#define ARC_OPERAND_STORE 0x10000
+
 /* Modifier values.  */
 /* A dot is required before a suffix.  Eg: .le  */
 #define ARC_MOD_DOT 0x1000
@@ -166,52 +201,57 @@ struct arc_operand {
 /* Non-zero if the operand type is really a modifier.  */
 #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
 
-  /* Insertion function.  This is used by the assembler.  To insert an
-     operand value into an instruction, check this field.
-
-     If it is NULL, execute
-         i |= (p & ((1 << o->bits) - 1)) << o->shift;
-     (I is the instruction which we are filling in, O is a pointer to
-     this structure, and OP is the opcode value; this assumes twos
-     complement arithmetic).
-
-     If this field is not NULL, then simply call it with the
-     instruction and the operand value.  It will return the new value
-     of the instruction.  If the ERRMSG argument is not NULL, then if
-     the operand value is illegal, *ERRMSG will be set to a warning
-     string (the operand will be inserted in any case).  If the
-     operand value is legal, *ERRMSG will be unchanged.
-
-     REG is non-NULL when inserting a register value.  */
+/* enforce read/write only register restrictions  */
+#define ARC_REGISTER_READONLY    0x01
+#define ARC_REGISTER_WRITEONLY   0x02
+#define ARC_REGISTER_NOSHORT_CUT 0x04
+
+/* Insertion function.  This is used by the assembler.  To insert an
+   operand value into an instruction, check this field.
+
+   If it is NULL, execute
+   i |= (p & ((1 << o->bits) - 1)) << o->shift;
+   (I is the instruction which we are filling in, O is a pointer to
+   this structure, and OP is the opcode value; this assumes twos
+   complement arithmetic).
+   
+   If this field is not NULL, then simply call it with the
+   instruction and the operand value.  It will return the new value
+   of the instruction.  If the ERRMSG argument is not NULL, then if
+   the operand value is illegal, *ERRMSG will be set to a warning
+   string (the operand will be inserted in any case).  If the
+   operand value is legal, *ERRMSG will be unchanged.
+
+   REG is non-NULL when inserting a register value.  */
 
   arc_insn (*insert) PARAMS ((arc_insn insn,
 			      const struct arc_operand *operand, int mods,
 			      const struct arc_operand_value *reg, long value,
 			      const char **errmsg));
 
-  /* Extraction function.  This is used by the disassembler.  To
-     extract this operand type from an instruction, check this field.
-
-     If it is NULL, compute
-         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
-	 if ((o->flags & ARC_OPERAND_SIGNED) != 0
-	     && (op & (1 << (o->bits - 1))) != 0)
-	   op -= 1 << o->bits;
-     (I is the instruction, O is a pointer to this structure, and OP
-     is the result; this assumes twos complement arithmetic).
-
-     If this field is not NULL, then simply call it with the
-     instruction value.  It will return the value of the operand.  If
-     the INVALID argument is not NULL, *INVALID will be set to
-     non-zero if this operand type can not actually be extracted from
-     this operand (i.e., the instruction does not match).  If the
-     operand is valid, *INVALID will not be changed.
-
-     INSN is a pointer to an array of two `arc_insn's.  The first element is
-     the insn, the second is the limm if present.
-
-     Operands that have a printable form like registers and suffixes have
-     their struct arc_operand_value pointer stored in OPVAL.  */
+/* Extraction function.  This is used by the disassembler.  To
+   extract this operand type from an instruction, check this field.
+   
+   If it is NULL, compute
+     op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+     if ((o->flags & ARC_OPERAND_SIGNED) != 0
+          && (op & (1 << (o->bits - 1))) != 0)
+       op -= 1 << o->bits;
+   (I is the instruction, O is a pointer to this structure, and OP
+   is the result; this assumes twos complement arithmetic).
+   
+   If this field is not NULL, then simply call it with the
+   instruction value.  It will return the value of the operand.  If
+   the INVALID argument is not NULL, *INVALID will be set to
+   non-zero if this operand type can not actually be extracted from
+   this operand (i.e., the instruction does not match).  If the
+   operand is valid, *INVALID will not be changed.
+
+   INSN is a pointer to an array of two `arc_insn's.  The first element is
+   the insn, the second is the limm if present.
+
+   Operands that have a printable form like registers and suffixes have
+   their struct arc_operand_value pointer stored in OPVAL.  */
 
   long (*extract) PARAMS ((arc_insn *insn,
 			   const struct arc_operand *operand,
@@ -219,9 +259,8 @@ struct arc_operand {
 			   int *invalid));
 };
 
-/* Bits that say what version of cpu we have.
-   These should be passed to arc_init_opcode_tables.
-   At present, all there is is the cpu type.  */
+/* Bits that say what version of cpu we have. These should be passed to
+   arc_init_opcode_tables. At present, all there is is the cpu type.  */
 
 /* CPU number, given value passed to `arc_init_opcode_tables'.  */
 #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
@@ -243,16 +282,16 @@ struct arc_operand {
 #define ARC_MASK_REG 63
 
 /* Delay slot types.  */
-#define ARC_DELAY_NONE 0	/* no delay slot */
-#define ARC_DELAY_NORMAL 1	/* delay slot in both cases */
-#define ARC_DELAY_JUMP 2	/* delay slot only if branch taken */
+#define ARC_DELAY_NONE 0   /* no delay slot */
+#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
+#define ARC_DELAY_JUMP 2   /* delay slot only if branch taken */
 
 /* Non-zero if X will fit in a signed 9 bit field.  */
 #define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
 
 extern const struct arc_operand arc_operands[];
 extern const int arc_operand_count;
-extern /*const*/ struct arc_opcode arc_opcodes[];
+extern struct arc_opcode arc_opcodes[];
 extern const int arc_opcodes_count;
 extern const struct arc_operand_value arc_suffixes[];
 extern const int arc_suffixes_count;
@@ -262,6 +301,7 @@ extern unsigned char arc_operand_map[];
 
 /* Utility fns in arc-opc.c.  */
 int arc_get_opcode_mach PARAMS ((int, int));
+
 /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'.  */
 void arc_opcode_init_tables PARAMS ((int));
 void arc_opcode_init_insert PARAMS ((void));
@@ -269,6 +309,7 @@ void arc_opcode_init_extract PARAMS ((void));
 const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *));
 const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int));
 int arc_opcode_limm_p PARAMS ((long *));
-const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value));
+const struct arc_operand_value *arc_opcode_lookup_suffix
+  PARAMS ((const struct arc_operand *type, int value));
 int arc_opcode_supported PARAMS ((const struct arc_opcode *));
 int arc_opval_supported PARAMS ((const struct arc_operand_value *));
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1d6aaa6..9612b66 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,4 +1,19 @@
-Wed Jan 10 15:13:21 MET 2001  Jan Hubicka  <jh@suse.cz>
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* configure.in: Add arc-ext.lo for bfd_arc_arch selection.
+	* Makefile.am (C_FILES): Add arc-ext.c.
+	(ALL_MACHINES) Add arc-ext.lo.
+	(INCLUDES) Add opcode directory to list.
+	New dependency entry for arc-ext.lo.
+	* disassemble.c (disassembler): Correct call to
+	arc_get_disassembler.
+	* arc-opc.c: New update for ARC, including full base
+	instructions for ARC variants.
+	* arc-dis.h, arc-dis.c: New update for ARC, including
+	extensibility functionality.
+	* arc-ext.h, arc-ext.c: New files for handling extensibility.
+
+2001-01-10  Jan Hubicka  <jh@suse.cz>
 
 	* i386-dis.c (PREGRP15 - PREGRP24): New.
 	(dis386_twobyt): Add SSE2 instructions.
@@ -29,7 +44,7 @@ Wed Jan 10 15:13:21 MET 2001  Jan Hubicka  <jh@suse.cz>
 	* cgen-dis.in (print_insn_normal): Ditto.
 	* cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto.
 
-Fri Jan  5 11:31:07 MET 2001  Jan Hubicka  <jh@suse.cz>
+2001-01-05  Jan Hubicka  <jh@suse.cz>
 
 	* i386-dis.c: Add x86_64 support.
 	(rex): New static variable.
@@ -249,7 +264,7 @@ Fri Jan  5 11:31:07 MET 2001  Jan Hubicka  <jh@suse.cz>
 	* m32r-desc.h: Regenerate.
 	* m32r-ibld.c: Regenerate.
 
-2000-10-05  Jim Wilson  <wilson@cygnus.com>
+2000-10-05  Jim Wilson  <wilson@redhat.com>
 
 	* ia64-ic.tbl: Update from Intel.
 	* ia64-asmtab.c: Regenerate.
@@ -273,7 +288,7 @@ Fri Jan  5 11:31:07 MET 2001  Jan Hubicka  <jh@suse.cz>
 	New.
 	* disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler.
 
-2000-09-22  Jim Wilson  <wilson@cygnus.com>
+2000-09-22  Jim Wilson  <wilson@redhat.com>
 
 	* ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for
 	gt, ge, ngt, and nge.
@@ -342,7 +357,7 @@ Fri Jan  5 11:31:07 MET 2001  Jan Hubicka  <jh@suse.cz>
 	instructions.  Added extended mnemonic mftbl as defined in the
 	405GP manual for all PPCs.
 
-2000-08-28  Jim Wilson  <wilson@cygnus.com>
+2000-08-28  Jim Wilson  <wilson@redhat.com>
 
 	* ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode
 	call.  Change last goto to use failed instead of done.
@@ -388,7 +403,7 @@ Fri Jan  5 11:31:07 MET 2001  Jan Hubicka  <jh@suse.cz>
 
 	* z8k-dis.c: Fix formatting.
 
-2000-08-16  Jim Wilson  <wilson@cygnus.com>
+2000-08-16  Jim Wilson  <wilson@redhat.com>
 
 	* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds.  Delete
 	break, mov-immediate, nop.
@@ -398,16 +413,16 @@ Fri Jan  5 11:31:07 MET 2001  Jan Hubicka  <jh@suse.cz>
 	* ia64-opc.h (POSTINC): Define.
 	* ia64-asmtab.c: Regenerate.
 
-2000-08-15  Jim Wilson  <wilson@cygnus.com>
+2000-08-15  Jim Wilson  <wilson@redhat.com>
 
 	* ia64-ic.tbl: Add missing entries.
 
-2000-08-08  Jason Eckhardt  <jle@cygnus.com>
+2000-08-08  Jason Eckhardt  <jle@redhat.com>
 
 	* i860-dis.c (print_br_address): Change third argument from int
 	to long.
 
-2000-08-07  Richard Henderson  <rth@cygnus.com>
+2000-08-07  Richard Henderson  <rth@redhat.com>
 
 	* ia64-dis.c (print_insn_ia64): Get byte skip count correct
 	for MLI templates.  Handle IA64_OPND_TGT64.
@@ -417,7 +432,7 @@ Fri Jan  5 11:31:07 MET 2001  Jan Hubicka  <jh@suse.cz>
 	* cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files.
 	* cgen.sh: Likewise.
 
-2000-08-02  Jim Wilson  <wilson@cygnus.com>
+2000-08-02  Jim Wilson  <wilson@redhat.com>
 	
 	* ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end.
 
@@ -454,7 +469,7 @@ Fri Jan  5 11:31:07 MET 2001  Jan Hubicka  <jh@suse.cz>
 	ATTRIBUTE_UNUSED.
 	(cgen_parse_keyword): Ditto.
 
-2000-07-22  Jason Eckhardt  <jle@cygnus.com>
+2000-07-22  Jason Eckhardt  <jle@redhat.com>
 
 	* i860-dis.c: New file.
 	(print_insn_i860): New function.
@@ -494,7 +509,7 @@ Fri Jan  5 11:31:07 MET 2001  Jan Hubicka  <jh@suse.cz>
 	* sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2.
 	Reported by Bill Clarke <llib@computer.org>.
 
-2000-07-09  Geoffrey Keating  <geoffk@cygnus.com>
+2000-07-09  Geoffrey Keating  <geoffk@redhat.com>
 
 	* ppc-opc.c (powerpc_opcodes): Correct suffix for vslw.
 	Patch by Randall J Fisher <rfisher@ecn.purdue.edu>.
@@ -574,11 +589,11 @@ Fri Jan  5 11:31:07 MET 2001  Jan Hubicka  <jh@suse.cz>
 	(bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl]
 	correctly.
 
-Fri Jun  9 21:49:02 2000  Denis Chertykov  <denisc@overta.ru>
+2000-06-09  Denis Chertykov  <denisc@overta.ru>
 
 	* avr-dis.c (avr_operand): Bugfix for jmp/call address.
 
-Wed Jun  7 21:36:45 2000  Denis Chertykov  <denisc@overta.ru>
+2000-06-07  Denis Chertykov  <denisc@overta.ru>
 
 	* avr-dis.c: completely rewritten.
 
@@ -593,12 +608,12 @@ Wed Jun  7 21:36:45 2000  Denis Chertykov  <denisc@overta.ru>
 	(bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl]
 	correctly.  Fix a typo.
 
-2000-05-31  Nick Clifton  <nickc@cygnus.com>
+2000-05-31  Nick Clifton  <nickc@redhat.com>
 
 	* opintl.h (_(String)): Explain why dgettext is used instead of
 	gettext.
 
-2000-05-30  Nick Clifton  <nickc@cygnus.com>
+2000-05-30  Nick Clifton  <nickc@redhat.com>
 
 	* opintl.h (gettext, dgettext, dcgettext, textdomain,
 	bindtextdomain): Replace defines with those from intl/libgettext.h
@@ -609,21 +624,21 @@ Wed Jun  7 21:36:45 2000  Denis Chertykov  <denisc@overta.ru>
 	* Makefile.am: Update dependencies with "make dep-am"
 	* Makefile.in: Regenerate.
 
-Thu May 25 22:53:20 2000  Alexandre Oliva  <aoliva@cygnus.com>
+2000-05-25  Alexandre Oliva  <aoliva@redhat.com>
 
 	* m10300-dis.c (disassemble): Don't assume 32-bit longs when
 	sign-extending operands.
 
-Mon May 15 15:18:07 2000  Donald Lindsay  <dlindsay@cygnus.com>
+2000-05-15  Donald Lindsay  <dlindsay@redhat.com>
 
 	* d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches
 	except brf's.
 
-2000-05-21  Nick Clifton  <nickc@cygnus.com>
+2000-05-21  Nick Clifton  <nickc@redhat.com>
 
 	* Makefile.am (LIBIBERTY): Define.
 
-Fri May 19 12:29:27 EDT 2000	Diego Novillo <dnovillo@redhat.com>
+2000-05-19 Diego Novillo <dnovillo@redhat.com>
 
 	* mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.
 	(STD_REGISTER_NAMES): New name for REGISTER_NAMES.
@@ -639,7 +654,7 @@ Fri May 19 12:29:27 EDT 2000	Diego Novillo <dnovillo@redhat.com>
 	CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
 	* m32r-desc.h: Ditto.
 
-2000-05-15  Nick Clifton  <nickc@cygnus.com>
+2000-05-15  Nick Clifton  <nickc@redhat.com>
 
 	* arm-opc.h: Use upper case for flasg in MSR and MRS
 	instructions.  Allow any bit to be set in the field_mask of
@@ -658,7 +673,7 @@ Fri May 19 12:29:27 EDT 2000	Diego Novillo <dnovillo@redhat.com>
 	* mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
 	target addresses for 'jal' and 'j'.
 
-2000-05-10  Geoff Keating  <geoffk@cygnus.com>
+2000-05-10  Geoff Keating  <geoffk@redhat.com>
 
 	* ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes
 	also available in common mode when powerpc syntax is being used.
@@ -668,7 +683,7 @@ Fri May 19 12:29:27 EDT 2000	Diego Novillo <dnovillo@redhat.com>
 	* m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args.
 	(dummy_print_address): Ditto.
 
-2000-05-04  Timothy Wall  <twall@cygnus.com>
+2000-05-04  Timothy Wall  <twall@redhat.com>
 
 	* tic54x-opc.c: New.
 	* tic54x-dis.c: New.
@@ -692,18 +707,18 @@ Fri May 19 12:29:27 EDT 2000	Diego Novillo <dnovillo@redhat.com>
 	(print_insn_little_powerpc): Likewise.
 	(print_insn_powerpc): Prepend 'v' when printing vector registers.
 
-Mon Apr 24 15:21:35 2000  Clinton Popetz  <cpopetz@cygnus.com>
+2000-04-24  Clinton Popetz  <cpopetz@redhat.com>
 
 	* configure.in: Add bfd_powerpc_64_arch.
 	* disassemble.c (disassembler): Use print_insn_big_powerpc for
 	64 bit code.
 
-2000-04-24  Nick Clifton  <nickc@cygnus.com>
+2000-04-24  Nick Clifton  <nickc@redhat.com>
 
 	* fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow
 	field.
 
-Sun Apr 23 17:54:14 2000  Denis Chertykov  <denisc@overta.ru>
+2000-04-23  Denis Chertykov  <denisc@overta.ru>
 
 	* avr-dis.c (reg_fmul_d): New. Extract destination register from
 	FMUL instruction.
@@ -715,7 +730,7 @@ Sun Apr 23 17:54:14 2000  Denis Chertykov  <denisc@overta.ru>
 	(print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU,
 	EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions.
 
-2000-04-22  Timothy Wall  <twall@cygnus.com>
+2000-04-22  Timothy Wall  <twall@redhat.com>
 
 	* ia64-gen.c (general): Add an ordered table of primary
 	opcode names, as well as priority fields to disassembly data
@@ -732,17 +747,17 @@ Sun Apr 23 17:54:14 2000  Denis Chertykov  <denisc@overta.ru>
 	* ia64-opc-b.c: Use more abbreviations.
 	* ia64-asmtab.c: Regenerate.
 
-Fri Apr 21 16:03:39 2000  Jason Eckhardt  <jle@cygnus.com>
+2000-04-21  Jason Eckhardt  <jle@redhat.com>
 
 	* hppa-dis.c (extract_16): New function.
 	(print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of
 	new operand types l,y,&,fe,fE,fx.
 
-Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
-			  David Mosberger  <davidm@hpl.hp.com>
-			  Timothy Wall <twall@cygnus.com>
-			  Bob Manson  <manson@charmed.cygnus.com>
-			  Jim Wilson  <wilson@cygnus.com>
+2000-04-21  Richard Henderson  <rth@redhat.com>
+	    David Mosberger  <davidm@hpl.hp.com>
+	    Timothy Wall <twall@redhat.com>
+	    Bob Manson  <manson@charmed.cygnus.com>
+	    Jim Wilson  <wilson@redhat.com>
 
 	* Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
 	(CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
@@ -761,7 +776,7 @@ Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
 	ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
 	ia64-war.tbl, ia64-waw.tbl): New files.
 
-2000-04-20  Alexandre Oliva  <aoliva@cygnus.com>
+2000-04-20  Alexandre Oliva  <aoliva@redhat.com>
 
 	* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
 	(disassemble): Use them.
@@ -785,21 +800,21 @@ Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
 	w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h.  Remove
 	ansidecl.h as sysdep.h includes it.
 
-Fri Apr  7 15:56:57 2000  Andrew Cagney  <cagney@b1.cygnus.com>
+2000-04-7  Andrew Cagney  <cagney@b1.redhat.com>
 
 	* configure.in (WARN_CFLAGS): Set to -W -Wall by default.  Add
 	--enable-build-warnings option.
 	* Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions.
 	* Makefile.in, configure: Re-generate.
 
-Wed Apr  5 22:28:18 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
+2000-04-05  J"orn Rennecke <amylaar@redhat.com>
 
 	* sh-opc.c (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs.
 	stc GBR,@-<REG_N> is available for arch_sh1_up.
 	Group parallel processing insn with identical mnemonics together.
 	Make three-operand psha / pshl come first.
 
-Wed Apr  5 22:05:40 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
+2000-04-05  J"orn Rennecke <amylaar@redhat.co.uk>
 
 	* sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
 	Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}.  Add REPEAT.
@@ -832,7 +847,7 @@ Wed Apr  5 22:05:40 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	the parameter ATTRIBUTE_UNUSED.
 	* ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
 
-2000-04-01  Alexandre Oliva  <aoliva@cygnus.com>
+2000-04-01  Alexandre Oliva  <aoliva@redhat.com>
 
 	* m10300-opc.c: SP-based offsets are always unsigned.
 
@@ -841,7 +856,7 @@ Wed Apr  5 22:05:40 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	* arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
 	[branch always] instead of "undefined".
 
-2000-03-27  Nick Clifton  <nickc@cygnus.com>
+2000-03-27  Nick Clifton  <nickc@redhat.com>
 
 	* d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of
 	short instructions, from end of list of long instructions.
@@ -868,11 +883,11 @@ Wed Apr  5 22:05:40 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	* disassemble.c: Likewise.
 	* configure: Regenerate.
 
-Mon Mar  6 19:52:05 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
+2000-03-06  J"oern Rennecke <amylaar@redhat.com>
 
 	* sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.
 
-2000-03-02  J"orn Rennecke <amylaar@cygnus.co.uk>
+2000-03-02  J"orn Rennecke <amylaar@redhat.co.uk>
 
 	* d30v-dis.c (print_insn): Remove d*i hacks.  Use per-operand
 	flag to determine if operand is pc-relative.
@@ -893,7 +908,7 @@ Mon Mar  6 19:52:05 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	(SHORT_U, SHORT_A5S): Removed stray alternatives.
 	(d30v_opcode_table): Use new *r formats.
 
-2000-02-28  Nick Clifton  <nickc@cygnus.com>
+2000-02-28  Nick Clifton  <nickc@redhat.com>
 
 	* m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
 	'signed_overflow_ok_p'.
@@ -904,13 +919,13 @@ Mon Mar  6 19:52:05 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	name of the libtool directory.
 	* Makefile.in: Rebuild.
 
-2000-02-24  Nick Clifton  <nickc@cygnus.com>
+2000-02-24  Nick Clifton  <nickc@redhat.com>
 
 	* cgen-opc.c (cgen_set_signed_overflow_ok): New function.
 	(cgen_clear_signed_overflow_ok): New function.
 	(cgen_signed_overflow_ok_p): New function.
 
-2000-02-23  Andrew Haley  <aph@cygnus.com>
+2000-02-23  Andrew Haley  <aph@redhat.com>
 
 	* m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
 	m32r-ibld.c,m32r-opc.h: Rebuild.
@@ -928,13 +943,13 @@ Mon Mar  6 19:52:05 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	* Makefile.in: Regenerate.
 	* configure: Likewise.
 
-2000-02-22  Chandra Chavva   <cchavva@cygnus.com>
+2000-02-22  Chandra Chavva   <cchavva@redhat.com>
 
 	* d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
 	ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
 	procedure.
 
-2000-02-22  Andrew Haley  <aph@cygnus.com>
+2000-02-22  Andrew Haley  <aph@redhat.com>
 
 	* mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
 	force gp32 to zero.
@@ -951,7 +966,7 @@ Mon Mar  6 19:52:05 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	* dis-buf.c (buffer_read_memory): Change `length' param and all int
 	vars to unsigned.
 
-Thu Feb 17 00:18:12 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
+2000-02-17 J"orn Rennecke <amylaar@redhat.co.uk>
 
 	* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
 	(print_insn_ppi): Likewise.
@@ -968,7 +983,7 @@ Thu Feb 17 00:18:12 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
 	D_REG_N.  Fill in arch field.  Add sh-dsp insns.
 
-2000-02-14  Fernando Nasser  <fnasser@totem.to.cygnus.com>
+2000-02-14  Fernando Nasser  <fnasser@totem.to.redhat.com>
 
 	* arm-dis.c: Change flavor name from atpcs-special to
 	special-atpcs to prevent name conflict in gdb.
@@ -978,7 +993,7 @@ Thu Feb 17 00:18:12 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	(print_insn_thumb): Use the register name entry from the currently
 	selected flavor for LR and PC.
 
-2000-02-10  Nick Clifton  <nickc@cygnus.com>
+2000-02-10  Nick Clifton  <nickc@redhat.com>
 
 	* mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
 	classes.
@@ -989,7 +1004,7 @@ Thu Feb 17 00:18:12 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	(print_insn_mcore): Add support for little endian targets.
 	Add support for MULSH and OPSR classes.
 
-2000-02-07  Nick Clifton  <nickc@cygnus.com>
+2000-02-07  Nick Clifton  <nickc@redhat.com>
 
 	* arm-dis.c (parse_arm_diassembler_option): Rename again.
 	Previous delat did not take.
@@ -1034,7 +1049,7 @@ Thu Feb 17 00:18:12 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 	* arm-dis.c (printf_insn_thumb): Prevent double dumping
 	of raw thumb instructions.
 
-2000-01-20  Nick Clifton  <nickc@cygnus.com>
+2000-01-20  Nick Clifton  <nickc@redhat.com>
 
 	* mcore-opc.h (mcore_table): Add "add" as an alias for "addu".
 
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 9cf5b1a..e31d9c1 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -40,6 +40,7 @@ CFILES = \
 	alpha-opc.c \
 	arc-dis.c \
 	arc-opc.c \
+	arc-ext.c \
 	arm-dis.c \
 	avr-dis.c \
 	cgen-asm.c \
@@ -121,6 +122,7 @@ ALL_MACHINES = \
 	alpha-opc.lo \
 	arc-dis.lo \
 	arc-opc.lo \
+	arc-ext.lo \
 	arm-dis.lo \
 	avr-dis.lo \
 	cgen-asm.lo \
@@ -342,9 +344,10 @@ arc-dis.lo: arc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/arc.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \
-  $(INCDIR)/elf/reloc-macros.h opintl.h
+  $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h
 arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/arc.h opintl.h
+arc-ext.lo: $(BFD_H) $(INCDIR)/libiberty.h arc-ext.h
 arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) arm-opc.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index f7a0feb..e406027 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -151,6 +151,7 @@ CFILES = \
 	alpha-opc.c \
 	arc-dis.c \
 	arc-opc.c \
+	arc-ext.c \
 	arm-dis.c \
 	avr-dis.c \
 	cgen-asm.c \
@@ -233,6 +234,7 @@ ALL_MACHINES = \
 	alpha-opc.lo \
 	arc-dis.lo \
 	arc-opc.lo \
+	arc-ext.lo \
 	arm-dis.lo \
 	avr-dis.lo \
 	cgen-asm.lo \
@@ -852,9 +854,10 @@ arc-dis.lo: arc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/arc.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \
-  $(INCDIR)/elf/reloc-macros.h opintl.h
+  $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h
 arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/arc.h opintl.h
+arc-ext.lo: $(BFD_H) $(INCDIR)/libiberty.h arc-ext.h
 arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) arm-opc.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h \
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 03f1379..3920006 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -1,268 +1,1220 @@
 /* Instruction printing code for the ARC.
-   Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc. 
+   Copyright (C) 1994, 1995, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. 
    Contributed by Doug Evans (dje@cygnus.com).
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
-#include "sysdep.h"
+#include <ansidecl.h>
+#include <libiberty.h>
 #include "dis-asm.h"
 #include "opcode/arc.h"
 #include "elf-bfd.h"
 #include "elf/arc.h"
+#include <string.h>
 #include "opintl.h"
 
-static int print_insn_arc_base_little PARAMS ((bfd_vma, disassemble_info *));
-static int print_insn_arc_base_big PARAMS ((bfd_vma, disassemble_info *));
+#include <ctype.h>
+#include <stdarg.h>
+#include "arc-dis.h"
+#include "arc-ext.h"
 
-static int print_insn PARAMS ((bfd_vma, disassemble_info *, int, int));
+#ifndef dbg
+#define dbg (0)
+#endif
 
-/* Print one instruction from PC on INFO->STREAM.
-   Return the size of the instruction (4 or 8 for the ARC). */
+#define BIT(word,n) 	((word) & (1 << n))
+#define BITS(word,s,e)  (((word) << (31 - e)) >> (s + (31 - e))) 
+#define OPCODE(word) 	(BITS ((word), 27, 31))
+#define FIELDA(word) 	(BITS ((word), 21, 26))
+#define FIELDB(word) 	(BITS ((word), 15, 20))
+#define FIELDC(word) 	(BITS ((word),  9, 14))
 
-static int
-print_insn (pc, info, mach, big_p)
-     bfd_vma pc;
-     disassemble_info *info;
-     int mach;
-     int big_p;
+/* FIELD D is signed in all of its uses, so we make sure argument is
+   treated as signed for bit shifting purposes:  */
+#define FIELDD(word) 	(BITS (((signed int)word), 0, 8))
+
+#define PUT_NEXT_WORD_IN(a)							\
+  do										\
+    {										\
+      if (is_limm == 1 && !NEXT_WORD (1))					\
+        mwerror (state, _("Illegal limm reference in last instruction!\n"));	\
+        a = state->words[1];							\
+    }										\
+  while (0)
+
+#define CHECK_FLAG_COND_NULLIFY()				\
+  do								\
+    {								\
+      if (is_shimm == 0)					\
+        {							\
+          flag = BIT (state->words[0], 8);			\
+          state->nullifyMode = BITS (state->words[0], 5, 6);	\
+          cond = BITS (state->words[0], 0, 4);			\
+        }							\
+    }								\
+  while (0)
+
+#define CHECK_COND()				\
+  do						\
+    {						\
+      if (is_shimm == 0)			\
+        cond = BITS (state->words[0], 0, 4);	\
+    }						\
+  while (0)
+
+#define CHECK_FIELD(field)			\
+  do						\
+    {						\
+      if (field == 62)				\
+        {					\
+          is_limm++;				\
+	  field##isReg = 0;			\
+	  PUT_NEXT_WORD_IN (field);		\
+	  limm_value = field;			\
+	}					\
+      else if (field > 60)			\
+        {					\
+	  field##isReg = 0;			\
+	  is_shimm++;				\
+	  flag = (field == 61);			\
+	  field = FIELDD (state->words[0]);	\
+	}					\
+    }						\
+  while (0)
+
+#define CHECK_FIELD_A()				\
+  do						\
+    {						\
+      fieldA = FIELDA(state->words[0]);		\
+      if (fieldA > 60)				\
+        {					\
+	  fieldAisReg = 0;			\
+	  fieldA = 0;				\
+	}					\
+    }						\
+  while (0)
+
+#define CHECK_FIELD_B()				\
+  do						\
+    {						\
+      fieldB = FIELDB (state->words[0]);	\
+      CHECK_FIELD (fieldB);			\
+    }						\
+  while (0)
+
+#define CHECK_FIELD_C()				\
+  do						\
+    {						\
+      fieldC = FIELDC (state->words[0]);	\
+      CHECK_FIELD (fieldC);			\
+    }						\
+  while (0)
+
+#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
+#define IS_REG(x)   (field##x##isReg)
+#define WRITE_FORMAT_LB_Rx_RB(x)     WRITE_FORMAT(x,"[","]","","")
+#define WRITE_FORMAT_x_COMMA_LB(x)   WRITE_FORMAT(x,"",",[","",",[")
+#define WRITE_FORMAT_COMMA_x_RB(x)   WRITE_FORMAT(x,",","]",",","]")
+#define WRITE_FORMAT_x_RB(x)         WRITE_FORMAT(x,"","]","","]")
+#define WRITE_FORMAT_COMMA_x(x)      WRITE_FORMAT(x,",","",",","")
+#define WRITE_FORMAT_x_COMMA(x)      WRITE_FORMAT(x,"",",","",",")
+#define WRITE_FORMAT_x(x)            WRITE_FORMAT(x,"","","","")
+#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString,		\
+				     (IS_REG (x) ? cb1"%r"ca1 :		\
+				      usesAuxReg ? cb"%a"ca :		\
+				      IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
+#define WRITE_FORMAT_RB() 	strcat (formatString, "]")
+#define WRITE_COMMENT(str)	(state->comm[state->commNum++] = (str))
+#define WRITE_NOP_COMMENT() 	if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
+
+#define NEXT_WORD(x) 	(offset += 4, state->words[x])
+
+#define add_target(x) 	(state->targets[state->tcnt++] = (x))
+
+static char comment_prefix[] = "\t; ";
+
+static const char *
+core_reg_name (state, val)
+     struct arcDisState * state;
+     int                  val; 
 {
-  const struct arc_opcode *opcode;
-  bfd_byte buffer[4];
-  void *stream = info->stream;
-  fprintf_ftype func = info->fprintf_func;
-  int status;
-  /* First element is insn, second element is limm (if present).  */
-  arc_insn insn[2];
-  int got_limm_p = 0;
-  static int initialized = 0;
-  static int current_mach = 0;
+  if (state->coreRegName)
+    return (*state->coreRegName)(state->_this, val);
+  return 0;
+}
 
-  if (!initialized || mach != current_mach)
-    {
-      initialized = 1;
-      current_mach = arc_get_opcode_mach (mach, big_p);
-      arc_opcode_init_tables (current_mach);
-    }
+static const char *
+aux_reg_name (state, val)
+     struct arcDisState * state;
+     int                  val; 
+{
+  if (state->auxRegName)
+    return (*state->auxRegName)(state->_this, val);
+  return 0;
+}
 
-  status = (*info->read_memory_func) (pc, buffer, 4, info);
-  if (status != 0)
+static const char *
+cond_code_name (state, val)
+     struct arcDisState * state;
+     int                  val; 
+{
+  if (state->condCodeName)
+    return (*state->condCodeName)(state->_this, val);
+  return 0;
+}
+
+static const char *
+instruction_name (state, op1, op2, flags)
+     struct arcDisState * state;
+     int    op1;
+     int    op2;
+     int *  flags; 
+{
+  if (state->instName)
+    return (*state->instName)(state->_this, op1, op2, flags);
+  return 0;
+}
+
+static void
+mwerror (state, msg)
+     struct arcDisState * state;
+     const char * msg; 
+{
+  if (state->err != 0)
+    (*state->err)(state->_this, (msg));
+}
+
+static const char *
+post_address (state, addr)
+     struct arcDisState * state;
+     int addr; 
+{
+  static char id[3 * ARRAY_SIZE (state->addresses)];
+  int j, i = state->acnt;
+
+  if (i < ((int) ARRAY_SIZE (state->addresses)))
     {
-      (*info->memory_error_func) (status, pc, info);
-      return -1;
+      state->addresses[i] = addr;
+      ++state->acnt;
+      j = i*3;
+      id[j+0] = '@';
+      id[j+1] = '0'+i;
+      id[j+2] = 0;
+      
+      return id + j;
     }
-  if (big_p)
-    insn[0] = bfd_getb32 (buffer);
-  else
-    insn[0] = bfd_getl32 (buffer);
+  return "";
+}
 
-  (*func) (stream, "%08lx\t", insn[0]);
+static void 
+my_sprintf (
+	    struct arcDisState * state,
+	    char * buf,
+	    const char * format,
+	    ...)
+{
+  char *bp; 
+  const char *p;
+  int size, leading_zero, regMap[2];
+  long auxNum;
+  va_list ap;
+  
+  va_start (ap, format);
+  
+  bp = buf; 
+  *bp = 0;
+  p = format;
+  auxNum = -1;
+  regMap[0] = 0;
+  regMap[1] = 0;
+  
+  while (1) 
+    switch (*p++)
+      {
+    case 0:
+      goto DOCOMM; /* (return)  */
+      default: 
+	*bp++ = p[-1]; 
+	break;
+      case '%':
+	size = 0;
+	leading_zero = 0;
+      RETRY: ;
+	switch (*p++) 
+	  {
+	  case '0':
+	  case '1':
+	  case '2':
+	  case '3':
+	  case '4':
+	  case '5':
+	  case '6':
+	  case '7':
+	  case '8':
+	  case '9':
+	    {
+	      /* size.  */
+	      size = p[-1] - '0';
+	      if (size == 0)
+		leading_zero = 1; /* e.g. %08x  */
+	      while (*p >= '0' && *p <= '9')
+		{
+		  size = size * 10 + *p - '0';
+		  p++;
+		}
+	      goto RETRY;
+	    }
+#define inc_bp() bp = bp + strlen (bp)
 
-  /* The instructions are stored in lists hashed by the insn code
-     (though we needn't care how they're hashed).  */
+	  case 'h': 
+	    {
+	      unsigned u = va_arg (ap, int);
 
-  opcode = arc_opcode_lookup_dis (insn[0]);
-  for ( ; opcode != NULL; opcode = ARC_OPCODE_NEXT_DIS (opcode))
-    {
-      char *syn;
-      int mods,invalid;
-      long value;
-      const struct arc_operand *operand;
-      const struct arc_operand_value *opval;
-
-      /* Basic bit mask must be correct.  */
-      if ((insn[0] & opcode->mask) != opcode->value)
-	continue;
-
-      /* Supported by this cpu?  */
-      if (! arc_opcode_supported (opcode))
-	continue;
-
-      /* Make two passes over the operands.  First see if any of them
-	 have extraction functions, and, if they do, make sure the
-	 instruction is valid.  */
-
-      arc_opcode_init_extract ();
-      invalid = 0;
-
-      /* ??? Granted, this is slower than the `ppc' way.  Maybe when this is
-	 done it'll be clear what the right way to do this is.  */
-      /* Instructions like "add.f r0,r1,1" are tricky because the ".f" gets
-	 printed first, but we don't know how to print it until we've processed
-	 the regs.  Since we're scanning all the args before printing the insn
-	 anyways, it's actually quite easy.  */
-
-      for (syn = opcode->syntax; *syn; ++syn)
-	{
-	  int c;
+	      /* Hex.  We can change the format to 0x%08x in
+		 one place, here, if we wish.
+		 We add underscores for easy reading.  */
+	      if (u > 65536) 
+		sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
+	      else 
+		sprintf (bp, "0x%x", u);
+	      inc_bp ();
+	    } 
+	    break;
+	  case 'X': case 'x': 
+	    {
+	      int val = va_arg (ap, int);
 
-	  if (*syn != '%' || *++syn == '%')
-	    continue;
-	  mods = 0;
-	  c = *syn;
-	  while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags))
+	      if (size != 0) 
+		if (leading_zero)
+		  sprintf (bp, "%0*x", size, val);
+		else
+		  sprintf (bp, "%*x", size, val);
+	      else
+		sprintf (bp, "%x", val);
+	      inc_bp ();
+	    }
+	    break;
+	  case 'd': 
 	    {
-	      mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS;
-	      ++syn;
-	      c = *syn;
+	      int val = va_arg (ap, int);
+	    
+	      if (size != 0)
+		sprintf (bp, "%*d", size, val);
+	      else
+		sprintf (bp, "%d", val);
+	      inc_bp ();
 	    }
-	  operand = arc_operands + arc_operand_map[c];
-	  if (operand->extract)
-	    (*operand->extract) (insn, operand, mods,
-				 (const struct arc_operand_value **) NULL,
-				 &invalid);
-	}
-      if (invalid)
-	continue;
+	    break;
+	  case 'r': 
+	    {
+	      /* Register.  */
+	      int val = va_arg (ap, int);
+	    
+#define REG2NAME(num, name) case num: sprintf (bp, ""name); \
+  regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
+	      
+	      switch (val) 
+		{
+		  REG2NAME (26, "gp");
+		  REG2NAME (27, "fp");
+		  REG2NAME (28, "sp");
+		  REG2NAME (29, "ilink1");
+		  REG2NAME (30, "ilink2");
+		  REG2NAME (31, "blink");
+		  REG2NAME (60, "lp_count");
+		default:
+		  {
+		    const char * ext;
+
+		    ext = core_reg_name (state, val);
+		    if (ext)
+		      sprintf (bp, "%s", ext);
+		    else
+		      sprintf (bp,"r%d",val);
+		  }
+		  break;
+		}
+	      inc_bp ();
+	    } break;
+	  
+	  case 'a': 
+	    {
+	      /* Aux Register.  */
+	      int val = va_arg (ap, int);
 
-      /* The instruction is valid.  */
+#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
 
-      /* If we have an insn with a limm, fetch it now.  Scanning the insns
-	 twice lets us do this.  */
-      if (arc_opcode_limm_p (NULL))
-	{
-	  status = (*info->read_memory_func) (pc + 4, buffer, 4, info);
-	  if (status != 0)
+	      switch (val) 
+		{
+		  AUXREG2NAME (0x0, "status");
+		  AUXREG2NAME (0x1, "semaphore");
+		  AUXREG2NAME (0x2, "lp_start");
+		  AUXREG2NAME (0x3, "lp_end");
+		  AUXREG2NAME (0x4, "identity");
+		  AUXREG2NAME (0x5, "debug");
+		default:
+		  {
+		    const char *ext;
+
+		    ext = aux_reg_name (state, val);
+		    if (ext)
+		      sprintf (bp, "%s", ext);
+		    else
+		      my_sprintf (state, bp, "%h", val);
+		  }
+		  break;
+		}
+	      inc_bp ();
+	    }
+	    break;
+	    
+	  case 's': 
 	    {
-	      (*info->memory_error_func) (status, pc, info);
-	      return -1;
+	      sprintf (bp, "%s", va_arg (ap, char *));
+	      inc_bp ();
 	    }
-	  if (big_p)
-	    insn[1] = bfd_getb32 (buffer);
+	    break;
+	    
+	  default:
+	    fprintf (stderr, "?? format %c\n", p[-1]);
+	    break;
+	  }
+      }
+
+ DOCOMM: *bp = 0;
+}
+
+static void 
+write_comments_(state, shimm, is_limm, limm_value)
+     struct arcDisState * state;
+     int shimm;
+     int is_limm;
+     long limm_value;
+{
+  if (state->commentBuffer != 0) 
+    {
+      int i;
+
+      if (is_limm) 
+	{
+	  const char *name = post_address (state, limm_value + shimm);
+
+	  if (*name != 0)
+	    WRITE_COMMENT (name);
+	}
+      for (i = 0; i < state->commNum; i++) 
+	{
+	  if (i == 0)
+	    strcpy (state->commentBuffer, comment_prefix);
 	  else
-	    insn[1] = bfd_getl32 (buffer);
-	  got_limm_p = 1;
+	    strcat (state->commentBuffer, ", ");	
+	  strncat (state->commentBuffer, state->comm[i], sizeof (state->commentBuffer));
 	}
+    }
+}
 
-      for (syn = opcode->syntax; *syn; ++syn)
-	{
-	  int c;
+#define write_comments2(x) write_comments_(state, x, is_limm, limm_value)
+#define write_comments() write_comments2(0)
+
+static const char *condName[] = {
+  /* 0..15.  */
+  ""   , "z"  , "nz" , "p"  , "n"  , "c"  , "nc" , "v"  , 
+  "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
+};
+
+static void 
+write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem)
+     struct arcDisState * state;
+     const char * instrName;
+     int cond;
+     int condCodeIsPartOfName;
+     int flag;
+     int signExtend;
+     int addrWriteBack;
+     int directMem;
+{
+  strcpy (state->instrBuffer, instrName);
+
+  if (cond > 0) 
+    {
+      const char *cc = 0;
+
+      if (!condCodeIsPartOfName)
+	strcat (state->instrBuffer, ".");
+
+      if (cond < 16)
+	cc = condName[cond];
+      else
+	cc = cond_code_name (state, cond);
+
+      if (!cc)
+	cc = "???";
+
+      strcat (state->instrBuffer, cc);
+    }
+
+  if (flag)
+    strcat (state->instrBuffer, ".f");
+
+  switch (state->nullifyMode) 
+    {
+    case BR_exec_always:
+      strcat (state->instrBuffer, ".d");
+      break;
+    case BR_exec_when_jump:
+      strcat (state->instrBuffer, ".jd");
+      break;
+    }
+
+  if (signExtend)
+    strcat (state->instrBuffer, ".x");
+
+  if (addrWriteBack)
+    strcat (state->instrBuffer, ".a");
+
+  if (directMem)
+    strcat (state->instrBuffer, ".di");
+}
+
+#define write_instr_name()						\
+  do									\
+    {									\
+      write_instr_name_(state, instrName,cond, condCodeIsPartOfName,	\
+			flag, signExtend, addrWriteBack, directMem);	\
+      formatString[0] = '\0';						\
+    }									\
+  while (0)
+
+enum { 
+  op_LD0 = 0, op_LD1 = 1, op_ST  = 2, op_3   = 3, 
+  op_BC  = 4, op_BLC = 5, op_LPC = 6, op_JC  = 7,
+  op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, 
+  op_AND = 12, op_OR  = 13, op_BIC = 14, op_XOR = 15
+};
+
+extern disassemble_info tm_print_insn_info;
 
-	  if (*syn != '%' || *++syn == '%')
+static int 
+dsmOneArcInst (addr, state)
+     bfd_vma              addr;
+     struct arcDisState * state;
+{
+  int condCodeIsPartOfName = 0;
+  int decodingClass;
+  const char * instrName;
+  int repeatsOp = 0;
+  int fieldAisReg = 1;
+  int fieldBisReg = 1;
+  int fieldCisReg = 1;
+  int fieldA;
+  int fieldB;
+  int fieldC = 0;
+  int flag = 0;
+  int cond = 0;
+  int is_shimm = 0;
+  int is_limm = 0;
+  long limm_value = 0;
+  int signExtend = 0;
+  int addrWriteBack = 0;
+  int directMem = 0;
+  int is_linked = 0;
+  int offset = 0;
+  int usesAuxReg = 0;
+  int flags;
+  int ignoreFirstOpd;
+  char formatString[60];
+  
+  state->instructionLen = 4;
+  state->nullifyMode = BR_exec_when_no_jump;
+  state->opWidth = 12;
+  state->isBranch = 0;
+  
+  state->_mem_load = 0;
+  state->_ea_present = 0;
+  state->_load_len = 0;
+  state->ea_reg1 = no_reg;
+  state->ea_reg2 = no_reg;
+  state->_offset = 0;
+  
+  if (! NEXT_WORD (0))
+    return 0;
+  
+  state->_opcode = OPCODE (state->words[0]);
+  instrName = 0;
+  decodingClass = 0; /* default!  */
+  repeatsOp = 0;
+  condCodeIsPartOfName=0;
+  state->commNum = 0;
+  state->tcnt = 0;
+  state->acnt = 0;
+  state->flow = noflow;
+  ignoreFirstOpd = 0;
+
+  if (state->commentBuffer)
+    state->commentBuffer[0] = '\0';
+
+  switch (state->_opcode) 
+    {
+    case op_LD0: 
+      switch (BITS (state->words[0],1,2)) 
+	{
+	case 0:
+	  instrName = "ld";
+	  state->_load_len = 4;
+	  break;
+	case 1:
+	  instrName = "ldb";
+	  state->_load_len = 1;
+	  break;
+	case 2:
+	  instrName = "ldw";
+	  state->_load_len = 2;
+	  break;
+	default:
+	  instrName = "??? (0[3])"; 
+	  state->flow = invalid_instr;
+	  break;
+	}
+      decodingClass = 5; 
+      break;
+    
+    case op_LD1: 
+      if (BIT (state->words[0],13)) 
+	{
+	  instrName = "lr"; 
+	  decodingClass = 10;
+	}
+      else 
+	{
+	  switch (BITS (state->words[0],10,11)) 
 	    {
-	      (*func) (stream, "%c", *syn);
-	      continue;
+	    case 0:
+	      instrName = "ld";
+	      state->_load_len = 4;
+	      break;
+	    case 1:
+	      instrName = "ldb";
+	      state->_load_len = 1;
+	      break;
+	    case 2:
+	      instrName = "ldw";
+	      state->_load_len = 2;
+	      break;
+	    default:
+	      instrName = "??? (1[3])"; 
+	      state->flow = invalid_instr;
+	      break;
 	    }
-
-	  /* We have an operand.  Fetch any special modifiers.  */
-	  mods = 0;
-	  c = *syn;
-	  while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags))
+	  decodingClass = 6;
+	}
+      break;
+      
+    case op_ST:
+      if (BIT (state->words[0],25)) 
+	{
+	  instrName = "sr";
+	  decodingClass = 8;
+	}
+      else 
+	{
+	  switch (BITS (state->words[0],22,23)) 
+	    {
+	    case 0:
+	      instrName = "st";
+	      break;
+	    case 1:
+	      instrName = "stb";
+	      break;
+	    case 2:
+	      instrName = "stw";
+	      break;
+	    default:
+	      instrName = "??? (2[3])"; 
+	      state->flow = invalid_instr;
+	      break;
+	    }
+	  decodingClass = 7;
+	}
+      break;
+      
+    case op_3:
+      decodingClass = 1;  /* default for opcode 3...  */
+      switch (FIELDC (state->words[0])) 
+	{
+	case  0:
+	  instrName = "flag"; 
+	  decodingClass = 2;
+	  break;
+	case  1:
+	  instrName = "asr";
+	  break;
+	case  2:
+	  instrName = "lsr";
+	  break;
+	case  3:
+	  instrName = "ror";
+	  break;
+	case  4:
+	  instrName = "rrc";
+	  break;
+	case  5:
+	  instrName = "sexb";
+	  break;
+	case  6:
+	  instrName = "sexw";
+	  break;
+	case  7:
+	  instrName = "extb";
+	  break;
+	case  8:
+	  instrName = "extw";
+	  break;
+	case  0x3f: 
+	  {
+	    decodingClass = 9;
+	    switch( FIELDD (state->words[0]) ) 
+	      {
+	      case 0:
+		instrName = "brk";
+		break;
+	      case 1:
+		instrName = "sleep";
+		break;
+	      case 2:
+		instrName = "swi";
+		break;
+	      default:
+		instrName = "???";
+		state->flow=invalid_instr;
+		break;
+	      }
+	  }
+	  break;
+	  
+	  /* ARC Extension Library Instructions
+	     NOTE: We assume that extension codes are these instrs.  */
+	default:
+	  instrName = instruction_name (state,
+					state->_opcode,
+					FIELDC (state->words[0]),
+					& flags);
+	  if (!instrName)
 	    {
-	      mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS;
-	      ++syn;
-	      c = *syn;
+	      instrName = "???";
+	      state->flow = invalid_instr;
 	    }
-	  operand = arc_operands + arc_operand_map[c];
+	  if (flags & IGNORE_FIRST_OPD)
+	    ignoreFirstOpd = 1;
+	  break;
+	}
+      break;
 
-	  /* Extract the value from the instruction.  */
-	  opval = NULL;
-	  if (operand->extract)
+    case op_BC:
+      instrName = "b";  
+    case op_BLC:
+      if (!instrName)
+	instrName = "bl"; 
+    case op_LPC:
+      if (!instrName)
+	instrName = "lp"; 
+    case op_JC:
+      if (!instrName)
+	{
+	  if (BITS (state->words[0],9,9)) 
 	    {
-	      value = (*operand->extract) (insn, operand, mods,
-					   &opval, (int *) NULL);
+	      instrName = "jl";  
+	      is_linked = 1;
 	    }
-	  else
+	  else 
 	    {
-	      value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
-	      if ((operand->flags & ARC_OPERAND_SIGNED)
-		  && (value & (1 << (operand->bits - 1))))
-		value -= 1 << operand->bits;
-
-	      /* If this is a suffix operand, set `opval'.  */
-	      if (operand->flags & ARC_OPERAND_SUFFIX)
-		opval = arc_opcode_lookup_suffix (operand, value);
+	      instrName = "j";  
+	      is_linked = 0;
 	    }
+	}
+      condCodeIsPartOfName = 1;
+      decodingClass = ((state->_opcode == op_JC) ? 4 : 3);
+      state->isBranch = 1;
+      break;
+    
+    case op_ADD:
+    case op_ADC:
+    case op_AND:
+      repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
+      decodingClass = 0;
 
-	  /* Print the operand as directed by the flags.  */
-	  if (operand->flags & ARC_OPERAND_FAKE)
-	    ; /* nothing to do (??? at least not yet) */
-	  else if (operand->flags & ARC_OPERAND_SUFFIX)
-	    {
-	      /* Default suffixes aren't printed.  Fortunately, they all have
-		 zero values.  Also, zero values for boolean suffixes are
-		 represented by the absence of text.  */
+      switch (state->_opcode) 
+	{
+	case op_ADD:
+	  instrName = (repeatsOp ? "asl" : "add");
+	  break;
+	case op_ADC:
+	  instrName = (repeatsOp ? "rlc" : "adc");
+	  break;
+	case op_AND:
+	  instrName = (repeatsOp ? "mov" : "and");
+	  break;
+	}
+      break;
+      
+    case op_SUB: instrName = "sub";
+      break;
+    case op_SBC: instrName = "sbc";
+      break;
+    case op_OR:  instrName = "or";
+      break;
+    case op_BIC: instrName = "bic";
+      break;
 
-	      if (value != 0)
-		{
-		  /* ??? OPVAL should have a value.  If it doesn't just cope
-		     as we want disassembly to be reasonably robust.
-		     Also remember that several condition code values (16-31)
-		     aren't defined yet.  For these cases just print the
-		     number suitably decorated.  */
-		  if (opval)
-		    (*func) (stream, "%s%s",
-			     mods & ARC_MOD_DOT ? "." : "",
-			     opval->name);
-		  else
-		    (*func) (stream, "%s%c%d",
-			     mods & ARC_MOD_DOT ? "." : "",
-			     operand->fmt, value);
-		}
+    case op_XOR:
+      if (state->words[0] == 0x7fffffff)
+	{
+	  /* nop encoded as xor -1, -1, -1  */
+	  instrName = "nop";
+	  decodingClass = 9;
+	}
+      else 
+	instrName = "xor";
+      break;
+      
+    default:
+      instrName = instruction_name (state,state->_opcode,0,&flags);
+      /* if (instrName) printf("FLAGS=0x%x\n", flags);  */
+      if (!instrName)
+	{
+	  instrName = "???";
+	  state->flow=invalid_instr;
+	}
+      if (flags & IGNORE_FIRST_OPD)
+	ignoreFirstOpd = 1;
+      break;
+    }
+  
+  fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now.  */
+  flag = cond = is_shimm = is_limm = 0;
+  state->nullifyMode = BR_exec_when_no_jump;	/* 0  */
+  signExtend = addrWriteBack = directMem = 0;
+  usesAuxReg = 0;
+  
+  switch (decodingClass) 
+    {
+    case 0:
+      CHECK_FIELD_A ();
+      CHECK_FIELD_B ();
+      if (!repeatsOp)
+	CHECK_FIELD_C ();
+      CHECK_FLAG_COND_NULLIFY ();
+      
+      write_instr_name ();
+      if (!ignoreFirstOpd) 
+	{
+	  WRITE_FORMAT_x (A);
+	  WRITE_FORMAT_COMMA_x (B);
+	  if (!repeatsOp)
+	    WRITE_FORMAT_COMMA_x (C);
+	  WRITE_NOP_COMMENT ();
+	  my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+	}
+      else 
+	{
+	  WRITE_FORMAT_x (B);
+	  if (!repeatsOp)
+	    WRITE_FORMAT_COMMA_x (C);
+	  my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC);
+	}
+      write_comments ();
+      break;
+      
+    case 1:
+      CHECK_FIELD_A ();
+      CHECK_FIELD_B ();
+      CHECK_FLAG_COND_NULLIFY ();
+      
+      write_instr_name ();
+      if (!ignoreFirstOpd) 
+	{
+	  WRITE_FORMAT_x (A);
+	  WRITE_FORMAT_COMMA_x (B);
+	  WRITE_NOP_COMMENT ();
+	  my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); 
+	}
+      else 
+	{
+	  WRITE_FORMAT_x (B);
+	  my_sprintf (state, state->operandBuffer, formatString, fieldB); 
+	}
+      write_comments ();
+      break;
+      
+    case 2:
+      CHECK_FIELD_B ();
+      CHECK_FLAG_COND_NULLIFY ();
+      flag = 0; /* this is the FLAG instruction -- it's redundant  */
+      
+      write_instr_name ();
+      WRITE_FORMAT_x (B);
+      my_sprintf (state, state->operandBuffer, formatString, fieldB);
+      write_comments ();
+      break;
+      
+    case 3:
+      fieldA = BITS (state->words[0],7,26) << 2;
+      fieldA = (fieldA << 10) >> 10; /* make it signed  */
+      fieldA += addr + 4;
+      CHECK_FLAG_COND_NULLIFY ();
+      flag = 0;
+      
+      write_instr_name ();
+      /* This address could be a label we know. Convert it.  */
+      if (state->_opcode != op_LPC /* LP  */) 
+	{
+	add_target (fieldA); /* For debugger.  */
+	state->flow = state->_opcode == op_BLC /* BL  */
+	  ? direct_call
+	  : direct_jump;
+	/* indirect calls are achieved by "lr blink,[status];
+	   lr dest<- func addr; j [dest]"  */
+	}           		
+      
+      strcat (formatString, "%s"); /* address/label name */
+      my_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA));
+      write_comments ();
+      break;
+      
+    case 4:
+      /* For op_JC -- jump to address specified.
+	 Also covers jump and link--bit 9 of the instr. word
+	 selects whether linked, thus "is_linked" is set above.  */
+      fieldA = 0;
+      CHECK_FIELD_B ();
+      CHECK_FLAG_COND_NULLIFY ();
+      
+      if (!fieldBisReg) 
+	{
+	  fieldAisReg = 0;
+	  fieldA = (fieldB >> 25) & 0x7F; /* flags */
+	  fieldB = (fieldB & 0xFFFFFF) << 2;
+	  state->flow = is_linked ? direct_call : direct_jump;
+	  add_target (fieldB);
+	  /* screwy JLcc requires .jd mode to execute correctly
+	   * but we pretend it is .nd (no delay slot).  */
+	  if (is_linked && state->nullifyMode == BR_exec_when_jump)
+	    state->nullifyMode = BR_exec_when_no_jump;
+	}
+      else 
+	{
+	  state->flow = is_linked ? indirect_call : indirect_jump;
+	  /* We should also treat this as indirect call if NOT linked
+	   * but the preceding instruction was a "lr blink,[status]"
+	   * and we have a delay slot with "add blink,blink,2".
+	   * For now we can't detect such.  */
+	  state->register_for_indirect_jump = fieldB;
+	}
+      
+      write_instr_name ();
+      strcat (formatString, 
+	      IS_REG (B) ? "[%r]" : "%s"); /* address/label name  */
+      if (fieldA != 0) 
+	{
+	  fieldAisReg = 0;
+	  WRITE_FORMAT_COMMA_x (A);
+	}
+      if (IS_REG (B))
+	my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
+      else
+	my_sprintf (state, state->operandBuffer, formatString, 
+		    post_address (state, fieldB), fieldA);
+      write_comments ();
+      break;
+      
+    case 5:
+      /* LD instruction.
+	 B and C can be regs, or one (both?) can be limm.  */
+      CHECK_FIELD_A ();
+      CHECK_FIELD_B ();
+      CHECK_FIELD_C ();
+      if (dbg)
+	printf ("5:b reg %d %d c reg %d %d  \n",
+		fieldBisReg,fieldB,fieldCisReg,fieldC);
+      state->_offset = 0;
+      state->_ea_present = 1;
+      if (fieldBisReg)
+	state->ea_reg1 = fieldB;
+      else
+	state->_offset += fieldB;
+      if (fieldCisReg)
+	state->ea_reg2 = fieldC;
+      else
+	state->_offset += fieldC;
+      state->_mem_load = 1;
+      
+      directMem     = BIT (state->words[0],5);
+      addrWriteBack = BIT (state->words[0],3);
+      signExtend    = BIT (state->words[0],0);
+      
+      write_instr_name ();
+      WRITE_FORMAT_x_COMMA_LB(A);
+      if (fieldBisReg || fieldB != 0)
+	WRITE_FORMAT_x_COMMA (B);
+      else
+	fieldB = fieldC;
+      
+      WRITE_FORMAT_x_RB (C);
+      my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+      write_comments ();
+      break;
+      
+    case 6:
+      /* LD instruction.  */
+      CHECK_FIELD_B ();
+      CHECK_FIELD_A ();
+      fieldC = FIELDD (state->words[0]);
+      
+      if (dbg)
+	printf ("6:b reg %d %d c 0x%x  \n",
+		fieldBisReg, fieldB, fieldC);
+      state->_ea_present = 1;
+      state->_offset = fieldC;
+      state->_mem_load = 1;
+      if (fieldBisReg)
+	state->ea_reg1 = fieldB;
+      /* field B is either a shimm (same as fieldC) or limm (different!)
+	 Say ea is not present, so only one of us will do the name lookup.  */
+      else
+	state->_offset += fieldB, state->_ea_present = 0;
+      
+      directMem     = BIT (state->words[0],14);
+      addrWriteBack = BIT (state->words[0],12);
+      signExtend    = BIT (state->words[0],9);
+      
+      write_instr_name ();
+      WRITE_FORMAT_x_COMMA_LB (A);
+      if (!fieldBisReg) 
+	{
+	  fieldB = state->_offset;
+	  WRITE_FORMAT_x_RB (B);
+	}
+      else 
+	{
+	  WRITE_FORMAT_x (B);
+	  if (fieldC != 0 && !BIT (state->words[0],13)) 
+	    {
+	      fieldCisReg = 0;
+	      WRITE_FORMAT_COMMA_x_RB (C);
 	    }
-	  else if (operand->flags & ARC_OPERAND_RELATIVE_BRANCH)
-	    (*info->print_address_func) (pc + 4 + value, info);
-	  /* ??? Not all cases of this are currently caught.  */
-	  else if (operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH)
-	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
-	  else if (operand->flags & ARC_OPERAND_ADDRESS)
-	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
-	  else if (opval)
-	    /* Note that this case catches both normal and auxiliary regs.  */
-	    (*func) (stream, "%s", opval->name);
 	  else
-	    (*func) (stream, "%ld", value);
+	    WRITE_FORMAT_RB ();
 	}
-
-      /* We have found and printed an instruction; return.  */
-      return got_limm_p ? 8 : 4;
+      my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+      write_comments ();
+      break;
+      
+    case 7:
+      /* ST instruction.  */
+      CHECK_FIELD_B();
+      CHECK_FIELD_C();
+      fieldA = FIELDD(state->words[0]); /* shimm  */
+      
+      /* [B,A offset]  */
+      if (dbg) printf("7:b reg %d %x off %x\n",
+				 fieldBisReg,fieldB,fieldA);
+      state->_ea_present = 1;
+      state->_offset = fieldA;
+      if (fieldBisReg)
+	state->ea_reg1 = fieldB;
+      /* field B is either a shimm (same as fieldA) or limm (different!) 
+	 Say ea is not present, so only one of us will do the name lookup.
+	 (for is_limm we do the name translation here).  */
+      else 
+	state->_offset += fieldB, state->_ea_present = 0;
+      
+      directMem     = BIT(state->words[0],26);
+      addrWriteBack = BIT(state->words[0],24);
+      
+      write_instr_name();
+      WRITE_FORMAT_x_COMMA_LB(C);
+	    
+      if (!fieldBisReg) 
+	{
+	  fieldB = state->_offset;
+	  WRITE_FORMAT_x_RB(B);
+	}
+      else 
+	{
+	  WRITE_FORMAT_x(B);
+	  if (fieldBisReg && fieldA != 0) 
+	    {
+	      fieldAisReg = 0;
+	      WRITE_FORMAT_COMMA_x_RB(A);
+	    }
+	  else
+	    WRITE_FORMAT_RB();
+	}
+      my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
+      write_comments2(fieldA);
+      break;
+    case 8:
+      /* SR instruction  */
+      CHECK_FIELD_B();
+      CHECK_FIELD_C();
+      
+      write_instr_name();
+      WRITE_FORMAT_x_COMMA_LB(C);
+      /* Try to print B as an aux reg if it is not a core reg.  */
+      usesAuxReg = 1;
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_RB();
+      my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
+      write_comments();
+      break;
+      
+    case 9:
+      write_instr_name();
+      state->operandBuffer[0] = '\0';
+      break;
+      
+    case 10:
+      /* LR instruction */
+      CHECK_FIELD_A();
+      CHECK_FIELD_B();
+      
+      write_instr_name();
+      WRITE_FORMAT_x_COMMA_LB(A);
+      /* Try to print B as an aux reg if it is not a core reg. */
+      usesAuxReg = 1;
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_RB();
+      my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
+      write_comments();
+      break;
+      
+    case 11:
+      CHECK_COND();
+      write_instr_name();
+      state->operandBuffer[0] = '\0';
+      break;
+      
+    default:
+      mwerror (state, "Bad decoding class in ARC disassembler");
+      break;
     }
+  
+  state->_cond = cond;
+  return state->instructionLen = offset;
+}
+
 
-  (*func) (stream, _("*unknown*"));
-  return 4;
+/* Returns the name the user specified core extension register.  */
+static const char *
+_coreRegName(arg, regval)
+     void * arg ATTRIBUTE_UNUSED;
+     int regval;
+{
+  return arcExtMap_coreRegName (regval);
 }
 
-/* Given MACH, one of bfd_mach_arc_xxx, return the print_insn function to use.
-   This does things a non-standard way (the "standard" way would be to copy
-   this code into disassemble.c).  Since there are more than a couple of
-   variants, hiding all this crud here seems cleaner.  */
+/* Returns the name the user specified AUX extension register.  */
+static const char *
+_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
+{
+    return arcExtMap_auxRegName(regval);
+}
 
-disassembler_ftype
-arc_get_disassembler (mach, big_p)
-     int mach;
-     int big_p;
+
+/* Returns the name the user specified condition code name.  */
+static const char *
+_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
 {
-  switch (mach)
-    {
-    case bfd_mach_arc_base:
-      return big_p ? print_insn_arc_base_big : print_insn_arc_base_little;
-    }
-  return print_insn_arc_base_little;
+    return arcExtMap_condCodeName(regval);
 }
 
-static int
-print_insn_arc_base_little (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
+/* Returns the name the user specified extension instruction.  */
+static const char *
+_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
 {
-  return print_insn (pc, info, bfd_mach_arc_base, 0);
+    return arcExtMap_instName(majop, minop, flags);
 }
 
+/* Decode an instruction returning the size of the instruction
+   in bytes or zero if unrecognized.  */
 static int
-print_insn_arc_base_big (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
+decodeInstr (address, info)
+     bfd_vma            address; /* Address of this instruction.  */
+     disassemble_info * info;
+{
+  int status;
+  bfd_byte buffer[4];
+  struct arcDisState s;	/* ARC Disassembler state  */
+  void *stream = info->stream; /* output stream  */
+  fprintf_ftype func = info->fprintf_func; 
+  int bytes;
+  
+  memset (&s, 0, sizeof(struct arcDisState));
+  
+  /* read first instruction  */
+  status = (*info->read_memory_func) (address, buffer, 4, info);
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, address, info);
+      return 0;
+    }
+  if (info->endian == BFD_ENDIAN_LITTLE)
+    s.words[0] = bfd_getl32(buffer);
+  else
+    s.words[0] = bfd_getb32(buffer);
+  /* always read second word in case of limm  */
+
+  /* we ignore the result since last insn may not have a limm  */
+  status = (*info->read_memory_func) (address + 4, buffer, 4, info);
+  if (info->endian == BFD_ENDIAN_LITTLE)
+    s.words[1] = bfd_getl32(buffer);
+  else
+    s.words[1] = bfd_getb32(buffer);
+
+  s._this = &s;
+  s.coreRegName = _coreRegName;
+  s.auxRegName = _auxRegName;
+  s.condCodeName = _condCodeName;
+  s.instName = _instName;
+
+  /* disassemble  */
+  bytes = dsmOneArcInst(address, (void *)&s);
+
+  /* display the disassembly instruction  */
+  (*func) (stream, "%08x ", s.words[0]);
+  (*func) (stream, "    ");
+  
+  (*func) (stream, "%-10s ", s.instrBuffer);
+  
+  if (__TRANSLATION_REQUIRED(s))
+    {
+      bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
+      (*info->print_address_func) ((bfd_vma) addr, info);
+      (*func) (stream, "\n");
+    }
+  else
+    (*func) (stream, "%s",s.operandBuffer);
+  return s.instructionLen;
+}
+
+/* Return the print_insn function to use.
+   Side effect: load (possibly empty) extension section  */
+
+disassembler_ftype
+arc_get_disassembler (void *ptr)
 {
-  return print_insn (pc, info, bfd_mach_arc_base, 1);
+  if (ptr)
+    build_ARC_extmap (ptr);
+  return decodeInstr;
 }
diff --git a/opcodes/arc-dis.h b/opcodes/arc-dis.h
new file mode 100644
index 0000000..992510c
--- /dev/null
+++ b/opcodes/arc-dis.h
@@ -0,0 +1,80 @@
+/* Disassembler structures definitions for the ARC.
+   Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc. 
+   Contributed by Doug Evans (dje@cygnus.com).
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef ARCDIS_H
+#define ARCDIS_H
+
+enum 
+{
+  BR_exec_when_no_jump,
+  BR_exec_always,
+  BR_exec_when_jump
+};
+
+enum Flow 
+{
+  noflow,
+  direct_jump,
+  direct_call,
+  indirect_jump,
+  indirect_call,
+  invalid_instr
+};
+
+enum { no_reg = 99 };
+enum { allOperandsSize = 256 };
+
+struct arcDisState 
+{
+  void *_this;
+  int instructionLen;
+  void (*err)(void*, const char*);
+  const char *(*coreRegName)(void*, int);
+  const char *(*auxRegName)(void*, int);
+  const char *(*condCodeName)(void*, int);
+  const char *(*instName)(void*, int, int, int*);
+  
+  unsigned char* instruction;
+  unsigned index;
+  const char *comm[6]; /* instr name, cond, NOP, 3 operands  */
+  int opWidth;
+  int targets[4];
+  int addresses[4];
+  /* Set as a side-effect of calling the disassembler.
+     Used only by the debugger.  */
+  enum Flow flow;
+  int register_for_indirect_jump;
+  int ea_reg1, ea_reg2, _offset;
+  int _cond, _opcode;
+  unsigned long words[2];
+  char *commentBuffer;
+  char instrBuffer[40];
+  char operandBuffer[allOperandsSize];
+  char _ea_present;
+  char _mem_load;
+  char _load_len;
+  char nullifyMode;
+  unsigned char commNum;
+  unsigned char isBranch;
+  unsigned char tcnt;
+  unsigned char acnt;
+};
+
+#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0)
+
+#endif
diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c
new file mode 100644
index 0000000..0b10677
--- /dev/null
+++ b/opcodes/arc-ext.c
@@ -0,0 +1,259 @@
+/* ARC target-dependent stuff. Extension structure access functions 
+   Copyright (C) 1995, 1997, 2000 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "bfd.h"
+#include "arc-ext.h"
+#include "libiberty.h"
+
+/* Extension structure  */
+static struct arcExtMap arc_extension_map;
+
+/* Get the name of an extension instruction.  */
+
+const char *
+arcExtMap_instName(int opcode, int minor, int *flags) 
+{
+    if (opcode == 3) 
+      {
+	/* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi  */
+	if (minor < 0x09 || minor == 0x3f)
+	  return 0;
+	else
+	  opcode = 0x1f - 0x10 + minor - 0x09 + 1;
+      }
+    else
+      if (opcode < 0x10)
+	return 0;
+    else
+      opcode -= 0x10;
+    if (!arc_extension_map.instructions[opcode])
+      return 0;
+    *flags = arc_extension_map.instructions[opcode]->flags;
+    return arc_extension_map.instructions[opcode]->name;
+}
+
+/* Get the name of an extension core register.  */
+
+const char *
+arcExtMap_coreRegName(int value) 
+{
+  if (value < 32)
+    return 0;
+  return (const char *) arc_extension_map.coreRegisters[value-32];
+}
+
+/* Get the name of an extension condition code.  */
+
+const char *
+arcExtMap_condCodeName(int value) 
+{
+  if (value < 16)
+    return 0;
+  return (const char *) arc_extension_map.condCodes[value-16];
+}
+
+/* Get the name of an extension aux register.  */
+
+const char *
+arcExtMap_auxRegName(long address)
+{
+  /* walk the list of aux reg names and find the name  */
+  struct ExtAuxRegister *r;
+
+  for (r = arc_extension_map.auxRegisters; r; r = r->next) {
+    if (r->address == address)
+      return (const char *) r->name;
+  }
+  return 0;
+}
+
+/* Recursively free auxilliary register strcture pointers until
+   the list is empty.  */
+
+static void 
+clean_aux_registers(struct ExtAuxRegister *r)
+{
+  if (r -> next)
+    {
+      clean_aux_registers( r->next);
+      free(r -> name);
+      free(r -> next);
+      r ->next = NULL;
+    }
+  else 
+    free(r -> name);
+}
+	      
+/* Free memory that has been allocated for the extensions.  */
+
+static void 
+cleanup_ext_map(void) 
+{
+  struct ExtAuxRegister *r;
+  struct ExtInstruction *insn;
+  int i;
+
+  /* clean aux reg structure  */
+  r = arc_extension_map.auxRegisters;
+  if (r) 
+    {
+      (clean_aux_registers(r));
+      free(r);
+    }
+  
+  /* clean instructions  */
+  for (i = 0; i < NUM_EXT_INST; i++) 
+    {
+      insn = arc_extension_map.instructions[i];
+      if (insn)
+	free(insn->name);
+    }
+  
+  /* clean core reg struct  */
+  for (i = 0; i < NUM_EXT_CORE; i++) 
+    {
+      if (arc_extension_map.coreRegisters[i])
+	free(arc_extension_map.coreRegisters[i]);
+    }
+  
+  for (i = 0; i < NUM_EXT_COND; i++) {
+    if (arc_extension_map.condCodes[i])
+      free(arc_extension_map.condCodes[i]);
+  }
+  
+  memset(&arc_extension_map, 0, sizeof(struct arcExtMap));  
+}
+
+int 
+arcExtMap_add(void *base, unsigned long length) 
+{
+  unsigned char *block = base;
+  unsigned char *p = block;
+  
+  /* Clean up and reset everything if needed.  */
+  cleanup_ext_map();
+
+  while (p && p < (block + length)) 
+    {
+      /* p[0] == length of record
+	 p[1] == type of record
+	 For instructions:
+	   p[2]  = opcode
+	   p[3]  = minor opcode (if opcode == 3)
+	   p[4]  = flags
+	   p[5]+ = name
+	 For core regs and condition codes:
+	   p[2]  = value
+	   p[3]+ = name
+	 For aux regs:
+	   p[2..5] = value
+	   p[6]+   = name
+	 (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5])  */
+
+      if (p[0] == 0)
+	return -1;
+      
+      switch (p[1])
+	{
+	case EXT_INSTRUCTION:
+	  {
+	    char opcode = p[2];
+	    char minor  = p[3];
+	    char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char));
+	    struct ExtInstruction * insn = 
+	      (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction));
+	    
+	    if (opcode==3)
+	      opcode = 0x1f - 0x10 + minor - 0x09 + 1;
+	    else
+	      opcode -= 0x10;
+	    insn -> flags = (char) *(p+4);
+	    strcpy(insn_name, (p+5));
+	    insn -> name = insn_name;
+	    arc_extension_map.instructions[(int) opcode] = insn;
+	  }
+	  break;
+	
+	case EXT_CORE_REGISTER: 
+	  {
+	    char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char));
+
+	    strcpy(core_name, (p+3));
+	    arc_extension_map.coreRegisters[p[2]-32] = core_name;
+	  }
+	  break;
+	  
+	case EXT_COND_CODE: 
+	  {
+	    char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char));
+	    strcpy(cc_name, (p+3));
+	    arc_extension_map.condCodes[p[2]-16] = cc_name;
+	  }	
+	  break;
+	  
+	case EXT_AUX_REGISTER: 
+	  {
+	    /* trickier -- need to store linked list to these  */
+	    struct ExtAuxRegister *newAuxRegister = 
+	      (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister));
+	    char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char));
+
+	    strcpy (aux_name, (p+6));
+	    newAuxRegister->name = aux_name;
+	    newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8  | p[5];
+	    newAuxRegister->next = arc_extension_map.auxRegisters;
+	    arc_extension_map.auxRegisters = newAuxRegister;
+	  }
+	  break;
+	  
+	default:
+	  return -1;
+	  
+	}
+      p += p[0]; /* move to next record  */
+    }
+  
+  return 0;
+}
+
+/* Load hw extension descibed in .extArcMap ELF section.  */
+
+void
+build_ARC_extmap (text_bfd)
+  bfd *text_bfd;
+{
+  char *arcExtMap;
+  bfd_size_type count;
+  asection *p;
+
+  for (p = text_bfd->sections; p != NULL; p = p->next)
+    if (!strcmp (p->name, ".arcextmap"))
+      {
+        count = p->_raw_size;
+        arcExtMap = (char *) xmalloc (count);
+        if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count))
+          {
+            arcExtMap_add ((PTR) arcExtMap, count);
+            break;
+          }
+        free ((PTR) arcExtMap);
+      }
+}
diff --git a/opcodes/arc-ext.h b/opcodes/arc-ext.h
new file mode 100644
index 0000000..aca9213
--- /dev/null
+++ b/opcodes/arc-ext.h
@@ -0,0 +1,62 @@
+/* ARC target-dependent stuff. Extension data structures.
+   Copyright (C) 1995, 1997, 2000 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef ARCEXT_H
+#define ARCEXT_H
+
+enum {EXT_INSTRUCTION   = 0};
+enum {EXT_CORE_REGISTER = 1};
+enum {EXT_AUX_REGISTER  = 2};
+enum {EXT_COND_CODE     = 3};
+
+enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)};
+enum {NUM_EXT_CORE = 59-32+1};
+enum {NUM_EXT_COND = 0x1f-0x10+1};
+
+struct ExtInstruction 
+{
+  char flags;
+  char *name;
+}; 
+
+struct ExtAuxRegister 
+{
+  long address;
+  char *name;
+  struct ExtAuxRegister *next; 
+};
+
+struct arcExtMap 
+{
+  struct ExtAuxRegister *auxRegisters;
+  struct ExtInstruction *instructions[NUM_EXT_INST];
+  unsigned char *coreRegisters[NUM_EXT_CORE];
+  unsigned char *condCodes[NUM_EXT_COND];
+};
+
+extern int arcExtMap_add(void*, unsigned long);
+extern const char *arcExtMap_coreRegName(int);
+extern const char *arcExtMap_auxRegName(long);
+extern const char *arcExtMap_condCodeName(int);
+extern const char *arcExtMap_instName(int, int, int*);
+extern void build_ARC_extmap(bfd *);
+
+#define IGNORE_FIRST_OPD 1
+
+#endif
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index f17ffc0..12ee62a 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1,5 +1,5 @@
 /* Opcode table for the ARC.
-   Copyright (c) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1997, 1998, 2000 Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
    
    This program is free software; you can redistribute it and/or modify
@@ -13,17 +13,12 @@
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include <stdio.h>
-#include "sysdep.h"
+#include "ansidecl.h"
 #include "opcode/arc.h"
-#include "opintl.h"
-
-#ifndef NULL
-#define NULL 0
-#endif
 
 #define INSERT_FN(fn) \
 static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
@@ -36,22 +31,43 @@ static long fn PARAMS ((arc_insn *, const struct arc_operand *, \
 INSERT_FN (insert_reg);
 INSERT_FN (insert_shimmfinish);
 INSERT_FN (insert_limmfinish);
-INSERT_FN (insert_shimmoffset);
-INSERT_FN (insert_shimmzero);
+INSERT_FN (insert_offset);
+INSERT_FN (insert_base);
+INSERT_FN (insert_st_syntax);
+INSERT_FN (insert_ld_syntax);
+INSERT_FN (insert_addr_wb);
 INSERT_FN (insert_flag);
+INSERT_FN (insert_nullify);
 INSERT_FN (insert_flagfinish);
 INSERT_FN (insert_cond);
 INSERT_FN (insert_forcelimm);
 INSERT_FN (insert_reladdr);
 INSERT_FN (insert_absaddr);
+INSERT_FN (insert_jumpflags);
 INSERT_FN (insert_unopmacro);
 
 EXTRACT_FN (extract_reg);
+EXTRACT_FN (extract_ld_offset);
+EXTRACT_FN (extract_ld_syntax);
+EXTRACT_FN (extract_st_offset);
+EXTRACT_FN (extract_st_syntax);
 EXTRACT_FN (extract_flag);
 EXTRACT_FN (extract_cond);
 EXTRACT_FN (extract_reladdr);
+EXTRACT_FN (extract_jumpflags);
 EXTRACT_FN (extract_unopmacro);
 
+enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM};
+
+#define OPERANDS 3
+
+enum operand ls_operand[OPERANDS];
+
+#define LS_VALUE  0
+#define LS_DEST   0
+#define LS_BASE   1
+#define LS_OFFSET 2
+
 /* Various types of ARC operands, including insn suffixes.  */
 
 /* Insn format values:
@@ -61,8 +77,13 @@ EXTRACT_FN (extract_unopmacro);
    'c'	REGC		register C field
    'S'	SHIMMFINISH	finish inserting a shimm value
    'L'	LIMMFINISH	finish inserting a limm value
-   'd'	SHIMMOFFSET	shimm offset in ld,st insns
-   '0'	SHIMMZERO	0 shimm value in ld,st insns
+   'o'	OFFSET		offset in st insns
+   'O'	OFFSET		offset in ld insns
+   '0'	SYNTAX_ST_NE	enforce store insn syntax, no errors
+   '1'	SYNTAX_LD_NE	enforce load insn syntax, no errors
+   '2'  SYNTAX_ST       enforce store insn syntax, errors, last pattern only
+   '3'  SYNTAX_LD       enforce load insn syntax, errors, last pattern only
+   's'  BASE            base in st insn
    'f'	FLAG		F flag
    'F'	FLAGFINISH	finish inserting the F flag
    'G'	FLAGINSN	insert F flag in "flag" insn
@@ -71,6 +92,7 @@ EXTRACT_FN (extract_unopmacro);
    'Q'	FORCELIMM	set `cond_p' to 1 to ensure a constant is a limm
    'B'	BRANCH		branch address (22 bit pc relative)
    'J'	JUMP		jump address (26 bit absolute)
+   'j'  JUMPFLAGS       optional high order bits of 'J'
    'z'	SIZE1		size field in ld a,[b,c]
    'Z'	SIZE10		size field in ld a,[b,shimm]
    'y'	SIZE22		size field in st c,[b,shimm]
@@ -92,28 +114,27 @@ EXTRACT_FN (extract_unopmacro);
 
    Fields are:
 
-   CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN
-*/
+   CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN  */
 
 const struct arc_operand arc_operands[] =
 {
-/* place holder (??? not sure if needed) */
+/* place holder (??? not sure if needed).  */
 #define UNUSED 0
-  { 0 },
+  { 0, 0, 0, 0, 0, 0 },
 
-/* register A or shimm/limm indicator */
+/* register A or shimm/limm indicator.  */
 #define REGA (UNUSED + 1)
-  { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
+  { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
 
-/* register B or shimm/limm indicator */
+/* register B or shimm/limm indicator.  */
 #define REGB (REGA + 1)
-  { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
+  { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
 
-/* register C or shimm/limm indicator */
+/* register C or shimm/limm indicator.  */
 #define REGC (REGB + 1)
-  { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
+  { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
 
-/* fake operand used to insert shimm value into most instructions */
+/* fake operand used to insert shimm value into most instructions.  */
 #define SHIMMFINISH (REGC + 1)
   { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
 
@@ -121,123 +142,141 @@ const struct arc_operand arc_operands[] =
 #define LIMMFINISH (SHIMMFINISH + 1)
   { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
 
-/* shimm operand when there is no reg indicator (ld,st) */
-#define SHIMMOFFSET (LIMMFINISH + 1)
-  { 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 },
+/* shimm operand when there is no reg indicator (st).  */
+#define ST_OFFSET (LIMMFINISH + 1)
+  { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset },
+
+/* shimm operand when there is no reg indicator (ld).  */
+#define LD_OFFSET (ST_OFFSET + 1)
+  { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset },
+
+/* operand for base.  */
+#define BASE (LD_OFFSET + 1)
+  { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg},
 
-/* 0 shimm operand for ld,st insns */
-#define SHIMMZERO (SHIMMOFFSET + 1)
-  { '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 },
+/* 0 enforce syntax for st insns.  */
+#define SYNTAX_ST_NE (BASE + 1)
+  { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax },
 
-/* flag update bit (insertion is defered until we know how) */
-#define FLAG (SHIMMZERO + 1)
+/* 1 enforce syntax for ld insns.  */
+#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1)
+  { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax },
+
+/* 0 enforce syntax for st insns.  */
+#define SYNTAX_ST (SYNTAX_LD_NE + 1)
+  { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax },
+
+/* 0 enforce syntax for ld insns.  */
+#define SYNTAX_LD (SYNTAX_ST + 1)
+  { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax },
+
+/* flag update bit (insertion is defered until we know how).  */
+#define FLAG (SYNTAX_LD + 1)
   { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
 
-/* fake utility operand to finish 'f' suffix handling */
+/* fake utility operand to finish 'f' suffix handling.  */
 #define FLAGFINISH (FLAG + 1)
   { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
 
-/* fake utility operand to set the 'f' flag for the "flag" insn */
+/* fake utility operand to set the 'f' flag for the "flag" insn.  */
 #define FLAGINSN (FLAGFINISH + 1)
   { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
 
-/* branch delay types */
+/* branch delay types.  */
 #define DELAY (FLAGINSN + 1)
-  { 'n', 2, 5, ARC_OPERAND_SUFFIX },
+  { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 },
 
-/* conditions */
+/* conditions.  */
 #define COND (DELAY + 1)
   { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
 
-/* set `cond_p' to 1 to ensure a constant is treated as a limm */
+/* set `cond_p' to 1 to ensure a constant is treated as a limm.  */
 #define FORCELIMM (COND + 1)
-  { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm },
+  { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 },
 
-/* branch address; b, bl, and lp insns */
+/* branch address; b, bl, and lp insns.  */
 #define BRANCH (FORCELIMM + 1)
-  { 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr },
+  { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr },
 
 /* jump address; j insn (this is basically the same as 'L' except that the
-   value is right shifted by 2) */
+   value is right shifted by 2).  */
 #define JUMP (BRANCH + 1)
-  { 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr },
+  { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 },
+
+/* jump flags; j{,l} insn value or'ed into 'J' addr for flag values.  */
+#define JUMPFLAGS (JUMP + 1)
+  { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags },
 
-/* size field, stored in bit 1,2 */
-#define SIZE1 (JUMP + 1)
-  { 'z', 2, 1, ARC_OPERAND_SUFFIX },
+/* size field, stored in bit 1,2.  */
+#define SIZE1 (JUMPFLAGS + 1)
+  { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* size field, stored in bit 10,11 */
+/* size field, stored in bit 10,11.  */
 #define SIZE10 (SIZE1 + 1)
-  { 'Z', 2, 10, ARC_OPERAND_SUFFIX, },
+  { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* size field, stored in bit 22,23 */
+/* size field, stored in bit 22,23.  */
 #define SIZE22 (SIZE10 + 1)
-  { 'y', 2, 22, ARC_OPERAND_SUFFIX, },
+  { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* sign extend field, stored in bit 0 */
+/* sign extend field, stored in bit 0.  */
 #define SIGN0 (SIZE22 + 1)
-  { 'x', 1, 0, ARC_OPERAND_SUFFIX },
+  { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* sign extend field, stored in bit 9 */
+/* sign extend field, stored in bit 9.  */
 #define SIGN9 (SIGN0 + 1)
-  { 'X', 1, 9, ARC_OPERAND_SUFFIX },
+  { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* address write back, stored in bit 3 */
+/* address write back, stored in bit 3.  */
 #define ADDRESS3 (SIGN9 + 1)
-  { 'w', 1, 3, ARC_OPERAND_SUFFIX },
+  { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
 
-/* address write back, stored in bit 12 */
+/* address write back, stored in bit 12.  */
 #define ADDRESS12 (ADDRESS3 + 1)
-  { 'W', 1, 12, ARC_OPERAND_SUFFIX },
+  { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
 
-/* address write back, stored in bit 24 */
+/* address write back, stored in bit 24.  */
 #define ADDRESS24 (ADDRESS12 + 1)
-  { 'v', 1, 24, ARC_OPERAND_SUFFIX },
+  { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
 
-/* cache bypass, stored in bit 5 */
+/* cache bypass, stored in bit 5.  */
 #define CACHEBYPASS5 (ADDRESS24 + 1)
-  { 'e', 1, 5, ARC_OPERAND_SUFFIX },
+  { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* cache bypass, stored in bit 14 */
+/* cache bypass, stored in bit 14.  */
 #define CACHEBYPASS14 (CACHEBYPASS5 + 1)
-  { 'E', 1, 14, ARC_OPERAND_SUFFIX },
+  { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* cache bypass, stored in bit 26 */
+/* cache bypass, stored in bit 26.  */
 #define CACHEBYPASS26 (CACHEBYPASS14 + 1)
-  { 'D', 1, 26, ARC_OPERAND_SUFFIX },
+  { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 },
 
-/* unop macro, used to copy REGB to REGC */
+/* unop macro, used to copy REGB to REGC.  */
 #define UNOPMACRO (CACHEBYPASS26 + 1)
   { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
 
 /* '.' modifier ('.' required).  */
 #define MODDOT (UNOPMACRO + 1)
-  { '.', 1, 0, ARC_MOD_DOT },
+  { '.', 1, 0, ARC_MOD_DOT, 0, 0 },
 
 /* Dummy 'r' modifier for the register table.
    It's called a "dummy" because there's no point in inserting an 'r' into all
    the %a/%b/%c occurrences in the insn table.  */
 #define REG (MODDOT + 1)
-  { 'r', 6, 0, ARC_MOD_REG },
+  { 'r', 6, 0, ARC_MOD_REG, 0, 0 },
 
 /* Known auxiliary register modifier (stored in shimm field).  */
 #define AUXREG (REG + 1)
-  { 'A', 9, 0, ARC_MOD_AUXREG },
+  { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 },
 
-/* end of list place holder */
-  { 0 }
+/* end of list place holder.  */
+  { 0, 0, 0, 0, 0, 0 }
 };
 
 /* Given a format letter, yields the index into `arc_operands'.
    eg: arc_operand_map['a'] = REGA.  */
 unsigned char arc_operand_map[256];
 
-#define I(x) (((x) & 31) << 27)
-#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
-#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
-#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
-#define R(x,b,m) (((x) & (m)) << (b))	/* value X, mask M, at bit B */
-
 /* ARC instructions.
 
    Longer versions of insns must appear before shorter ones (if gas sees
@@ -246,110 +285,141 @@ unsigned char arc_operand_map[256];
 
    Instructions that are really macros based on other insns must appear
    before the real insn so they're chosen when disassembling.  Eg: The `mov'
-   insn is really the `and' insn.
-
-   This table is best viewed on a wide screen (161 columns).  I'd prefer to
-   keep it this way.  The rest of the file, however, should be viewable on an
-   80 column terminal.  */
-
-/* ??? This table also includes macros: asl, lsl, and mov.  The ppc port has
-   a more general facility for dealing with macros which could be used if
-   we need to.  */
-
-/* This table can't be `const' because members `next_asm' and `next_dis' are
-   computed at run-time.  We could split this into two, but that doesn't seem
-   worth it.  */
+   insn is really the `and' insn.  */
 
-struct arc_opcode arc_opcodes[] = {
+struct arc_opcode arc_opcodes[] =
+{
+  /* Base case instruction set (core versions 5-8)  */
 
-  /* Macros appear first.  */
   /* "mov" is really an "and".  */
-  { "mov%.q%.f %a,%b%F%S%L%U",		I(-1),		I(12) },
+  { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 },
   /* "asl" is really an "add".  */
-  { "asl%.q%.f %a,%b%F%S%L%U",		I(-1),		I(8) },
+  { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
   /* "lsl" is really an "add".  */
-  { "lsl%.q%.f %a,%b%F%S%L%U",		I(-1),		I(8) },
+  { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
   /* "nop" is really an "xor".  */
-  { "nop",				0xffffffff,	0x7fffffff },
+  { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 },
   /* "rlc" is really an "adc".  */
-  { "rlc%.q%.f %a,%b%F%S%L%U",		I(-1),		I(9) },
-
-  /* The rest of these needn't be sorted, but it helps to find them if they are.  */
-  { "adc%.q%.f %a,%b,%c%F%S%L",		I(-1),		I(9) },
-  { "add%.q%.f %a,%b,%c%F%S%L",		I(-1),		I(8) },
-  { "and%.q%.f %a,%b,%c%F%S%L",		I(-1),		I(12) },
-  { "asr%.q%.f %a,%b%F%S%L",		I(-1)+C(-1),	I(3)+C(1) },
-  { "bic%.q%.f %a,%b,%c%F%S%L",		I(-1),		I(14) },
-  { "b%q%.n %B",			I(-1),		I(4),		ARC_OPCODE_COND_BRANCH },
-  { "bl%q%.n %B",			I(-1),		I(5),		ARC_OPCODE_COND_BRANCH },
-  { "extb%.q%.f %a,%b%F%S%L",		I(-1)+C(-1),	I(3)+C(7) },
-  { "extw%.q%.f %a,%b%F%S%L",		I(-1)+C(-1),	I(3)+C(8) },
-  { "flag%.q %b%G%S%L",			I(-1)+A(-1)+C(-1),		I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) },
-  /* %Q: force cond_p=1 --> no shimm values */
-  /* ??? This insn allows an optional flags spec.  */
-  { "j%q%Q%.n%.f %b%J",			I(-1)+A(-1)+C(-1)+R(-1,7,1),	I(7)+A(0)+C(0)+R(0,7,1) },
-  /* Put opcode 1 ld insns first so shimm gets prefered over limm.  */
-  /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed.  */
-  { "ld%Z%.X%.W%.E %0%a,[%b]%L",	I(-1)+R(-1,13,1)+R(-1,0,511),	I(1)+R(0,13,1)+R(0,0,511) },
-  { "ld%Z%.X%.W%.E %a,[%b,%d]%S%L",	I(-1)+R(-1,13,1),		I(1)+R(0,13,1) },
-  { "ld%z%.x%.w%.e%Q %a,[%b,%c]%L",	I(-1)+R(-1,4,1)+R(-1,6,7),	I(0)+R(0,4,1)+R(0,6,7) },
-  { "lp%q%.n %B",			I(-1),		I(6), },
-  { "lr %a,[%Ab]%S%L",			I(-1)+C(-1),	I(1)+C(0x10) },
-  { "lsr%.q%.f %a,%b%F%S%L",		I(-1)+C(-1),	I(3)+C(2) },
-  { "or%.q%.f %a,%b,%c%F%S%L",		I(-1),		I(13) },
-  { "ror%.q%.f %a,%b%F%S%L",		I(-1)+C(-1),	I(3)+C(3) },
-  { "rrc%.q%.f %a,%b%F%S%L",		I(-1)+C(-1),	I(3)+C(4) },
-  { "sbc%.q%.f %a,%b,%c%F%S%L",		I(-1),		I(11) },
-  { "sexb%.q%.f %a,%b%F%S%L",		I(-1)+C(-1),	I(3)+C(5) },
-  { "sexw%.q%.f %a,%b%F%S%L",		I(-1)+C(-1),	I(3)+C(6) },
-  { "sr %c,[%Ab]%S%L",			I(-1)+A(-1),	I(2)+A(0x10) },
-  /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed.  */
-  { "st%y%.v%.D%Q %0%c,[%b]%L",		I(-1)+R(-1,25,1)+R(-1,21,1)+R(-1,0,511),	I(2)+R(0,25,1)+R(0,21,1)+R(0,0,511) },
-  { "st%y%.v%.D %c,[%b,%d]%S%L",	I(-1)+R(-1,25,1)+R(-1,21,1),			I(2)+R(0,25,1)+R(0,21,1) },
-  { "sub%.q%.f %a,%b,%c%F%S%L",		I(-1),		I(10) },
-  { "xor%.q%.f %a,%b,%c%F%S%L",		I(-1),		I(15) }
+  { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 },
+  { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 },
+  { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 },
+  { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 },
+  { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 },
+  { "bic%.q%.f %a,%b,%c%F%S%L",	I(-1), I(14), ARC_MACH_5, 0, 0 },
+  { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 },
+  { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 },
+  { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 },
+  { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 },
+  { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 },
+  { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 },
+  /* %Q: force cond_p=1 -> no shimm values. This insn allows an
+     optional flags spec.  */
+  { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  /* This insn allows an optional flags spec.  */
+  { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+  /* Put opcode 1 ld insns first so shimm gets prefered over limm.
+     "[%b]" is before "[%b,%o]" so 0 offsets don't get printed.  */
+  { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 },
+  { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
+  { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
+  { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1),	I(1)|R(0,13,1), ARC_MACH_5, 0, 0 },
+  { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 },
+  { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 },
+  { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 },
+  { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 },
+  { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 },
+  { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 },
+  { "sbc%.q%.f %a,%b,%c%F%S%L",	I(-1), I(11), ARC_MACH_5, 0, 0 },
+  { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 },
+  { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 },
+  { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 },
+  /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed.  */
+  { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
+  { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
+  { "sub%.q%.f %a,%b,%c%F%S%L",	I(-1), I(10), ARC_MACH_5, 0, 0 },
+  { "xor%.q%.f %a,%b,%c%F%S%L",	I(-1), I(15), ARC_MACH_5, 0, 0 }
 };
+
 const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
 
 const struct arc_operand_value arc_reg_names[] =
 {
-  /* Sort this so that the first 61 entries are sequential.
-     IE: For each i (i<61), arc_reg_names[i].value == i.  */
-
-  { "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG },
-  { "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG },
-  { "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG },
-  { "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG },
-  { "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG },
-  { "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG },
-  { "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG },
-  { "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG },
-  { "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG },
-  { "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG },
-  { "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG },
-  { "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG },
-  { "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG },
-  { "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG },
-  { "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG },
-  { "lp_count", 60, REG },
-
-  /* I'd prefer to output these as "fp" and "sp" by default, but we still need
-     to recognize the canonical values.  */
-  { "r27", 27, REG }, { "r28", 28, REG },
-
-  /* Someone may wish to refer to these in this way, and it's probably a
-     good idea to reserve them as such anyway.  */
-  { "r29", 29, REG }, { "r30", 30, REG }, { "r31", 31, REG }, { "r60", 60, REG },
-
-  /* Standard auxiliary registers.  */
-  { "status",	0, AUXREG },
-  { "semaphore", 1, AUXREG },
-  { "lp_start",	2, AUXREG },
-  { "lp_end",	3, AUXREG },
-  { "identity",	4, AUXREG },
-  { "debug",	5, AUXREG },
+  /* Core register set r0-r63.  */
+
+  /* r0-r28 - general purpose registers.  */
+  { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
+  { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
+  { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
+  { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
+  { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
+  { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
+  { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 },
+  { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 },
+  { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 },
+  { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 },
+  /* Maskable interrupt link register.  */
+  { "ilink1", 29, REG, 0 },
+  /* Maskable interrupt link register.  */
+  { "ilink2", 30, REG, 0 },
+  /* Branch-link register.  */
+  { "blink", 31, REG, 0 },
+
+  /* r32-r59 reserved for extensions.  */
+  { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 },
+  { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 },
+  { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 },
+  { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 },
+  { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 },
+  { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 },
+  { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 },
+  { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 },
+  { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 },
+  { "r59", 59, REG, 0 },
+
+  /* Loop count register (24 bits).  */
+  { "lp_count", 60, REG, ARC_REGISTER_READONLY },
+  /* Short immediate data indicator setting flags.  */
+  { "r61", 61, REG, ARC_REGISTER_READONLY },
+  /* Long immediate data indicator setting flags.  */
+  { "r62", 62, REG, ARC_REGISTER_READONLY },
+  /* Short immediate data indicator not setting flags.  */
+  { "r63", 63, REG, ARC_REGISTER_READONLY },
+
+  /* Small-data base register.  */
+  { "gp", 26, REG, 0 },
+  /* Frame pointer.  */
+  { "fp", 27, REG, 0 },
+  /* Stack pointer.  */
+  { "sp", 28, REG, 0 },
+
+  { "r29", 29, REG, 0 },
+  { "r30", 30, REG, 0 },
+  { "r31", 31, REG, 0 },
+  { "r60", 60, REG, 0 },
+
+  /* Auxiliary register set.  */
+
+  /* Auxiliary register address map:
+     0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation
+     0xfffffeff-0x80000000 - customer limm allocation
+     0x7fffffff-0x00000100 - ARC limm allocation
+     0x000000ff-0x00000000 - ARC shimm allocation  */
+
+  /* Base case auxiliary registers (shimm address).  */
+  { "status",         0x00, AUXREG, 0 },
+  { "semaphore",      0x01, AUXREG, 0 },
+  { "lp_start",       0x02, AUXREG, 0 },
+  { "lp_end",         0x03, AUXREG, 0 },
+  { "identity",       0x04, AUXREG, ARC_REGISTER_READONLY },
+  { "debug",          0x05, AUXREG, 0 },
 };
-const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
+
+const int arc_reg_names_count =
+  sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
 
 /* The suffix table.
    Operands with the same name must be stored together.  */
@@ -357,58 +427,64 @@ const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0
 const struct arc_operand_value arc_suffixes[] =
 {
   /* Entry 0 is special, default values aren't printed by the disassembler.  */
-  { "", 0, -1 },
-  { "al", 0, COND },
-  { "ra", 0, COND },
-  { "eq", 1, COND },
-  { "z", 1, COND },
-  { "ne", 2, COND },
-  { "nz", 2, COND },
-  { "p", 3, COND },
-  { "pl", 3, COND },
-  { "n", 4, COND },
-  { "mi", 4, COND },
-  { "c", 5, COND },
-  { "cs", 5, COND },
-  { "lo", 5, COND },
-  { "nc", 6, COND },
-  { "cc", 6, COND },
-  { "hs", 6, COND },
-  { "v", 7, COND },
-  { "vs", 7, COND },
-  { "nv", 8, COND },
-  { "vc", 8, COND },
-  { "gt", 9, COND },
-  { "ge", 10, COND },
-  { "lt", 11, COND },
-  { "le", 12, COND },
-  { "hi", 13, COND },
-  { "ls", 14, COND },
-  { "pnz", 15, COND },
-  { "f", 1, FLAG },
-  { "nd", ARC_DELAY_NONE, DELAY },
-  { "d", ARC_DELAY_NORMAL, DELAY },
-  { "jd", ARC_DELAY_JUMP, DELAY },
-/*{ "b", 7, SIZEEXT },*/
-/*{ "b", 5, SIZESEX },*/
-  { "b", 1, SIZE1 },
-  { "b", 1, SIZE10 },
-  { "b", 1, SIZE22 },
-/*{ "w", 8, SIZEEXT },*/
-/*{ "w", 6, SIZESEX },*/
-  { "w", 2, SIZE1 },
-  { "w", 2, SIZE10 },
-  { "w", 2, SIZE22 },
-  { "x", 1, SIGN0 },
-  { "x", 1, SIGN9 },
-  { "a", 1, ADDRESS3 },
-  { "a", 1, ADDRESS12 },
-  { "a", 1, ADDRESS24 },
-  { "di", 1, CACHEBYPASS5 },
-  { "di", 1, CACHEBYPASS14 },
-  { "di", 1, CACHEBYPASS26 },
+  { "", 0, -1, 0 },
+
+  /* Base case condition codes.  */
+  { "al", 0, COND, 0 },
+  { "ra", 0, COND, 0 },
+  { "eq", 1, COND, 0 },
+  { "z", 1, COND, 0 },
+  { "ne", 2, COND, 0 },
+  { "nz", 2, COND, 0 },
+  { "pl", 3, COND, 0 },
+  { "p", 3, COND, 0 },
+  { "mi", 4, COND, 0 },
+  { "n", 4, COND, 0 },
+  { "cs", 5, COND, 0 },
+  { "c", 5, COND, 0 },
+  { "lo", 5, COND, 0 },
+  { "cc", 6, COND, 0 },
+  { "nc", 6, COND, 0 },
+  { "hs", 6, COND, 0 },
+  { "vs", 7, COND, 0 },
+  { "v", 7, COND, 0 },
+  { "vc", 8, COND, 0 },
+  { "nv", 8, COND, 0 },
+  { "gt", 9, COND, 0 },
+  { "ge", 10, COND, 0 },
+  { "lt", 11, COND, 0 },
+  { "le", 12, COND, 0 },
+  { "hi", 13, COND, 0 },
+  { "ls", 14, COND, 0 },
+  { "pnz", 15, COND, 0 },
+
+  /* Condition codes 16-31 reserved for extensions.  */
+
+  { "f", 1, FLAG, 0 },
+
+  { "nd", ARC_DELAY_NONE, DELAY, 0 },
+  { "d", ARC_DELAY_NORMAL, DELAY, 0 },
+  { "jd", ARC_DELAY_JUMP, DELAY, 0 },
+
+  { "b", 1, SIZE1, 0 },
+  { "b", 1, SIZE10, 0 },
+  { "b", 1, SIZE22, 0 },
+  { "w", 2, SIZE1, 0 },
+  { "w", 2, SIZE10, 0 },
+  { "w", 2, SIZE22, 0 },
+  { "x", 1, SIGN0, 0 },
+  { "x", 1, SIGN9, 0 },
+  { "a", 1, ADDRESS3, 0 },
+  { "a", 1, ADDRESS12, 0 },
+  { "a", 1, ADDRESS24, 0 },
+
+  { "di", 1, CACHEBYPASS5, 0 },
+  { "di", 1, CACHEBYPASS14, 0 },
+  { "di", 1, CACHEBYPASS26, 0 },
 };
-const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
+
+const int arc_suffixes_count =
+  sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
 
 /* Indexed by first letter of opcode.  Points to chain of opcodes with same
    first letter.  */
@@ -429,10 +505,12 @@ arc_get_opcode_mach (bfd_mach, big_p)
      int bfd_mach, big_p;
 {
   static int mach_type_map[] =
-    {
-      ARC_MACH_BASE
-    };
-
+  {
+    ARC_MACH_5,
+    ARC_MACH_6,
+    ARC_MACH_7,
+    ARC_MACH_8
+  };
   return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0);
 }
 
@@ -453,8 +531,6 @@ arc_opcode_init_tables (flags)
   /* We may be intentionally called more than once (for example gdb will call
      us each time the user switches cpu).  These tables only need to be init'd
      once though.  */
-  /* ??? We can remove the need for arc_opcode_supported by taking it into
-     account here, but I'm not sure I want to do that yet (if ever).  */
   if (!init_p)
     {
       register int i,n;
@@ -490,23 +566,7 @@ int
 arc_opcode_supported (opcode)
      const struct arc_opcode *opcode;
 {
-  if (ARC_OPCODE_CPU (opcode->flags) == 0)
-    return 1;
-  if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type))
-    return 1;
-  return 0;
-}
-
-/* Return non-zero if OPVAL is supported on the specified cpu.
-   Cpu selection is made when calling `arc_opcode_init_tables'.  */
-
-int
-arc_opval_supported (opval)
-     const struct arc_operand_value *opval;
-{
-  if (ARC_OPVAL_CPU (opval->flags) == 0)
-    return 1;
-  if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type))
+  if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type)
     return 1;
   return 0;
 }
@@ -535,14 +595,26 @@ static int flag_p;
 /* Nonzero if we've finished processing the 'f' suffix.  */
 static int flagshimm_handled_p;
 
+/* Nonzero if we've seen a 'a' suffix (address writeback).  */
+static int addrwb_p;
+
 /* Nonzero if we've seen a 'q' suffix (condition code).  */
 static int cond_p;
 
+/* Nonzero if we've inserted a nullify condition.  */
+static int nullify_p;
+
+/* The value of the a nullify condition we inserted.  */
+static int nullify;
+
+/* Nonzero if we've inserted jumpflags.  */
+static int jumpflags_p;
+
 /* Nonzero if we've inserted a shimm.  */
 static int shimm_p;
 
 /* The value of the shimm we inserted (each insn only gets one but it can
-   appear multiple times.  */
+   appear multiple times).  */
 static int shimm;
 
 /* Nonzero if we've inserted a limm (during assembly) or seen a limm
@@ -560,11 +632,20 @@ static long limm;
 void
 arc_opcode_init_insert ()
 {
+  int i;
+
+  for(i = 0; i < OPERANDS; i++)
+    ls_operand[i] = OP_NONE;
+
   flag_p = 0;
   flagshimm_handled_p = 0;
   cond_p = 0;
+  addrwb_p = 0;
   shimm_p = 0;
   limm_p = 0;
+  jumpflags_p = 0;
+  nullify_p = 0;
+  nullify = 0; /* the default is important.  */
 }
 
 /* Called by the assembler to see if the insn has a limm operand.
@@ -572,7 +653,7 @@ arc_opcode_init_insert ()
 
 int
 arc_opcode_limm_p (limmp)
-     long *limmp;
+  long *limmp;
 {
   if (limmp)
     *limmp = limm;
@@ -586,14 +667,15 @@ arc_opcode_limm_p (limmp)
 
 static arc_insn
 insert_reg (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods;
+  const struct arc_operand_value *reg;
+  long value;
+  const char **errmsg;
 {
   static char buf[100];
+  enum operand op_type = OP_NONE;
 
   if (reg == NULL)
     {
@@ -609,16 +691,30 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 	     we have to use a limm.  */
 	  && (!shimm_p || shimm == value))
 	{
-	  int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
-	  flagshimm_handled_p = 1;
-	  shimm_p = 1;
-	  shimm = value;
+	  int marker;
+
+          op_type = OP_SHIMM;
+	 /* forget about shimm as dest mlm.  */
+
+	  if('a' != operand->fmt)
+	    {
+	      shimm_p = 1;
+	      shimm = value;
+	      flagshimm_handled_p = 1;
+	      marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
+	    }
+          else
+            {
+	      /* don't request flag setting on shimm as dest.  */
+	      marker = ARC_REG_SHIMM;
+            }
 	  insn |= marker << operand->shift;
-	  /* insn |= value & 511; - done later */
+	  /* insn |= value & 511; - done later.  */
 	}
       /* We have to use a limm.  If we've already seen one they must match.  */
       else if (!limm_p || limm == value)
 	{
+	  op_type = OP_LIMM;
 	  limm_p = 1;
 	  limm = value;
 	  insn |= ARC_REG_LIMM << operand->shift;
@@ -626,7 +722,7 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 	}
       else
 	{
-	  *errmsg = _("unable to fit different valued constants into instruction");
+	  *errmsg = "unable to fit different valued constants into instruction";
 	}
     }
   else
@@ -636,27 +732,66 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
       if (reg->type == AUXREG)
 	{
 	  if (!(mods & ARC_MOD_AUXREG))
-	    *errmsg = _("auxiliary register not allowed here");
+	    *errmsg = "auxiliary register not allowed here";
 	  else
 	    {
+              if((insn & I(-1)) == I(2)) /* check for use validity.  */
+                 {
+		   if(reg->flags & ARC_REGISTER_READONLY)
+		     *errmsg = "attempt to set readonly register";
+                 }
+               else
+                 {
+		   if(reg->flags & ARC_REGISTER_WRITEONLY)
+		     *errmsg = "attempt to read writeonly register";
+                 }
 	      insn |= ARC_REG_SHIMM << operand->shift;
 	      insn |= reg->value << arc_operands[reg->type].shift;
 	    }
 	}
       else
 	{
+      /* check for use validity.  */
+          if('a' == operand->fmt || ((insn & I(-1)) < I(2)))
+            {
+	      if(reg->flags & ARC_REGISTER_READONLY)
+		*errmsg = "attempt to set readonly register";
+            }
+          if('a' != operand->fmt)
+            {
+	      if(reg->flags & ARC_REGISTER_WRITEONLY)
+		*errmsg = "attempt to read writeonly register";
+            }
 	  /* We should never get an invalid register number here.  */
 	  if ((unsigned int) reg->value > 60)
 	    {
-	      /* xgettext:c-format */
-	      sprintf (buf, _("invalid register number `%d'"), reg->value);
+	      sprintf (buf, "invalid register number `%d'", reg->value);
 	      *errmsg = buf;
 	    }
-	  else
-	    insn |= reg->value << operand->shift;
+	  insn |= reg->value << operand->shift;
+          op_type = OP_REG;
 	}
     }
 
+  switch (operand->fmt)
+    {
+    case 'a':
+      ls_operand[LS_DEST] = op_type; 
+      break;
+    case 's':
+      ls_operand[LS_BASE] = op_type; 
+      break;
+    case 'c':
+      if ((insn & I(-1)) == I(2))
+          ls_operand[LS_VALUE] = op_type; 
+      else
+          ls_operand[LS_OFFSET] = op_type;
+      break;
+    case 'o': case 'O':
+      ls_operand[LS_OFFSET] = op_type;
+      break;
+    }
+
   return insn;
 }
 
@@ -664,18 +799,34 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
 
 static arc_insn
 insert_flag (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+  arc_insn insn;
+  const struct arc_operand *operand ATTRIBUTE_UNUSED;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value ATTRIBUTE_UNUSED;
+  const char **errmsg ATTRIBUTE_UNUSED;
 {
   /* We can't store anything in the insn until we've parsed the registers.
      Just record the fact that we've got this flag.  `insert_reg' will use it
      to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100).  */
   flag_p = 1;
+  return insn;
+}
 
+/* Called when we see an nullify condition.  */
+
+static arc_insn
+insert_nullify (insn, operand, mods, reg, value, errmsg)
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value;
+  const char **errmsg ATTRIBUTE_UNUSED;
+{
+  nullify_p = 1;
+  insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+  nullify = value;
   return insn;
 }
 
@@ -685,12 +836,12 @@ insert_flag (insn, operand, mods, reg, value, errmsg)
 
 static arc_insn
 insert_flagfinish (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value ATTRIBUTE_UNUSED;
+  const char **errmsg ATTRIBUTE_UNUSED;
 {
   if (flag_p && !flagshimm_handled_p)
     {
@@ -706,12 +857,12 @@ insert_flagfinish (insn, operand, mods, reg, value, errmsg)
 
 static arc_insn
 insert_cond (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value;
+  const char **errmsg ATTRIBUTE_UNUSED;
 {
   cond_p = 1;
   insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
@@ -726,34 +877,100 @@ insert_cond (insn, operand, mods, reg, value, errmsg)
 
 static arc_insn
 insert_forcelimm (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+  arc_insn insn;
+  const struct arc_operand *operand ATTRIBUTE_UNUSED;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value ATTRIBUTE_UNUSED;
+  const char **errmsg ATTRIBUTE_UNUSED;
 {
   cond_p = 1;
   return insn;
 }
 
-/* Used in ld/st insns to handle the shimm offset field.  */
+static arc_insn
+insert_addr_wb (insn, operand, mods, reg, value, errmsg)
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value ATTRIBUTE_UNUSED;
+  const char **errmsg ATTRIBUTE_UNUSED;
+{
+  addrwb_p = 1 << operand->shift;
+  return insn;
+}
+
+static arc_insn
+insert_base (insn, operand, mods, reg, value, errmsg)
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods;
+  const struct arc_operand_value *reg;
+  long value;
+  const char **errmsg;
+{
+  if (reg != NULL)
+    {
+      arc_insn myinsn;
+      myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift;
+      insn |= B(myinsn);
+      ls_operand[LS_BASE] = OP_REG; 
+    }
+  else if (ARC_SHIMM_CONST_P (value) && !cond_p)
+    {
+      if (shimm_p && value != shimm)
+        {
+          /* convert the previous shimm operand to a limm.  */
+          limm_p = 1;
+          limm = shimm;
+          insn &= ~C(-1); /* we know where the value is in insn.  */
+          insn |= C(ARC_REG_LIMM);
+          ls_operand[LS_VALUE] = OP_LIMM;
+        }
+      insn |= ARC_REG_SHIMM << operand->shift;
+      shimm_p = 1;
+      shimm = value;
+      ls_operand[LS_BASE] = OP_SHIMM;
+    }
+  else
+    {
+      if (limm_p && value != limm)
+        {
+          *errmsg = "too many long constants";
+          return insn;
+        }
+      limm_p = 1;
+      limm = value;
+      insn |= B(ARC_REG_LIMM);
+      ls_operand[LS_BASE] = OP_LIMM;
+    }
+
+  return insn;
+}
+
+/* Used in ld/st insns to handle the offset field. We don't try to
+   match operand syntax here. we catch bad combinations later.  */
 
 static arc_insn
-insert_shimmoffset (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+insert_offset (insn, operand, mods, reg, value, errmsg)
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods;
+  const struct arc_operand_value *reg;
+  long value;
+  const char **errmsg;
 {
   long minval, maxval;
-  static char buf[100];
 
   if (reg != NULL)
     {
-      *errmsg = "register appears where shimm value expected";
+      arc_insn myinsn;
+      myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift;
+      ls_operand[LS_OFFSET] = OP_REG;
+      if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later.  */
+          if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later.  */
+              insn |= C(myinsn);
     }
   else
     {
@@ -769,46 +986,281 @@ insert_shimmoffset (insn, operand, mods, reg, value, errmsg)
 	  minval = 0;
 	  maxval = (1 << operand->bits) - 1;
 	}
-      if (value < minval || value > maxval)
+      if ((cond_p && !limm_p) || (value < minval || value > maxval))
 	{
-	  /* xgettext:c-format */
-	  sprintf (buf, _("value won't fit in range %ld - %ld"),
-		   minval, maxval);
-	  *errmsg = buf;
+        if (limm_p && value != limm)
+          {
+	    *errmsg = "too many long constants";
+          }
+        else
+          {
+	    limm_p = 1;
+	    limm = value;
+	    if (operand->flags & ARC_OPERAND_STORE)
+	      insn |= B(ARC_REG_LIMM);
+	    if (operand->flags & ARC_OPERAND_LOAD)
+	      insn |= C(ARC_REG_LIMM);
+	    ls_operand[LS_OFFSET] = OP_LIMM;
+          }
 	}
       else
-	insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+        {
+	  if ((value < minval || value > maxval))
+	    *errmsg = "need too many limms";
+	  else if (shimm_p && value != shimm) 
+	    {
+	      /* check for bad operand combinations before we lose info about them.  */
+	      if ((insn & I(-1)) == I(1))
+		{
+		  *errmsg = "to many shimms in load";
+		  goto out;
+		}
+	      if (limm_p && operand->flags & ARC_OPERAND_LOAD)
+		{
+		  *errmsg = "too many long constants";
+		  goto out;
+		}
+	      /* convert what we thought was a shimm to a limm.  */
+	      limm_p = 1;
+	      limm = shimm;
+	      if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE)
+		{
+		  insn &= ~C(-1);
+		  insn |= C(ARC_REG_LIMM);
+		  ls_operand[LS_VALUE] = OP_LIMM;
+		}
+	      if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE)
+		{
+		  insn &= ~B(-1);
+		  insn |= B(ARC_REG_LIMM);
+		  ls_operand[LS_BASE] = OP_LIMM;
+		}
+	    }
+	  shimm = value;
+	  shimm_p = 1;
+	  ls_operand[LS_OFFSET] = OP_SHIMM;
+        }
     }
+ out:
   return insn;
 }
 
-/* Used in ld/st insns when the shimm offset is 0.  */
+/* Used in st insns to do final disasemble syntax check.  */
+
+static long
+extract_st_syntax (insn, operand, mods, opval, invalid)
+  arc_insn *insn;
+  const struct arc_operand *operand ATTRIBUTE_UNUSED;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+  int *invalid;
+{
+#define ST_SYNTAX(V,B,O) \
+((ls_operand[LS_VALUE]  == (V) && \
+  ls_operand[LS_BASE]   == (B) && \
+  ls_operand[LS_OFFSET] == (O)))
+  if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE)   && (insn[0] & 511) == 0)
+	|| ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
+	|| (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
+	|| (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0)
+	|| ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
+	|| ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM)
+	|| ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
+	|| (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE)  && (insn[0] & 511) == 0)
+	|| ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+	|| ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+	|| ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
+	|| ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
+	|| ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)
+	|| ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
+    *invalid = 1;
+  return 0;
+}
+
+int
+arc_limm_fixup_adjust(insn)
+  arc_insn insn;
+{
+  int retval = 0;
+
+  /* check for st shimm,[limm].  */
+  if ((insn & (I(-1) | C(-1) | B(-1))) ==
+     (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM)))
+    {
+      retval = insn & 0x1ff;
+      if (retval & 0x100) /* sign extend 9 bit offset.  */
+	retval |= ~0x1ff;
+    }
+  return(-retval); /* negate offset for return.  */
+}
+
+/* Used in st insns to do final syntax check.  */
+
+static arc_insn
+insert_st_syntax (insn, operand, mods, reg, value, errmsg)
+  arc_insn insn;
+  const struct arc_operand *operand ATTRIBUTE_UNUSED;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value ATTRIBUTE_UNUSED;
+  const char **errmsg;
+{
+  if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm != 0)
+    {
+      /* change an illegal insn into a legal one, it's easier to
+	 do it here than to try to handle it during operand scan.  */
+      limm_p = 1;
+      limm = shimm;
+      shimm_p = 0;
+      shimm = 0;
+      insn = insn & ~(C(-1) | 511);
+      insn |= ARC_REG_LIMM << ARC_SHIFT_REGC;
+      ls_operand[LS_VALUE] = OP_LIMM;
+    }
+
+  if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE))
+    {
+      /* try to salvage this syntax.  */
+    if (shimm & 0x1) /* odd shimms won't work.  */
+      {
+	if (limm_p) /* do we have a limm already?  */
+	  {
+	    *errmsg = "impossible store";
+	  }
+	limm_p = 1;
+	limm = shimm;
+	shimm = 0;
+	shimm_p = 0;
+	insn = insn & ~(B(-1) | 511);
+	insn |= B(ARC_REG_LIMM);
+	ls_operand[LS_BASE] = OP_LIMM;
+      }
+    else
+      {
+	shimm >>= 1;
+	insn = insn & ~511;
+	insn |= shimm;
+	ls_operand[LS_OFFSET] = OP_SHIMM;
+      }
+    }
+  if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE))
+    {
+      limm += arc_limm_fixup_adjust(insn);
+    }
+  if (ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) && (shimm * 2 == limm))
+    {
+      insn &= ~C(-1);
+      limm_p = 0;
+      limm = 0;
+      insn |= C(ARC_REG_SHIMM);
+      ls_operand[LS_VALUE] = OP_SHIMM;
+    }
+  if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE)
+	|| ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
+	|| ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+	|| ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+	|| (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0))
+	|| ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
+	|| ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE)
+	|| ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
+	|| ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
+	|| ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
+	|| ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) 
+	|| ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
+    *errmsg = "st operand error";
+  if (addrwb_p)
+    {
+      if (ls_operand[LS_BASE] != OP_REG)
+	*errmsg = "address writeback not allowed";
+      insn |= addrwb_p;
+    }
+  if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm)
+    *errmsg = "store value must be zero";
+  return insn;
+}
+
+/* Used in ld insns to do final syntax check.  */
 
 static arc_insn
-insert_shimmzero (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+insert_ld_syntax (insn, operand, mods, reg, value, errmsg)
+  arc_insn insn;
+  const struct arc_operand *operand ATTRIBUTE_UNUSED;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value ATTRIBUTE_UNUSED;
+  const char **errmsg;
 {
-  shimm_p = 1;
-  shimm = 0;
+#define LD_SYNTAX(D,B,O) \
+((ls_operand[LS_DEST]  == (D) && \
+  ls_operand[LS_BASE]   == (B) && \
+  ls_operand[LS_OFFSET] == (O)))
+
+  int test = insn & I(-1);
+
+  if (!(test == I(1)))
+   {
+     if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
+	  || ls_operand[LS_OFFSET] == OP_SHIMM))
+       *errmsg = "invalid load/shimm insn";
+   }
+  if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE)
+	|| LD_SYNTAX(OP_REG,OP_REG,OP_REG)
+	|| LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+	|| (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
+	|| (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
+	|| LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) 
+	|| (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
+      *errmsg = "ld operand error";
+  if (addrwb_p)
+    {
+      if (ls_operand[LS_BASE] != OP_REG)
+	*errmsg = "address writeback not allowed";
+      insn |= addrwb_p;
+    }
   return insn;
 }
 
+/* Used in ld insns to do final syntax check.  */
+
+static long
+extract_ld_syntax (insn, operand, mods, opval, invalid)
+  arc_insn *insn;
+  const struct arc_operand *operand ATTRIBUTE_UNUSED;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+  int *invalid;
+{
+  int test = insn[0] & I(-1);
+
+  if (!(test == I(1)))
+    {
+      if((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
+	  || ls_operand[LS_OFFSET] == OP_SHIMM))
+	*invalid = 1;
+    }
+  if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1)))
+	|| LD_SYNTAX(OP_REG,OP_REG,OP_REG)
+	|| LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+	|| (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
+	|| (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
+	|| (LD_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) && (shimm == 0))
+	|| LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+	|| (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
+    *invalid = 1;
+  return 0;
+}
+
 /* Called at the end of processing normal insns (eg: add) to insert a shimm
    value (if present) into the insn.  */
 
 static arc_insn
 insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value ATTRIBUTE_UNUSED;
+  const char **errmsg ATTRIBUTE_UNUSED;
 {
   if (shimm_p)
     insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
@@ -829,15 +1281,52 @@ insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
 
 static arc_insn
 insert_limmfinish (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+  arc_insn insn;
+  const struct arc_operand *operand ATTRIBUTE_UNUSED;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value ATTRIBUTE_UNUSED;
+  const char **errmsg ATTRIBUTE_UNUSED;
 {
+#if 0
   if (limm_p)
-    ; /* nothing to do, gas does it */
+    ; /* nothing to do, gas does it.  */
+#endif
+  return insn;
+}
+
+static arc_insn
+insert_jumpflags (insn, operand, mods, reg, value, errmsg)
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value;
+  const char **errmsg;
+{
+  if (!flag_p)
+    {
+      *errmsg = "jump flags, but no .f seen";
+    }
+  if (!limm_p)
+    {
+      *errmsg = "jump flags, but no limm addr";
+    }
+  if (limm & 0xfc000000)
+    {
+      *errmsg = "flag bits of jump address limm lost";
+    }
+  if (limm & 0x03000000)
+    {
+      *errmsg = "attempt to set HR bits";
+    }
+  if ((value & ((1 << operand->bits) - 1)) != value)
+    {
+      *errmsg = "bad jump flags value";
+    }
+  jumpflags_p = 1;
+  limm = (limm & ((1 << operand->shift) - 1))
+    | ((value & ((1 << operand->bits) - 1)) << operand->shift); 
   return insn;
 }
 
@@ -845,12 +1334,12 @@ insert_limmfinish (insn, operand, mods, reg, value, errmsg)
 
 static arc_insn
 insert_unopmacro (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value ATTRIBUTE_UNUSED;
+  const char **errmsg ATTRIBUTE_UNUSED;
 {
   insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
   return insn;
@@ -860,15 +1349,15 @@ insert_unopmacro (insn, operand, mods, reg, value, errmsg)
 
 static arc_insn
 insert_reladdr (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+  arc_insn insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value;
+  const char **errmsg;
 {
   if (value & 3)
-    *errmsg = _("branch address not on 4 byte boundary");
+    *errmsg = "branch address not on 4 byte boundary";
   insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
   return insn;
 }
@@ -878,23 +1367,42 @@ insert_reladdr (insn, operand, mods, reg, value, errmsg)
    Note that this function is only intended to handle instructions (with 4 byte
    immediate operands).  It is not intended to handle data.  */
 
-/* ??? Actually, there's nothing for us to do as we can't call frag_more, the
+/* ??? Actually, there's little for us to do as we can't call frag_more, the
    caller must do that.  The extract fns take a pointer to two words.  The
    insert fns could be converted and then we could do something useful, but
    then the reloc handlers would have to know to work on the second word of
-   a 2 word quantity.  That's too much so we don't handle them.  */
+   a 2 word quantity.  That's too much so we don't handle them.
+
+   We do check for correct usage of the nullify suffix, or we
+   set the default correctly, though.  */
 
 static arc_insn
 insert_absaddr (insn, operand, mods, reg, value, errmsg)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     long value;
-     const char **errmsg;
+  arc_insn insn;
+  const struct arc_operand *operand ATTRIBUTE_UNUSED;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+  long value ATTRIBUTE_UNUSED;
+  const char **errmsg;
 {
   if (limm_p)
-    ; /* nothing to do */
+    {
+      /* if it is a jump and link, .jd must be specified.  */
+      if (insn & R(-1,9,1))
+	{
+	  if (!nullify_p)
+	    {
+	      insn |=  0x02 << 5;  /* default nullify to .jd.  */
+	    }
+	  else
+	    {
+	      if(nullify != 0x02)
+		{
+		  *errmsg = "must specify .jd or no nullify suffix";
+		}
+	    }
+	}
+    }
   return insn;
 }
 
@@ -912,10 +1420,7 @@ static const struct arc_operand_value *lookup_register (int type, long regno);
 void
 arc_opcode_init_extract ()
 {
-  flag_p = 0;
-  flagshimm_handled_p = 0;
-  shimm_p = 0;
-  limm_p = 0;
+  arc_opcode_init_insert();
 }
 
 /* As we're extracting registers, keep an eye out for the 'f' indicator
@@ -927,46 +1432,76 @@ arc_opcode_init_extract ()
 
 static long
 extract_reg (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value **opval;
-     int *invalid;
+  arc_insn *insn;
+  const struct arc_operand *operand;
+  int mods;
+  const struct arc_operand_value **opval;
+  int *invalid ATTRIBUTE_UNUSED;
 {
   int regno;
   long value;
+  enum operand op_type;
 
   /* Get the register number.  */
-  regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+  regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
 
   /* Is it a constant marker?  */
   if (regno == ARC_REG_SHIMM)
     {
-      value = insn[0] & 511;
-      if ((operand->flags & ARC_OPERAND_SIGNED)
-	  && (value & 256))
-	value -= 512;
-      flagshimm_handled_p = 1;
+      op_type = OP_SHIMM;
+    /* always return zero if dest is a shimm  mlm.  */
+
+      if ('a' != operand->fmt)
+	{
+	  value = *insn & 511;
+	  if ((operand->flags & ARC_OPERAND_SIGNED)
+	      && (value & 256))
+	    value -= 512;
+	  if (!flagshimm_handled_p)
+	    flag_p = 0;
+	  flagshimm_handled_p = 1;
+	}
+      else
+	{
+	  value = 0;
+	}
     }
   else if (regno == ARC_REG_SHIMM_UPDATE)
     {
-      value = insn[0] & 511;
-      if ((operand->flags & ARC_OPERAND_SIGNED)
-	  && (value & 256))
-	value -= 512;
+      op_type = OP_SHIMM;
+
+      /* always return zero if dest is a shimm  mlm.  */
+
+      if ('a' != operand->fmt)
+	{
+	  value = *insn & 511;
+	  if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
+	    value -= 512;
+	}
+      else
+	{
+	  value = 0;
+	}
       flag_p = 1;
       flagshimm_handled_p = 1;
     }
   else if (regno == ARC_REG_LIMM)
     {
+      op_type = OP_LIMM;
       value = insn[1];
       limm_p = 1;
+      /* if this is a jump instruction (j,jl), show new pc correctly.  */
+      if(0x07 == ((*insn & I(-1)) >> 27))
+        {
+	  value = (value & 0xffffff);
+        }
     }
   /* It's a register, set OPVAL (that's the only way we distinguish registers
      from constants here).  */
   else
     {
       const struct arc_operand_value *reg = lookup_register (REG, regno);
+      op_type = OP_REG;
 
       if (reg == NULL)
 	abort ();
@@ -986,6 +1521,24 @@ extract_reg (insn, operand, mods, opval, invalid)
       if (reg != NULL && opval != NULL)
 	*opval = reg;
     }
+  switch(operand->fmt)
+   {
+   case 'a':
+     ls_operand[LS_DEST] = op_type; 
+     break;
+   case 's':
+     ls_operand[LS_BASE] = op_type; 
+     break;
+   case 'c':
+     if((insn[0]& I(-1)) == I(2))
+       ls_operand[LS_VALUE] = op_type; 
+     else
+       ls_operand[LS_OFFSET] = op_type;
+     break;
+   case 'o': case 'O':
+     ls_operand[LS_OFFSET] = op_type;
+     break;
+   }
 
   return value;
 }
@@ -995,11 +1548,11 @@ extract_reg (insn, operand, mods, opval, invalid)
 
 static long
 extract_flag (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value **opval;
-     int *invalid;
+  arc_insn *insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value **opval;
+  int *invalid ATTRIBUTE_UNUSED;
 {
   int f;
   const struct arc_operand_value *val;
@@ -1007,12 +1560,12 @@ extract_flag (insn, operand, mods, opval, invalid)
   if (flagshimm_handled_p)
     f = flag_p != 0;
   else
-    f = (insn[0] & (1 << operand->shift)) != 0;
+    f = (*insn & (1 << operand->shift)) != 0;
 
   /* There is no text for zero values.  */
   if (f == 0)
     return 0;
-
+  flag_p = 1;
   val = arc_opcode_lookup_suffix (operand, 1);
   if (opval != NULL && val != NULL)
     *opval = val;
@@ -1026,11 +1579,11 @@ extract_flag (insn, operand, mods, opval, invalid)
 
 static long
 extract_cond (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value **opval;
-     int *invalid;
+  arc_insn *insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value **opval;
+  int *invalid ATTRIBUTE_UNUSED;
 {
   long cond;
   const struct arc_operand_value *val;
@@ -1038,7 +1591,7 @@ extract_cond (insn, operand, mods, opval, invalid)
   if (flagshimm_handled_p)
     return 0;
 
-  cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+  cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
   val = arc_opcode_lookup_suffix (operand, cond);
 
   /* Ignore NULL values of `val'.  Several condition code values are
@@ -1053,42 +1606,109 @@ extract_cond (insn, operand, mods, opval, invalid)
 
 static long
 extract_reladdr (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value **opval;
-     int *invalid;
+  arc_insn *insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+  int *invalid ATTRIBUTE_UNUSED;
 {
   long addr;
 
-  addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+  addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
   if ((operand->flags & ARC_OPERAND_SIGNED)
       && (addr & (1 << (operand->bits - 1))))
     addr -= 1 << operand->bits;
-
   return addr << 2;
 }
 
+/* extract the flags bits from a j or jl long immediate.  */
+static long
+extract_jumpflags(insn, operand, mods, opval, invalid)
+  arc_insn *insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+  int *invalid;
+{
+  if (!flag_p || !limm_p)
+    *invalid = 1;
+  return((flag_p && limm_p)
+         ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0);
+}
+
+/* extract st insn's offset.  */
+
+static long
+extract_st_offset (insn, operand, mods, opval, invalid)
+  arc_insn *insn;
+  const struct arc_operand *operand;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+  int *invalid;
+{
+  int value = 0;
+
+  if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM)
+    {
+      value = insn[0] & 511;
+      if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
+	value -= 512;
+      if(value)
+	ls_operand[LS_OFFSET] = OP_SHIMM;
+    }
+  else
+    {
+      *invalid = 1;
+    }
+  return(value);
+}
+
+/* extract ld insn's offset.  */
+
+static long
+extract_ld_offset (insn, operand, mods, opval, invalid)
+  arc_insn *insn;
+  const struct arc_operand *operand;
+  int mods;
+  const struct arc_operand_value **opval;
+  int *invalid;
+{
+  int test = insn[0] & I(-1);
+  int value;
+
+  if (test)
+    {
+      value = insn[0] & 511;
+      if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
+	value -= 512;
+      if (value)
+	ls_operand[LS_OFFSET] = OP_SHIMM;
+      return(value);
+    }
+/* if it isn't in the insn, it's concealed behind reg 'c'.  */
+  return extract_reg(insn,
+                     &arc_operands[arc_operand_map['c']], mods, opval, invalid);
+}
+
 /* The only thing this does is set the `invalid' flag if B != C.
    This is needed because the "mov" macro appears before it's real insn "and"
    and we don't want the disassembler to confuse them.  */
 
 static long
 extract_unopmacro (insn, operand, mods, opval, invalid)
-     arc_insn *insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value **opval;
-     int *invalid;
+  arc_insn *insn;
+  const struct arc_operand *operand ATTRIBUTE_UNUSED;
+  int mods ATTRIBUTE_UNUSED;
+  const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+  int *invalid;
 {
   /* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
      C == ARC_REG_SHIMM (or vice versa).  No big deal.  Those insns will get
      printed as "and"s.  */
-  if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG)
-      != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG))
+  if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG)
+      != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG))
     if (invalid != NULL)
       *invalid = 1;
-
   return 0;
 }
 
@@ -1097,10 +1717,19 @@ extract_unopmacro (insn, operand, mods, opval, invalid)
 
 const struct arc_operand_value *
 arc_opcode_lookup_suffix (type, value)
-     const struct arc_operand *type;
-     int value;
+  const struct arc_operand *type;
+  int value;
 {
   register const struct arc_operand_value *v,*end;
+  struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+
+  while (ext_oper)
+    {
+      if (type == &arc_operands[ext_oper->operand.type]
+	  && value == ext_oper->operand.value)
+	return (&ext_oper->operand);
+      ext_oper = ext_oper->next;
+    }
 
   /* ??? This is a little slow and can be speeded up.  */
 
@@ -1113,10 +1742,18 @@ arc_opcode_lookup_suffix (type, value)
 
 static const struct arc_operand_value *
 lookup_register (type, regno)
-     int type;
-     long regno;
+  int type;
+  long regno;
 {
   register const struct arc_operand_value *r,*end;
+  struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+
+  while (ext_oper)
+    {
+      if (ext_oper->operand.type == type && ext_oper->operand.value == regno)
+	return (&ext_oper->operand);
+      ext_oper = ext_oper->next;
+    }
 
   if (type == REG)
     return &arc_reg_names[regno];
@@ -1129,3 +1766,58 @@ lookup_register (type, regno)
       return r;
   return 0;
 }
+
+int
+arc_insn_is_j(insn)
+  arc_insn insn;
+{
+  return (insn & (I(-1))) == I(0x7);
+}
+
+int
+arc_insn_not_jl(insn)
+  arc_insn insn;
+{
+  return (insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) !=
+    (I(0x7) | R(-1,9,1));
+}
+
+int
+arc_operand_type(int opertype)
+{
+  switch (opertype)
+    {
+    case 0:
+      return(COND);
+      break;
+    case 1:
+      return(REG);
+      break;
+    case 2:
+      return(AUXREG);
+      break;
+    }
+  return -1;
+}
+
+struct arc_operand_value *
+get_ext_suffix(s)
+  char *s;
+{
+  struct arc_ext_operand_value *suffix = arc_ext_operands;
+
+  while (suffix)
+    {
+      if ((COND == suffix->operand.type)
+	  && !strcmp(s,suffix->operand.name))
+	return(&suffix->operand);
+      suffix = suffix->next;
+    }
+  return(NULL);
+}
+
+int
+arc_get_noshortcut_flag()
+{
+  return(ARC_REGISTER_NOSHORT_CUT);
+}
diff --git a/opcodes/configure b/opcodes/configure
index 08ca1cd..426a70e 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -4516,7 +4516,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_a29k_arch)		ta="$ta a29k-dis.lo" ;;
 	bfd_alliant_arch)	;;
 	bfd_alpha_arch)		ta="$ta alpha-dis.lo alpha-opc.lo" ;;
-	bfd_arc_arch)		ta="$ta arc-dis.lo arc-opc.lo" ;;
+	bfd_arc_arch)		ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
 	bfd_arm_arch)		ta="$ta arm-dis.lo" ;;
 	bfd_avr_arch)		ta="$ta avr-dis.lo" ;;
 	bfd_convex_arch)	;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 7b18cfa..b0d4288 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -170,7 +170,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_a29k_arch)		ta="$ta a29k-dis.lo" ;;
 	bfd_alliant_arch)	;;
 	bfd_alpha_arch)		ta="$ta alpha-dis.lo alpha-opc.lo" ;;
-	bfd_arc_arch)		ta="$ta arc-dis.lo arc-opc.lo" ;;
+	bfd_arc_arch)		ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
 	bfd_arm_arch)		ta="$ta arm-dis.lo" ;;
 	bfd_avr_arch)		ta="$ta avr-dis.lo" ;;
 	bfd_convex_arch)	;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index f4c61f3..9a957c2 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -87,8 +87,7 @@ disassembler (abfd)
 #ifdef ARCH_arc
     case bfd_arch_arc:
       {
-	disassemble = arc_get_disassembler (bfd_get_mach (abfd),
-					    bfd_big_endian (abfd));
+	disassemble = arc_get_disassembler (abfd);
 	break;
       }
 #endif
diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in
index 1b24f67..b30cbd5 100644
--- a/opcodes/po/POTFILES.in
+++ b/opcodes/po/POTFILES.in
@@ -2,6 +2,7 @@ a29k-dis.c
 alpha-dis.c
 alpha-opc.c
 arc-dis.c
+arc-ext.c
 arc-opc.c
 arm-dis.c
 arm-opc.h
diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot
index f286872..3336bbd 100644
--- a/opcodes/po/opcodes.pot
+++ b/opcodes/po/opcodes.pot
@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2001-01-09 12:07-0800\n"
+"POT-Creation-Date: 2001-01-11 12:44-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -22,31 +22,8 @@ msgstr ""
 msgid "jump hint unaligned"
 msgstr ""
 
-#. Default text to print if an instruction isn't recognized.
-#: arc-dis.c:232 fr30-dis.c:39 m32r-dis.c:39
-msgid "*unknown*"
-msgstr ""
-
-#: arc-opc.c:629
-msgid "unable to fit different valued constants into instruction"
-msgstr ""
-
-#: arc-opc.c:639
-msgid "auxiliary register not allowed here"
-msgstr ""
-
-#: arc-opc.c:652
-#, c-format
-msgid "invalid register number `%d'"
-msgstr ""
-
-#: arc-opc.c:775
-#, c-format
-msgid "value won't fit in range %ld - %ld"
-msgstr ""
-
-#: arc-opc.c:871
-msgid "branch address not on 4 byte boundary"
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
 msgstr ""
 
 #: arm-dis.c:489
@@ -143,6 +120,11 @@ msgstr ""
 msgid "bad instruction `%.50s'"
 msgstr ""
 
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:39 m32r-dis.c:39
+msgid "*unknown*"
+msgstr ""
+
 #: fr30-dis.c:300 m32r-dis.c:239
 #, c-format
 msgid "Unrecognized field %d while printing insn.\n"
@@ -204,7 +186,7 @@ msgstr ""
 msgid "%02x\t\t*unknown*"
 msgstr ""
 
-#: i386-dis.c:2624
+#: i386-dis.c:2740
 msgid "<internal disassembler error>"
 msgstr ""