From: Claudiu Manoil <claudiu.manoil@nxp.com>
Date: Tue, 26 Feb 2019 13:42:21 +0000 (+0200)
Subject: arm64: dts: fsl: ls1028a-rdb: Add ENETC external eth ports for the LS1028A RDB board
X-Git-Tag: v5.15~6918^2~49^2~2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0c805404f083cad1cd5a79eda421d726ce76e63a;p=platform%2Fkernel%2Flinux-starfive.git

arm64: dts: fsl: ls1028a-rdb: Add ENETC external eth ports for the LS1028A RDB board

The LS1028A RDB board features an Atheros PHY connected over
SGMII to the ENETC PF0 (or Port0).  ENETC Port1 (PF1) has no
external connection on this board, so it can be disabled for now.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index fdeb4176fc33..f86b054a74ae 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -71,3 +71,20 @@
 &duart1 {
 	status = "okay";
 };
+
+&enetc_port0 {
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		sgmii_phy0: ethernet-phy@2 {
+			reg = <0x2>;
+		};
+	};
+};
+
+&enetc_port1 {
+	status = "disabled";
+};