From: Minkyu Kang Date: Mon, 27 Jul 2009 05:41:12 +0000 (+0900) Subject: s5pc1xx: clock: s5pc110 support X-Git-Tag: s5pc110_universal_support~53 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0c5a84b70ad831cbedd72d95a1c2945e0b351520;p=kernel%2Fu-boot.git s5pc1xx: clock: s5pc110 support Signed-off-by: Minkyu Kang --- diff --git a/board/samsung/universal/lowlevel_init.S b/board/samsung/universal/lowlevel_init.S index 5e9db86..a146439 100644 --- a/board/samsung/universal/lowlevel_init.S +++ b/board/samsung/universal/lowlevel_init.S @@ -190,14 +190,18 @@ wakeup_reset: * void system_clock_init(void) */ system_clock_init: - ldr r8, =S5P_PA_CLK @ 0xE0100000 + ldr r6, =S5P_PA_CLK @ 0xE0100000 + + /* Check S5PC100 */ + cmp r7, r8 + bne 110f /* Set Lock Time */ ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 - str r1, [r8, #0x000] @ S5P_APLL_LOCK - str r1, [r8, #0x004] @ S5P_MPLL_LOCK - str r1, [r8, #0x008] @ S5P_EPLL_LOCK - str r1, [r8, #0x00C] @ S5P_HPLL_LOCK + str r1, [r6, #0x000] @ S5P_APLL_LOCK + str r1, [r6, #0x004] @ S5P_MPLL_LOCK + str r1, [r6, #0x008] @ S5P_EPLL_LOCK + str r1, [r6, #0x00C] @ S5P_HPLL_LOCK /* S5P_APLL_CON */ #ifdef CONFIG_CLK_667_166_83 @@ -217,19 +221,58 @@ system_clock_init: #else #error you should set the correct clock configuration #endif - str r1, [r8, #0x100] + str r1, [r6, #0x100] /* S5P_MPLL_CON */ ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) - str r1, [r8, #0x104] + str r1, [r6, #0x104] /* S5P_EPLL_CON */ ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz) - str r1, [r8, #0x108] + str r1, [r6, #0x108] /* S5P_HPLL_CON */ ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96 - str r1, [r8, #0x10C] + str r1, [r6, #0x10C] + b 200f +110: + /* Set Lock Time */ + ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 + str r1, [r6, #0x000] @ S5P_APLL_LOCK + str r1, [r6, #0x008] @ S5P_MPLL_LOCK + str r1, [r6, #0x010] @ S5P_EPLL_LOCK + str r1, [r6, #0x020] @ S5P_VPLL_LOCK + + /* S5P_APLL_CON */ +#ifdef CONFIG_CLK_667_166_83 + ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz) +#elif defined(CONFIG_CLK_666_166_66) + ldr r1, =0x814d0301 @ SDIV 1, PDIV 3, MDIV 333 (1333MHz) +#elif defined(CONFIG_CLK_600_150_75) + ldr r1, =0x812C0300 @ SDIV 0, PDIV 3, MDIV 300 (1200MHz) +#elif defined(CONFIG_CLK_533_133_66) + ldr r1, =0x810b0300 @ SDIV 0, PDIV 3, MDIV 267 (1066MHz) +#elif defined(CONFIG_CLK_500_166_66) + ldr r1, =0x81f40301 @ SDIV 1, PDIV 3, MDIV 500 (1000MHz) +#elif defined(CONFIG_CLK_467_117_59) + ldr r1, =0x826E0401 @ SDIV 1, PDIV 4, MDIV 622 (933MHz) +#elif defined(CONFIG_CLK_400_100_50) + ldr r1, =0x81900301 @ SDIV 1, PDIV 3, MDIV 400 (800MHz) +#else +#error you should set the correct clock configuration +#endif + ldr r1, =0x80C80601 + str r1, [r6, #0x100] + /* S5P_MPLL_CON */ + ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) + str r1, [r6, #0x108] + /* S5P_EPLL_CON */ + ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz) + str r1, [r6, #0x110] + /* S5P_VPLL_CON */ + ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96 + str r1, [r6, #0x120] +200: /* Set Clock divider */ - ldr r1, [r8, #0x300] + ldr r1, [r6, #0x300] ldr r2, =0x00003fff bic r1, r1, r2 #ifdef CONFIG_CLK_800_166_66 @@ -242,25 +285,17 @@ system_clock_init: ldr r2, =0x00011301 #endif orr r1, r1, r2 - str r1, [r8, #0x300] - ldr r1, [r8, #0x304] + str r1, [r6, #0x300] + ldr r1, [r6, #0x304] ldr r2, =0x00011110 orr r1, r1, r2 - str r1, [r8, #0x304] + str r1, [r6, #0x304] ldr r1, =0x00000001 - str r1, [r8, #0x308] + str r1, [r6, #0x308] /* Set Source Clock */ ldr r1, =0x1111 @ A, M, E, HPLL Muxing - str r1, [r8, #0x200] @ S5P_CLK_SRC0 - -#if 0 - ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing - str r1, [r8, #0x204] @ S5P_CLK_SRC1 - - ldr r1, =0x9000 @ ARMCLK/4 - str r1, [r8, #0x400] @ S5P_CLK_OUT -#endif + str r1, [r6, #0x200] @ S5P_CLK_SRC0 /* wait at least 200us to stablize all clock */ mov r2, #0x10000 diff --git a/board/samsung/universal/onenand.c b/board/samsung/universal/onenand.c index afe0090..67655b0 100644 --- a/board/samsung/universal/onenand.c +++ b/board/samsung/universal/onenand.c @@ -38,35 +38,35 @@ void onenand_board_init(struct mtd_info *mtd) this->base = (void *)0xB0000000; /* D0 Domain system 1 clock gating */ - value = readl(S5P_CLK_GATE_D00); + value = readl(S5P_CLOCK_BASE + S5P_CLK_GATE_D00_OFFSET); value &= ~(1 << 2); /* CFCON */ value |= (1 << 2); - writel(value, S5P_CLK_GATE_D00); + writel(value, S5P_CLOCK_BASE + S5P_CLK_GATE_D00_OFFSET); /* D0 Domain memory clock gating */ - value = readl(S5P_CLK_GATE_D01); + value = readl(S5P_CLOCK_BASE + S5P_CLK_GATE_D01_OFFSET); value &= ~(1 << 2); /* CLK_ONENANDC */ value |= (1 << 2); - writel(value, S5P_CLK_GATE_D01); + writel(value, S5P_CLOCK_BASE + S5P_CLK_GATE_D01_OFFSET); /* System Special clock gating */ - value = readl(S5P_CLK_GATE_SCLK0); + value = readl(S5P_CLOCK_BASE + S5P_CLK_GATE_SCLK0_OFFSET); value &= ~(1 << 2); /* OneNAND */ value |= (1 << 2); - writel(value, S5P_CLK_GATE_SCLK0); + writel(value, S5P_CLOCK_BASE + S5P_CLK_GATE_SCLK0_OFFSET); - value = readl(S5P_CLK_SRC0); + value = readl(S5P_CLOCK_BASE + S5P_CLK_SRC0_OFFSET); value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */ // value |= (1 << 24); /* MUX_1nand: 1 from DIV_D1_BUS */ value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */ - writel(value, S5P_CLK_SRC0); + writel(value, S5P_CLOCK_BASE + S5P_CLK_SRC0_OFFSET); - value = readl(S5P_CLK_DIV1); + value = readl(S5P_CLOCK_BASE + S5P_CLK_DIV1_OFFSET); // value &= ~(3 << 20); /* DIV_1nand: 1 / (ratio+1) */ // value |= (0 << 20); /* ratio = 1 */ value &= ~(3 << 16); value |= (1 << 16); - writel(value, S5P_CLK_DIV1); + writel(value, S5P_CLOCK_BASE + S5P_CLK_DIV1_OFFSET); if (cpu_is_s5pc100()) { onenand_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET); diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c index 93f52ad..f1839ec 100644 --- a/cpu/arm_cortexa8/s5pc1xx/clock.c +++ b/cpu/arm_cortexa8/s5pc1xx/clock.c @@ -38,6 +38,12 @@ #define MPLL 1 #define EPLL 2 #define HPLL 3 +#define VPLL 4 + +static int s5p1xx_clock_read_reg(int offset) +{ + return readl(S5P_CLOCK_BASE + offset); +} /* ------------------------------------------------------------------------- */ /* @@ -52,20 +58,36 @@ unsigned long get_pll_clk(int pllreg) { - unsigned long r, m, p, s, mask; + unsigned long r, m, p, s, mask, fout; switch (pllreg) { case APLL: - r = readl(S5P_APLL_CON); + if (cpu_is_s5pc110()) + r = s5p1xx_clock_read_reg(S5PC110_APLL_CON_OFFSET); + else + r = s5p1xx_clock_read_reg(S5PC100_APLL_CON_OFFSET); break; case MPLL: - r = readl(S5P_MPLL_CON); + if (cpu_is_s5pc110()) + r = s5p1xx_clock_read_reg(S5PC110_MPLL_CON_OFFSET); + else + r = s5p1xx_clock_read_reg(S5PC100_MPLL_CON_OFFSET); break; case EPLL: - r = readl(S5P_EPLL_CON); + if (cpu_is_s5pc110()) + r = s5p1xx_clock_read_reg(S5PC110_EPLL_CON_OFFSET); + else + r = s5p1xx_clock_read_reg(S5PC100_EPLL_CON_OFFSET); break; case HPLL: - r = readl(S5P_HPLL_CON); + if (cpu_is_s5pc110()) + hang(); + r = s5p1xx_clock_read_reg(S5PC100_HPLL_CON_OFFSET); + break; + case VPLL: + if (cpu_is_s5pc100()) + hang(); + r = s5p1xx_clock_read_reg(S5PC110_VPLL_CON_OFFSET); break; default: hang(); @@ -80,7 +102,17 @@ unsigned long get_pll_clk(int pllreg) p = (r >> 8) & 0x3f; s = r & 0x7; - return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s))); + if (cpu_is_s5pc110()) { + if (pllreg == APLL) + fout = m * CONFIG_SYS_CLK_FREQ / (p * (s * 2 - 1)); + else + fout = m * CONFIG_SYS_CLK_FREQ / (p * s * 2); + } + else { + fout = m * CONFIG_SYS_CLK_FREQ / (p * (1 << s)); + } + + return fout; } /* return ARMCORE frequency */ @@ -90,7 +122,7 @@ unsigned long get_arm_clk(void) unsigned long dout_apll, armclk; unsigned int apll_ratio, arm_ratio;; - div = readl(S5P_CLK_DIV0); + div = s5p1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); /* ARM_RATIO: [6:4] */ arm_ratio = (div >> 4) & 0x7; /* APLL_RATIO: [0] */ @@ -120,7 +152,7 @@ unsigned long get_hclk(void) unsigned long hclkd0; uint div, d0_bus_ratio; - div = readl(S5P_CLK_DIV0); + div = s5p1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); /* D0_BUS_RATIO: [10:8] */ d0_bus_ratio = (div >> 8) & 0x7; @@ -135,7 +167,7 @@ unsigned long get_pclkd0(void) unsigned long pclkd0; uint div, pclkd0_ratio; - div = readl(S5P_CLK_DIV0); + div = s5p1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); /* PCLKD0_RATIO: [14:12] */ pclkd0_ratio = (div >> 12) & 0x7; @@ -150,7 +182,7 @@ unsigned long get_pclk(void) unsigned long d1_bus, pclkd1; uint div, d1_bus_ratio, pclkd1_ratio; - div = readl(S5P_CLK_DIV1); + div = s5p1xx_clock_read_reg(S5P_CLK_DIV1_OFFSET); /* D1_BUS_RATIO: [14:12] */ d1_bus_ratio = (div >> 12) & 0x7; /* PCLKD1_RATIO: [18:16] */ diff --git a/include/asm-arm/arch-s5pc1xx/clock.h b/include/asm-arm/arch-s5pc1xx/clock.h index ba04fcc..94b0662 100644 --- a/include/asm-arm/arch-s5pc1xx/clock.h +++ b/include/asm-arm/arch-s5pc1xx/clock.h @@ -27,45 +27,55 @@ /* * Clock control */ -#define S5P_CLKREG(x) (S5P_PA_CLK + (x)) +#define S5P_CLOCK_BASE S5P_PA_CLK /* Clock Register */ -#define S5P_APLL_LOCK S5P_CLKREG(0x0) -#define S5P_MPLL_LOCK S5P_CLKREG(0x4) -#define S5P_EPLL_LOCK S5P_CLKREG(0x8) -#define S5P_HPLL_LOCK S5P_CLKREG(0xc) +#define S5PC100_APLL_LOCK_OFFSET 0x0 +#define S5PC100_MPLL_LOCK_OFFSET 0x4 +#define S5PC100_EPLL_LOCK_OFFSET 0x8 +#define S5PC100_HPLL_LOCK_OFFSET 0xc -#define S5P_APLL_CON S5P_CLKREG(0x100) -#define S5P_MPLL_CON S5P_CLKREG(0x104) -#define S5P_EPLL_CON S5P_CLKREG(0x108) -#define S5P_HPLL_CON S5P_CLKREG(0x10c) +#define S5PC100_APLL_CON_OFFSET 0x100 +#define S5PC100_MPLL_CON_OFFSET 0x104 +#define S5PC100_EPLL_CON_OFFSET 0x108 +#define S5PC100_HPLL_CON_OFFSET 0x10c -#define S5P_CLK_SRC0 S5P_CLKREG(0x200) -#define S5P_CLK_SRC1 S5P_CLKREG(0x204) -#define S5P_CLK_SRC2 S5P_CLKREG(0x208) -#define S5P_CLK_SRC3 S5P_CLKREG(0x20c) +#define S5PC110_APLL_LOCK_OFFSET 0x00 +#define S5PC110_MPLL_LOCK_OFFSET 0x08 +#define S5PC110_EPLL_LOCK_OFFSET 0x10 +#define S5PC110_VPLL_LOCK_OFFSET 0x20 -#define S5P_CLK_DIV0 S5P_CLKREG(0x300) -#define S5P_CLK_DIV1 S5P_CLKREG(0x304) -#define S5P_CLK_DIV2 S5P_CLKREG(0x308) -#define S5P_CLK_DIV3 S5P_CLKREG(0x30c) -#define S5P_CLK_DIV4 S5P_CLKREG(0x310) +#define S5PC110_APLL_CON_OFFSET 0x100 +#define S5PC110_MPLL_CON_OFFSET 0x108 +#define S5PC110_EPLL_CON_OFFSET 0x110 +#define S5PC110_VPLL_CON_OFFSET 0x120 -#define S5P_CLK_OUT S5P_CLKREG(0x400) +#define S5P_CLK_SRC0_OFFSET 0x200 +#define S5P_CLK_SRC1_OFFSET 0x204 +#define S5P_CLK_SRC2_OFFSET 0x208 +#define S5P_CLK_SRC3_OFFSET 0x20c -#define S5P_CLK_GATE_D00 S5P_CLKREG(0x500) -#define S5P_CLK_GATE_D01 S5P_CLKREG(0x504) -#define S5P_CLK_GATE_D02 S5P_CLKREG(0x508) +#define S5P_CLK_DIV0_OFFSET 0x300 +#define S5P_CLK_DIV1_OFFSET 0x304 +#define S5P_CLK_DIV2_OFFSET 0x308 +#define S5P_CLK_DIV3_OFFSET 0x30c +#define S5P_CLK_DIV4_OFFSET 0x310 -#define S5P_CLK_GATE_D10 S5P_CLKREG(0x520) -#define S5P_CLK_GATE_D11 S5P_CLKREG(0x524) -#define S5P_CLK_GATE_D12 S5P_CLKREG(0x528) -#define S5P_CLK_GATE_D13 S5P_CLKREG(0x530) -#define S5P_CLK_GATE_D14 S5P_CLKREG(0x534) +#define S5P_CLK_OUT_OFFSET 0x400 -#define S5P_CLK_GATE_D20 S5P_CLKREG(0x540) +#define S5P_CLK_GATE_D00_OFFSET 0x500 +#define S5P_CLK_GATE_D01_OFFSET 0x504 +#define S5P_CLK_GATE_D02_OFFSET 0x508 -#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x560) -#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x564) +#define S5P_CLK_GATE_D10_OFFSET 0x520 +#define S5P_CLK_GATE_D11_OFFSET 0x524 +#define S5P_CLK_GATE_D12_OFFSET 0x528 +#define S5P_CLK_GATE_D13_OFFSET 0x530 +#define S5P_CLK_GATE_D14_OFFSET 0x534 + +#define S5P_CLK_GATE_D20_OFFSET 0x540 + +#define S5P_CLK_GATE_SCLK0_OFFSET 0x560 +#define S5P_CLK_GATE_SCLK1_OFFSET 0x564 #endif