From: David Green <david.green@arm.com>
Date: Thu, 20 Jul 2023 08:12:05 +0000 (+0100)
Subject: [DAG][AArch64] Fix truncated vscale constant types
X-Git-Tag: upstream/17.0.6~1023
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0c41c59deebc25682f85175aa92e5fafa1c619ef;p=platform%2Fupstream%2Fllvm.git

[DAG][AArch64] Fix truncated vscale constant types

It appears that vscale values truncated to i1 causes mismatches in the constant
types when created in getNode. https://godbolt.org/z/TaaTo86ne.

Differential Revision: https://reviews.llvm.org/D155626
---

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index d00c6eb..5c1b19e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1942,10 +1942,8 @@ SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
 
 SDValue SelectionDAG::getVScale(const SDLoc &DL, EVT VT, APInt MulImm,
                                 bool ConstantFold) {
-  assert(MulImm.getSignificantBits() <= VT.getSizeInBits() &&
-         "Immediate does not fit VT");
-
-  MulImm = MulImm.sextOrTrunc(VT.getSizeInBits());
+  assert(MulImm.getBitWidth() == VT.getSizeInBits() &&
+         "APInt size does not match type size!");
 
   if (ConstantFold) {
     const MachineFunction &MF = getMachineFunction();
@@ -5751,7 +5749,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     if (OpOpcode == ISD::UNDEF)
       return getUNDEF(VT);
     if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes)
-      return getVScale(DL, VT, N1.getConstantOperandAPInt(0));
+      return getVScale(DL, VT,
+                       N1.getConstantOperandAPInt(0).trunc(VT.getSizeInBits()));
     break;
   case ISD::ANY_EXTEND_VECTOR_INREG:
   case ISD::ZERO_EXTEND_VECTOR_INREG:
diff --git a/llvm/test/CodeGen/AArch64/sve-vscale.ll b/llvm/test/CodeGen/AArch64/sve-vscale.ll
index 2b827e53..fa48808 100644
--- a/llvm/test/CodeGen/AArch64/sve-vscale.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vscale.ll
@@ -101,6 +101,17 @@ define i32 @rdvl_max() nounwind {
   ret i32 %1
 }
 
+define i1 @rdvl_i1() {
+; CHECK-LABEL: rdvl_i1:
+; CHECK:         rdvl x8, #-1
+; CHECK-NEXT:    asr x8, x8, #4
+; CHECK-NEXT:    and w0, w8, #0x1
+; CHECK-NEXT:    ret
+  %a = tail call i64 @llvm.vscale.i64()
+  %b = trunc i64 %a to i1
+  ret i1 %b
+}
+
 ;
 ; CNTH
 ;