From: Ville Syrjälä Date: Fri, 29 Nov 2013 12:56:12 +0000 (+0200) Subject: drm/i915: MI_PREDICATE_RESULT_2 is HSW only X-Git-Tag: upstream/snapshot3+hdmi~3760^2~7^2~9 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0bf2134780e321a8af93315d99e575a821ee1a77;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git drm/i915: MI_PREDICATE_RESULT_2 is HSW only The MI_PREDICATE_RESULT_2 register exits only on HSW. On other platforms the same offset is either reserved, or contains some other register. So write the register only on HSW. This regression has been introduced in commit 9435373ef8870e0a84b6fec0ad89b952bf3097fa Author: Rodrigo Vivi Date: Wed Aug 28 16:45:46 2013 -0300 drm/i915: Report enabled slices on Haswell GT3 Signed-off-by: Ville Syrjälä [danvet: Add regression notice.] Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 12bbd5e..621c7c6 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4442,10 +4442,9 @@ i915_gem_init_hw(struct drm_device *dev) if (dev_priv->ellc_size) I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); - if (IS_HSW_GT3(dev)) - I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); - else - I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + if (IS_HASWELL(dev)) + I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? + LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); if (HAS_PCH_NOP(dev)) { u32 temp = I915_READ(GEN7_MSG_CTL);