From: Jim Wilson <jimw@sifive.com>
Date: Thu, 22 Feb 2018 19:28:51 +0000 (-0800)
Subject: RISC-V: Make disassebler work for --enable-targets=all config.
X-Git-Tag: binutils-2_31~1230
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0bccfb2994d307601ceba5c3a6223b7ca7cf5338;p=external%2Fbinutils.git

RISC-V: Make disassebler work for --enable-targets=all config.

	opcodes/
	* disassemble.c (ARCH_riscv): Define if ARCH_all.
---

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b4b4cbb..325972f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2018-02-22  Shea Levy <shea@shealevy.com>
+
+	* disassemble.c (ARCH_riscv): Define if ARCH_all.
+
 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-opc.tbl: Add {rex},
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index ae48f536..78f0995 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -76,6 +76,7 @@
 #define ARCH_pj
 #define ARCH_powerpc
 #define ARCH_pru
+#define ARCH_riscv
 #define ARCH_rs6000
 #define ARCH_rl78
 #define ARCH_rx