From: Brad Bishop Date: Wed, 9 Sep 2020 22:28:53 +0000 (-0500) Subject: spi: fsi: Fix clock running too fast X-Git-Tag: v5.10.7~1093^2~79^2~4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0b546bbe9474ff23e6843916ad6d567f703b2396;p=platform%2Fkernel%2Flinux-rpi.git spi: fsi: Fix clock running too fast Use a clock divider tuned to a 200MHz FSI bus frequency (the maximum). Use of the previous divider at 200MHz results in corrupt data from endpoint devices. Ideally the clock divider would be calculated from the FSI clock, but that would require some significant work on the FSI driver. With FSI frequencies slower than 200MHz, the SPI clock will simply run slower, but safely. Signed-off-by: Brad Bishop Signed-off-by: Eddie James Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20200909222857.28653-3-eajames@linux.ibm.com Signed-off-by: Mark Brown --- diff --git a/drivers/spi/spi-fsi.c b/drivers/spi/spi-fsi.c index 8f64af0..559d0ff 100644 --- a/drivers/spi/spi-fsi.c +++ b/drivers/spi/spi-fsi.c @@ -350,7 +350,7 @@ static int fsi_spi_transfer_init(struct fsi_spi *ctx) u64 status = 0ULL; u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE | SPI_FSI_CLOCK_CFG_SCK_NO_DEL | - FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 4); + FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19); end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS); do {