From: Ian Romanick Date: Mon, 1 Aug 2022 23:42:57 +0000 (-0700) Subject: intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 reg size X-Git-Tag: upstream/23.3.3~1798 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0b23df395190101cb74164e562e63658762f2180;p=platform%2Fupstream%2Fmesa.git intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 reg size [ Francisco Jerez: Simplify. ] Reviewed-by: Caio Oliveira Reviewed-by: Jordan Justen Part-of: --- diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 388ece6..b875bc6 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -6987,7 +6987,7 @@ fs_visitor::run_vs() { assert(stage == MESA_SHADER_VERTEX); - payload_ = new vs_thread_payload(); + payload_ = new vs_thread_payload(*this); emit_nir_code(); diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 67b333f..2c2bb6b 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -98,7 +98,7 @@ protected: }; struct vs_thread_payload : public thread_payload { - vs_thread_payload(); + vs_thread_payload(const fs_visitor &v); fs_reg urb_handles; }; diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp index 3934d12..005fb09 100644 --- a/src/intel/compiler/brw_fs_thread_payload.cpp +++ b/src/intel/compiler/brw_fs_thread_payload.cpp @@ -25,11 +25,18 @@ using namespace brw; -vs_thread_payload::vs_thread_payload() +vs_thread_payload::vs_thread_payload(const fs_visitor &v) { - urb_handles = brw_ud8_grf(1, 0); + unsigned r = 0; + + /* R0: Thread header. */ + r += reg_unit(v.devinfo); - num_regs = 2; + /* R1: URB handles. */ + urb_handles = brw_ud8_grf(r, 0); + r += reg_unit(v.devinfo); + + num_regs = r; } tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)