From: Hyung-Kyu Choi <hk0110.choi@samsung.com>
Date: Fri, 7 Jul 2017 05:20:10 +0000 (+0900)
Subject: [RyuJIT/ARM32] Apply review feedback
X-Git-Tag: accepted/tizen/base/20180629.140029~1083^2~253^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0acd5abc5725353833f9d6fb14a6fd4290a6c1d4;p=platform%2Fupstream%2Fcoreclr.git

[RyuJIT/ARM32] Apply review feedback

Rename vairable and rewrite code to use less #ifdef

Signed-off-by: Hyung-Kyu Choi <hk0110.choi@samsung.com>
---

diff --git a/src/jit/lsra.cpp b/src/jit/lsra.cpp
index ae6a6b1..ddab7f9 100644
--- a/src/jit/lsra.cpp
+++ b/src/jit/lsra.cpp
@@ -5750,17 +5750,14 @@ regNumber LinearScan::tryAllocateFreeReg(Interval* currentInterval, RefPosition*
     {
         if (intervalToUnassign != nullptr)
         {
+            RegRecord* physRegToUnassign = availablePhysRegInterval;
 #ifdef _TARGET_ARM_
-            RegRecord* unassignedPhysReg = availablePhysRegInterval;
             // We should unassign a double register if availablePhysRegInterval is part of the double register
             if (availablePhysRegInterval->assignedInterval->registerType == TYP_DOUBLE &&
                 !genIsValidDoubleReg(availablePhysRegInterval->regNum))
-                unassignedPhysReg = findAnotherHalfRegRec(availablePhysRegInterval);
-
-            unassignPhysReg(unassignedPhysReg, intervalToUnassign->recentRefPosition);
-#else
-            unassignPhysReg(availablePhysRegInterval, intervalToUnassign->recentRefPosition);
+                physRegToUnassign = findAnotherHalfRegRec(availablePhysRegInterval);
 #endif
+            unassignPhysReg(physRegToUnassign, intervalToUnassign->recentRefPosition);
             if (bestScore & VALUE_AVAILABLE)
             {
                 assert(intervalToUnassign->isConstant);
@@ -5770,11 +5767,7 @@ regNumber LinearScan::tryAllocateFreeReg(Interval* currentInterval, RefPosition*
             // the next ref, remember it.
             else if ((bestScore & UNASSIGNED) != 0 && intervalToUnassign != nullptr)
             {
-#ifdef _TARGET_ARM_
-                updatePreviousInterval(unassignedPhysReg, intervalToUnassign, intervalToUnassign->registerType);
-#else
-                updatePreviousInterval(availablePhysRegInterval, intervalToUnassign, intervalToUnassign->registerType);
-#endif
+                updatePreviousInterval(physRegToUnassign, intervalToUnassign, intervalToUnassign->registerType);
             }
         }
         else