From: Krzysztof Parzyszek Date: Mon, 10 Jul 2017 18:31:02 +0000 (+0000) Subject: [Hexagon] Handle Hexagon-specific machine operand target flags in MIR X-Git-Tag: llvmorg-5.0.0-rc1~836 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0ac065f3184266322e1545982fa98eab832bf029;p=platform%2Fupstream%2Fllvm.git [Hexagon] Handle Hexagon-specific machine operand target flags in MIR llvm-svn: 307564 --- diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 1eac2d3..da4e5fb 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1726,6 +1726,39 @@ bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI, return false; } +std::pair +HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { + return std::make_pair(TF & ~HexagonII::MO_Bitmasks, + TF & HexagonII::MO_Bitmasks); +} + +ArrayRef> +HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { + using namespace HexagonII; + static const std::pair Flags[] = { + {MO_PCREL, "hexagon-pcrel"}, + {MO_GOT, "hexagon-got"}, + {MO_LO16, "hexagon-lo16"}, + {MO_HI16, "hexagon-hi16"}, + {MO_GPREL, "hexagon-gprel"}, + {MO_GDGOT, "hexagon-gdgot"}, + {MO_GDPLT, "hexagon-gdplt"}, + {MO_IE, "hexagon-ie"}, + {MO_IEGOT, "hexagon-iegot"}, + {MO_TPREL, "hexagon-tprel"} + }; + return makeArrayRef(Flags); +} + +ArrayRef> +HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const { + using namespace HexagonII; + static const std::pair Flags[] = { + {HMOTF_ConstExtended, "hexagon-ext"} + }; + return makeArrayRef(Flags); +} + unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const { MachineRegisterInfo &MRI = MF->getRegInfo(); const TargetRegisterClass *TRC; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 944d016..0436ce3 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -301,6 +301,27 @@ public: const MachineInstr &UseMI, unsigned UseIdx) const override; + /// Decompose the machine operand's target flags into two values - the direct + /// target flag value and any of bit flags that are applied. + std::pair + decomposeMachineOperandsTargetFlags(unsigned TF) const override; + + /// Return an array that contains the direct target flag values and their + /// names. + /// + /// MIR Serialization is able to serialize only the target flags that are + /// defined by this method. + ArrayRef> + getSerializableDirectMachineOperandTargetFlags() const override; + + /// Return an array that contains the bitmask target flag values and their + /// names. + /// + /// MIR Serialization is able to serialize only the target flags that are + /// defined by this method. + ArrayRef> + getSerializableBitmaskMachineOperandTargetFlags() const override; + bool isTailCall(const MachineInstr &MI) const override; /// HexagonInstrInfo specifics. diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index d8009c5..7f90e83 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -169,8 +169,11 @@ namespace HexagonII { // Hexagon specific MO operand flag mask. enum HexagonMOTargetFlagVal { - //===------------------------------------------------------------------===// - // Hexagon Specific MachineOperand flags. + // Hexagon-specific MachineOperand target flags. + // + // When chaning these, make sure to update + // getSerializableDirectMachineOperandTargetFlags and + // getSerializableBitmaskMachineOperandTargetFlags if needed. MO_NO_FLAG, /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation @@ -207,10 +210,12 @@ namespace HexagonII { MO_TPREL, // HMOTF_ConstExtended - // Addendum to abovem, indicates a const extended op + // Addendum to above, indicates a const extended op // Can be used as a mask. - HMOTF_ConstExtended = 0x80 + HMOTF_ConstExtended = 0x80, + // Union of all bitmasks (currently only HMOTF_ConstExtended). + MO_Bitmasks = HMOTF_ConstExtended }; // Hexagon Sub-instruction classes. diff --git a/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir b/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir new file mode 100644 index 0000000..656e0a6 --- /dev/null +++ b/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir @@ -0,0 +1,36 @@ +# RUN: llc -march=hexagon -run-pass none -o - %s | FileCheck %s +--- +name: fred + +body: | + bb.0: + + ; CHECK: target-flags(hexagon-pcrel) + %r0 = A2_tfrsi target-flags (hexagon-pcrel) 0 + ; CHECK: target-flags(hexagon-got) + %r0 = A2_tfrsi target-flags (hexagon-got) 0 + ; CHECK: target-flags(hexagon-lo16) + %r0 = A2_tfrsi target-flags (hexagon-lo16) 0 + ; CHECK: target-flags(hexagon-hi16) + %r0 = A2_tfrsi target-flags (hexagon-hi16) 0 + ; CHECK: target-flags(hexagon-gprel) + %r0 = A2_tfrsi target-flags (hexagon-gprel) 0 + ; CHECK: target-flags(hexagon-gdgot) + %r0 = A2_tfrsi target-flags (hexagon-gdgot) 0 + ; CHECK: target-flags(hexagon-gdplt) + %r0 = A2_tfrsi target-flags (hexagon-gdplt) 0 + ; CHECK: target-flags(hexagon-ie) + %r0 = A2_tfrsi target-flags (hexagon-ie) 0 + ; CHECK: target-flags(hexagon-iegot) + %r0 = A2_tfrsi target-flags (hexagon-iegot) 0 + ; CHECK: target-flags(hexagon-tprel) + %r0 = A2_tfrsi target-flags (hexagon-tprel) 0 + + ; CHECK: target-flags(hexagon-ext) + %r0 = A2_tfrsi target-flags (hexagon-ext) 0 + ; CHECK: target-flags(hexagon-pcrel, hexagon-ext) + %r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0 + ; CHECK: target-flags(hexagon-ie, hexagon-ext) + %r0 = A2_tfrsi target-flags (hexagon-ie,hexagon-ext) 0 +... +