From: H. Peter Anvin <hpa@zytor.com>
Date: Tue, 18 Sep 2007 00:27:46 +0000 (-0700)
Subject: insns.dat: All SSE5 instructions are AMD
X-Git-Tag: nasm-2.11.05~1956^2~4^2~19
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0a80739c46f2a6e7217c56f0b96248388a8ea1c9;p=platform%2Fupstream%2Fnasm.git

insns.dat: All SSE5 instructions are AMD

SSE5 is an AMD-defined instruction set, so tag those AMD.
---

diff --git a/insns.dat b/insns.dat
index 60bfa04..fcf0bec 100644
--- a/insns.dat
+++ b/insns.dat
@@ -2022,19 +2022,19 @@ POPCNT		reg32,rm32		\321\333\2\x0F\xB8\110		NEHALEM
 POPCNT		reg64,rm32		\324\333\2\x0F\xB8\110		NEHALEM,X64
 
 ; AMD SSE5 instructions
-FMSUBPS		xmmreg,=0,xmmreg,xmmrm	\160\3\x0F\x24\x08\132		SSE5
-FMSUBPS		xmmreg,=0,xmmrm,xmmreg	\164\3\x0F\x24\x08\123		SSE5
-FMSUBPS		xmmreg,xmmreg,xmmrm,=0	\160\3\x0F\x24\x0C\121		SSE5
-FMSUBPS		xmmreg,xmmrm,xmmreg,=0	\164\3\x0F\x24\x0C\112		SSE5
-FMSUBPD		xmmreg,=0,xmmreg,xmmrm	\160\3\x0F\x24\x09\132		SSE5
-FMSUBPD		xmmreg,=0,xmmrm,xmmreg	\164\3\x0F\x24\x09\123		SSE5
-FMSUBPD		xmmreg,xmmreg,xmmrm,=0	\160\3\x0F\x24\x0D\121		SSE5
-FMSUBPD		xmmreg,xmmrm,xmmreg,=0	\164\3\x0F\x24\x0D\112		SSE5
-FMSUBSS		xmmreg,=0,xmmreg,xmmrm	\160\3\x0F\x24\x0A\132		SSE5
-FMSUBSS		xmmreg,=0,xmmrm,xmmreg	\164\3\x0F\x24\x0A\123		SSE5
-FMSUBSS		xmmreg,xmmreg,xmmrm,=0	\160\3\x0F\x24\x0E\121		SSE5
-FMSUBSS		xmmreg,xmmrm,xmmreg,=0	\164\3\x0F\x24\x0E\112		SSE5
-FMSUBSD		xmmreg,=0,xmmreg,xmmrm	\160\3\x0F\x24\x0B\132		SSE5
-FMSUBSD		xmmreg,=0,xmmrm,xmmreg	\164\3\x0F\x24\x0B\123		SSE5
-FMSUBSD		xmmreg,xmmreg,xmmrm,=0	\160\3\x0F\x24\x0F\121		SSE5
-FMSUBSD		xmmreg,xmmrm,xmmreg,=0	\164\3\x0F\x24\x0F\112		SSE5
+FMSUBPS		xmmreg,=0,xmmreg,xmmrm	\160\3\x0F\x24\x08\132		SSE5,AMD
+FMSUBPS		xmmreg,=0,xmmrm,xmmreg	\164\3\x0F\x24\x08\123		SSE5,AMD
+FMSUBPS		xmmreg,xmmreg,xmmrm,=0	\160\3\x0F\x24\x0C\121		SSE5,AMD
+FMSUBPS		xmmreg,xmmrm,xmmreg,=0	\164\3\x0F\x24\x0C\112		SSE5,AMD
+FMSUBPD		xmmreg,=0,xmmreg,xmmrm	\160\3\x0F\x24\x09\132		SSE5,AMD
+FMSUBPD		xmmreg,=0,xmmrm,xmmreg	\164\3\x0F\x24\x09\123		SSE5,AMD
+FMSUBPD		xmmreg,xmmreg,xmmrm,=0	\160\3\x0F\x24\x0D\121		SSE5,AMD
+FMSUBPD		xmmreg,xmmrm,xmmreg,=0	\164\3\x0F\x24\x0D\112		SSE5,AMD
+FMSUBSS		xmmreg,=0,xmmreg,xmmrm	\160\3\x0F\x24\x0A\132		SSE5,AMD
+FMSUBSS		xmmreg,=0,xmmrm,xmmreg	\164\3\x0F\x24\x0A\123		SSE5,AMD
+FMSUBSS		xmmreg,xmmreg,xmmrm,=0	\160\3\x0F\x24\x0E\121		SSE5,AMD
+FMSUBSS		xmmreg,xmmrm,xmmreg,=0	\164\3\x0F\x24\x0E\112		SSE5,AMD
+FMSUBSD		xmmreg,=0,xmmreg,xmmrm	\160\3\x0F\x24\x0B\132		SSE5,AMD
+FMSUBSD		xmmreg,=0,xmmrm,xmmreg	\164\3\x0F\x24\x0B\123		SSE5,AMD
+FMSUBSD		xmmreg,xmmreg,xmmrm,=0	\160\3\x0F\x24\x0F\121		SSE5,AMD
+FMSUBSD		xmmreg,xmmrm,xmmreg,=0	\164\3\x0F\x24\x0F\112		SSE5,AMD