From: Matt Arsenault Date: Mon, 16 Sep 2019 00:29:12 +0000 (+0000) Subject: AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFP X-Git-Tag: llvmorg-11-init~9166 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0a6123595f97709af912690403dea841eced0f0a;p=platform%2Fupstream%2Fllvm.git AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFP llvm-svn: 371949 --- diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 5225475..1f610db 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -753,12 +753,12 @@ def : GCNPat < def : GCNPat < (f16 (sint_to_fp i32:$src)), - (V_CVT_F16_F32_e32 (V_CVT_F32_I32_e32 $src)) + (V_CVT_F16_F32_e32 (V_CVT_F32_I32_e32 VSrc_b32:$src)) >; def : GCNPat < (f16 (uint_to_fp i32:$src)), - (V_CVT_F16_F32_e32 (V_CVT_F32_U32_e32 $src)) + (V_CVT_F16_F32_e32 (V_CVT_F32_U32_e32 VSrc_b32:$src)) >; //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir index 8c8c40a..61608cf 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN --- @@ -6,27 +7,74 @@ name: sitofp legalized: true regBankSelected: true -# GCN-LABEL: name: sitofp body: | bb.0: liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4 - ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0 + ; GCN-LABEL: name: sitofp + ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0 + ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 + ; GCN: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec + ; GCN: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec + ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) + ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) %0:sgpr(s32) = COPY $sgpr0 - ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0 %2:vgpr(p1) = COPY $vgpr3_vgpr4 ; sitofp s - ; GCN: V_CVT_F32_I32_e64 [[SGPR]], 0, 0 %3:vgpr(s32) = G_SITOFP %0 ; sitofp v - ; GCN: V_CVT_F32_I32_e64 [[VGPR]], 0, 0 %4:vgpr(s32) = G_SITOFP %1 G_STORE %3, %2 :: (store 4, addrspace 1) G_STORE %4, %2 :: (store 4, addrspace 1) ... + +--- +name: sitofp_s32_to_s16_vv +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0 + + ; GCN-LABEL: name: sitofp_s32_to_s16_vv + ; GCN: liveins: $vgpr0 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec + ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec + ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s16) = G_SITOFP %0 + %2:vgpr(s32) = G_ANYEXT %1 + $vgpr0 = COPY %2 +... + +--- +name: sitofp_s32_to_s16_vs +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $sgpr0 + + ; GCN-LABEL: name: sitofp_s32_to_s16_vs + ; GCN: liveins: $sgpr0 + ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0 + ; GCN: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec + ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec + ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] + %0:sgpr(s32) = COPY $sgpr0 + %1:vgpr(s16) = G_SITOFP %0 + %2:vgpr(s32) = G_ANYEXT %1 + $vgpr0 = COPY %2 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir new file mode 100644 index 0000000..7e3dbaf --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir @@ -0,0 +1,86 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN + +--- +name: uitofp_s32_to_s32_vv +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0 + + ; GCN-LABEL: name: uitofp_s32_to_s32_vv + ; GCN: liveins: $vgpr0 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec + ; GCN: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = G_UITOFP %0 + $vgpr0 = COPY %1 +... + +--- +name: uitofp_s32_to_s32_vs +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $sgpr0 + + ; GCN-LABEL: name: uitofp_s32_to_s32_vs + ; GCN: liveins: $sgpr0 + ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0 + ; GCN: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec + ; GCN: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]] + %0:sgpr(s32) = COPY $sgpr0 + %1:vgpr(s32) = G_UITOFP %0 + $vgpr0 = COPY %1 +... + +--- +name: uitofp_s32_to_s16_vv +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0 + + ; GCN-LABEL: name: uitofp_s32_to_s16_vv + ; GCN: liveins: $vgpr0 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec + ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec + ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s16) = G_UITOFP %0 + %2:vgpr(s32) = G_ANYEXT %1 + $vgpr0 = COPY %2 +... + +--- +name: uitofp_s32_to_s16_vs +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $sgpr0 + + ; GCN-LABEL: name: uitofp_s32_to_s16_vs + ; GCN: liveins: $sgpr0 + ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0 + ; GCN: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec + ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec + ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] + %0:sgpr(s32) = COPY $sgpr0 + %1:vgpr(s16) = G_UITOFP %0 + %2:vgpr(s32) = G_ANYEXT %1 + $vgpr0 = COPY %2 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir index 8c4d9d0..5b9aa93 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir @@ -143,12 +143,12 @@ body: | ... --- -name: test_sitofp_s32_to_s16 +name: test_sitofp_s16_to_s32 body: | bb.0: liveins: $vgpr0 - ; CHECK-LABEL: name: test_sitofp_s32_to_s16 + ; CHECK-LABEL: name: test_sitofp_s16_to_s32 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[COPY]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir index 2ac82876..6fa7d44 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir @@ -112,12 +112,12 @@ body: | ... --- -name: test_uitofp_s32_to_s16 +name: test_uitofp_s16_to_s32 body: | bb.0: liveins: $vgpr0 - ; CHECK-LABEL: name: test_uitofp_s32_to_s16 + ; CHECK-LABEL: name: test_uitofp_s16_to_s32 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[COPY]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UITOFP]](s16)