From: Peter Chen Date: Tue, 16 Jul 2013 02:23:20 +0000 (+0800) Subject: ARM: imx: clk-pllv3: improve the timeout waiting method X-Git-Tag: upstream/snapshot3+hdmi~4405^2~6^2~14 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0a036388529477bcce01226a8ba901ef16333393;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git ARM: imx: clk-pllv3: improve the timeout waiting method There are two improvements for this commit: - Add comparing pll lock condition after while loop. It can fix potential fake timeout problem caused by the code is just scheduled out before compare the timeout, and the time of scheduling out are more than one jiffies. - Move timeout assignment more close to compare the timeout. It can reduce the possibility the code is scheduled out, and the timeout can be more precise. Signed-off-by: Peter Chen Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index a9fad5f..f6640b6 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -48,7 +48,7 @@ struct clk_pllv3 { static int clk_pllv3_prepare(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); - unsigned long timeout = jiffies + msecs_to_jiffies(10); + unsigned long timeout; u32 val; val = readl_relaxed(pll->base); @@ -59,12 +59,19 @@ static int clk_pllv3_prepare(struct clk_hw *hw) val &= ~BM_PLL_POWER; writel_relaxed(val, pll->base); + timeout = jiffies + msecs_to_jiffies(10); /* Wait for PLL to lock */ - while (!(readl_relaxed(pll->base) & BM_PLL_LOCK)) + do { + if (readl_relaxed(pll->base) & BM_PLL_LOCK) + break; if (time_after(jiffies, timeout)) - return -ETIMEDOUT; + break; + } while (1); - return 0; + if (readl_relaxed(pll->base) & BM_PLL_LOCK) + return 0; + else + return -ETIMEDOUT; } static void clk_pllv3_unprepare(struct clk_hw *hw)