From: Stephen Boyd <sboyd@codeaurora.org>
Date: Tue, 15 Nov 2016 02:38:35 +0000 (-0800)
Subject: Merge tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git... 
X-Git-Tag: v5.15~12045^2~38
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=09d5dc586be6549374c62422606f995ec5328cde;p=platform%2Fkernel%2Flinux-starfive.git

Merge tag 'v4.10-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next

Pull Rockchip clk driver updates from Heiko Stuebner:

PLL initialization for PLLs having both an integral and fractional mode
(rk3036, rk3399) does now take into account the mode that the PLL is
actually running at.

As always also some additional and optimized PLL rates for rk3066 and
rk3399, some additional clock ids for rk3066 and some additional clocks
on rk3399 are now sucessfully handled inside their respective driver.

* tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused
  clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree
  clk: rockchip: add 400MHz to rk3066 clock rates table
  clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399
  clk: rockchip: Use clock ids for cpu and peri clocks on rk3066
  clk: rockchip: Add binding ids for cpu and peri clocks on rk3066
  clk: rockchip: add 533.25MHz to rk3399 clock rates table
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09d5dc586be6549374c62422606f995ec5328cde