From: Paul Burton Date: Fri, 30 Jan 2015 12:09:34 +0000 (+0000) Subject: MIPS: clear MSACSR cause bits when handling MSA FP exception X-Git-Tag: v4.9.8~4429^2~1^2~5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=091be550a70a086c3b4420c6155e733dc410f190;p=platform%2Fkernel%2Flinux-rpi3.git MIPS: clear MSACSR cause bits when handling MSA FP exception Much like for traditional scalar FP exceptions, the cause bits in the MSACSR register need to be cleared following an MSA FP exception. Without doing so the exception will simply be raised again whenever the kernel restores MSACSR from a tasks saved context, leading to undesirable spurious exceptions. Clear the cause bits from the handle_msa_fpe function, mirroring the way handle_fpe clears the cause bits in FCSR. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9164/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 2ebaabe..86e2242 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -368,6 +368,15 @@ NESTED(nmi_handler, PT_SIZE, sp) STI .endm + .macro __build_clear_msa_fpe + _cfcmsa a1, MSA_CSR + li a2, ~(0x3f << 12) + and a1, a1, a2 + _ctcmsa MSA_CSR, a1 + TRACE_IRQS_ON + STI + .endm + .macro __build_clear_ade MFC0 t0, CP0_BADVADDR PTR_S t0, PT_BVADDR(sp) @@ -426,7 +435,7 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER cpu cpu sti silent /* #11 */ BUILD_HANDLER ov ov sti silent /* #12 */ BUILD_HANDLER tr tr sti silent /* #13 */ - BUILD_HANDLER msa_fpe msa_fpe sti silent /* #14 */ + BUILD_HANDLER msa_fpe msa_fpe msa_fpe silent /* #14 */ BUILD_HANDLER fpe fpe fpe silent /* #15 */ BUILD_HANDLER ftlb ftlb none silent /* #16 */ BUILD_HANDLER msa msa sti silent /* #21 */