From: Sanjay Patel <spatel@rotateright.com>
Date: Mon, 19 Nov 2018 15:34:09 +0000 (+0000)
Subject: [Hexagon] make test immune to improvements in undef simplification
X-Git-Tag: llvmorg-8.0.0-rc1~3950
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=08c0a0ac58764944adf5b116c82c2bc98ac6df1a;p=platform%2Fupstream%2Fllvm.git

[Hexagon] make test immune to improvements in undef simplification

llvm-svn: 347218
---

diff --git a/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll b/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll
index 86687b3..c795254 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll
@@ -9,11 +9,11 @@ target triple = "hexagon"
 @g0 = global <16 x float> zeroinitializer, align 8
 @g1 = global <16 x i32> zeroinitializer, align 8
 
-define void @fred() #0 {
+define void @fred(<16 x i16> %x) #0 {
 b0:
   %v1 = load <16 x float>, <16 x float>* @g0, align 8
   %v2 = fcmp olt <16 x float> undef, %v1
-  %v3 = select <16 x i1> %v2, <16 x i16> undef, <16 x i16> zeroinitializer
+  %v3 = select <16 x i1> %v2, <16 x i16> %x, <16 x i16> zeroinitializer
   %v4 = sext <16 x i16> %v3 to <16 x i32>
   store <16 x i32> %v4, <16 x i32>* @g1, align 64
   ret void