From: Timothy Arceri Date: Wed, 18 Oct 2017 22:27:04 +0000 (+1100) Subject: radv: copy indirect lowering settings from radeonsi X-Git-Tag: upstream/18.1.0~4966 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=087e010b2b3dd83a539f97203909d6c43b5da87c;p=platform%2Fupstream%2Fmesa.git radv: copy indirect lowering settings from radeonsi It looks the original indirect mask was probably copied from ANV. Sascha Willems demo results: tessellation ~4000 -> ~4200 fps V2: continue lowering local indirects due to llvm deficiencies. Tested-by: Alex Smith Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index a86ba2a..3688680 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -245,8 +245,33 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_shader_gather_info(nir, entry_point->impl); + /* While it would be nice not to have this flag, we are constrained + * by the reality that LLVM 5.0 doesn't have working VGPR indexing + * on GFX9. + */ + bool llvm_has_working_vgpr_indexing = + device->physical_device->rad_info.chip_class <= VI; + + /* TODO: Indirect indexing of GS inputs is unimplemented. + * + * TCS and TES load inputs directly from LDS or offchip memory, so + * indirect indexing is trivial. + */ nir_variable_mode indirect_mask = 0; - indirect_mask |= nir_var_shader_in; + if (nir->stage == MESA_SHADER_GEOMETRY || + (nir->stage != MESA_SHADER_TESS_CTRL && + nir->stage != MESA_SHADER_TESS_EVAL && + !llvm_has_working_vgpr_indexing)) { + indirect_mask |= nir_var_shader_in; + } + + /* TODO: We shouldn't need to do this, however LLVM isn't currently + * smart enough to handle indirects without causing excess spilling + * causing the gpu to hang. + * + * See the following thread for more details of the problem: + * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html + */ indirect_mask |= nir_var_local; nir_lower_indirect_derefs(nir, indirect_mask);