From: Xiang, Haihao Date: Tue, 9 Nov 2010 04:58:23 +0000 (+0800) Subject: i965_drv_video: H.264 decoding on Sandybridge X-Git-Tag: 1.0_branch~341 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=085eaf3bde30479a717708986b3a997bb1d34647;p=profile%2Fivi%2Fvaapi-intel-driver.git i965_drv_video: H.264 decoding on Sandybridge Signed-off-by: Xiang, Haihao --- diff --git a/Makefile.am b/Makefile.am index f32d579..8dd13bd 100644 --- a/Makefile.am +++ b/Makefile.am @@ -43,7 +43,8 @@ i965_drv_video_la_SOURCES = \ i965_avc_bsd.c \ i965_avc_hw_scoreboard.c\ i965_avc_ildb.c \ - i965_post_processing.c + i965_post_processing.c \ + gen6_mfd.c noinst_HEADERS = \ object_heap.h \ @@ -61,4 +62,5 @@ noinst_HEADERS = \ i965_avc_bsd.h \ i965_avc_hw_scoreboard.h\ i965_avc_ildb.h \ - i965_post_processing.h + i965_post_processing.h \ + gen6_mfd.h diff --git a/gen6_mfd.c b/gen6_mfd.c new file mode 100644 index 0000000..869f1fe --- /dev/null +++ b/gen6_mfd.c @@ -0,0 +1,1213 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Xiang Haihao + * + */ + +#include +#include +#include +#include + +#include + +#include "intel_batchbuffer.h" +#include "intel_driver.h" + +#include "i965_defines.h" +#include "i965_drv_video.h" + +#include "gen6_mfd.h" + +#define DMV_SIZE 0x88000 /* 557056 bytes for a frame */ + +static void +gen6_mfd_avc_frame_store_index(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct i965_media_state *media_state = &i965->media_state; + struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)media_state->private_context; + int i, j; + + assert(ARRAY_ELEMS(gen6_mfd_context->reference_surface) == ARRAY_ELEMS(pic_param->ReferenceFrames)); + + for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) { + int found = 0; + + if (gen6_mfd_context->reference_surface[i].surface_id == VA_INVALID_ID) + continue; + + for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) { + VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j]; + if (ref_pic->flags & VA_PICTURE_H264_INVALID) + continue; + + if (gen6_mfd_context->reference_surface[i].surface_id == ref_pic->picture_id) { + found = 1; + break; + } + } + + if (!found) { + struct object_surface *obj_surface = SURFACE(gen6_mfd_context->reference_surface[i].surface_id); + obj_surface->flags &= ~SURFACE_REFERENCED; + + if (obj_surface->flags & SURFACE_DISPLAYED) { + dri_bo_unreference(obj_surface->bo); + obj_surface->bo = NULL; + obj_surface->flags = 0; + } + + if (obj_surface->free_private_data) + obj_surface->free_private_data(&obj_surface->private_data); + + gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID; + gen6_mfd_context->reference_surface[i].frame_store_id = -1; + } + } + + for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) { + VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i]; + int found = 0; + + if (ref_pic->flags & VA_PICTURE_H264_INVALID) + continue; + + for (j = 0; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) { + if (gen6_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) + continue; + + if (gen6_mfd_context->reference_surface[j].surface_id == ref_pic->picture_id) { + found = 1; + break; + } + } + + if (!found) { + int frame_idx; + struct object_surface *obj_surface = SURFACE(ref_pic->picture_id); + + if (obj_surface->bo == NULL) { + /* Some broken sources such as conformance case FM2_SVA_C + * will get here !!!. Allocating a BO for it to avoid SEGMENT FAULT + */ + obj_surface->bo = dri_bo_alloc(i965->intel.bufmgr, + "vaapi surface", + obj_surface->size, + 0x1000); + } + + for (frame_idx = 0; frame_idx < ARRAY_ELEMS(gen6_mfd_context->reference_surface); frame_idx++) { + for (j = 0; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) { + if (gen6_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) + continue; + + if (gen6_mfd_context->reference_surface[j].frame_store_id == frame_idx) + break; + } + + if (j == ARRAY_ELEMS(gen6_mfd_context->reference_surface)) + break; + } + + assert(frame_idx < ARRAY_ELEMS(gen6_mfd_context->reference_surface)); + + for (j = 0; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) { + if (gen6_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) { + gen6_mfd_context->reference_surface[j].surface_id = ref_pic->picture_id; + gen6_mfd_context->reference_surface[j].frame_store_id = frame_idx; + break; + } + } + } + } + + /* sort */ + for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface) - 1; i++) { + if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && + gen6_mfd_context->reference_surface[i].frame_store_id == i) + continue; + + for (j = i + 1; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) { + if (gen6_mfd_context->reference_surface[j].surface_id != VA_INVALID_ID && + gen6_mfd_context->reference_surface[j].frame_store_id == i) { + VASurfaceID id = gen6_mfd_context->reference_surface[i].surface_id; + int frame_idx = gen6_mfd_context->reference_surface[i].frame_store_id; + + gen6_mfd_context->reference_surface[i].surface_id = gen6_mfd_context->reference_surface[j].surface_id; + gen6_mfd_context->reference_surface[i].frame_store_id = gen6_mfd_context->reference_surface[j].frame_store_id; + gen6_mfd_context->reference_surface[j].surface_id = id; + gen6_mfd_context->reference_surface[j].frame_store_id = frame_idx; + break; + } + } + } +} + +static void +gen6_mfd_free_mfx_surface(void **data) +{ + struct gen6_mfd_surface *gen6_mfd_surface = *data; + + if (!gen6_mfd_surface) + return; + + dri_bo_unreference(gen6_mfd_surface->dmv_top); + gen6_mfd_surface->dmv_top = NULL; + dri_bo_unreference(gen6_mfd_surface->dmv_bottom); + gen6_mfd_surface->dmv_bottom = NULL; + + free(gen6_mfd_surface); + *data = NULL; +} + +static void +gen6_mfd_init_mfx_surface(VADriverContextP ctx, + VAPictureParameterBufferH264 *pic_param, + struct object_surface *obj_surface) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct gen6_mfd_surface *gen6_mfd_surface = obj_surface->private_data; + + obj_surface->free_private_data = gen6_mfd_free_mfx_surface; + + if (!gen6_mfd_surface) { + gen6_mfd_surface = calloc(sizeof(struct gen6_mfd_surface), 1); + assert((obj_surface->size & 0x3f) == 0); + obj_surface->private_data = gen6_mfd_surface; + } + + gen6_mfd_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag && + !pic_param->seq_fields.bits.direct_8x8_inference_flag); + + if (gen6_mfd_surface->dmv_top == NULL) { + gen6_mfd_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr, + "direct mv w/r buffer", + DMV_SIZE, + 0x1000); + } + + if (gen6_mfd_surface->dmv_bottom_flag && + gen6_mfd_surface->dmv_bottom == NULL) { + gen6_mfd_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr, + "direct mv w/r buffer", + DMV_SIZE, + 0x1000); + } +} + +static void +gen6_mfd_pipe_mode_select(VADriverContextP ctx, + struct decode_state *decode_state, + int standard_select) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct i965_media_state *media_state = &i965->media_state; + struct gen6_mfd_context *gen6_mfd_context = media_state->private_context; + + assert(standard_select == MFX_FORMAT_MPEG2 || + standard_select == MFX_FORMAT_AVC || + standard_select == MFX_FORMAT_VC1); + + BEGIN_BCS_BATCH(ctx, 4); + OUT_BCS_BATCH(ctx, MFX_PIPE_MODE_SELECT | (4 - 2)); + OUT_BCS_BATCH(ctx, + (MFD_MODE_VLD << 16) | /* VLD mode */ + (0 << 10) | /* disable Stream-Out */ + (gen6_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */ + (gen6_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */ + (0 << 7) | /* disable TLB prefectch */ + (0 << 5) | /* not in stitch mode */ + (MFX_CODEC_DECODE << 4) | /* decoding mode */ + (standard_select << 0)); + OUT_BCS_BATCH(ctx, + (0 << 20) | /* round flag in PB slice */ + (0 << 19) | /* round flag in Intra8x8 */ + (0 << 7) | /* expand NOA bus flag */ + (1 << 6) | /* must be 1 */ + (0 << 5) | /* disable clock gating for NOA */ + (0 << 4) | /* terminate if AVC motion and POC table error occurs */ + (0 << 3) | /* terminate if AVC mbdata error occurs */ + (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ + (0 << 1) | /* AVC long field motion vector */ + (1 << 0)); /* always calculate AVC ILDB boundary strength */ + OUT_BCS_BATCH(ctx, 0); + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_surface_state(VADriverContextP ctx, + struct decode_state *decode_state, + int standard_select) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct object_surface *obj_surface = SURFACE(decode_state->current_render_target); + assert(obj_surface); + + BEGIN_BCS_BATCH(ctx, 6); + OUT_BCS_BATCH(ctx, MFX_SURFACE_STATE | (6 - 2)); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, + ((obj_surface->height - 1) << 19) | + ((obj_surface->width - 1) << 6)); + OUT_BCS_BATCH(ctx, + (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ + (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */ + (0 << 22) | /* surface object control state, FIXME??? */ + ((obj_surface->width - 1) << 3) | /* pitch */ + (0 << 2) | /* must be 0 for interleave U/V */ + (0 << 1) | /* tiled flag, FIXME: must be 1 ??? */ + (I965_TILEWALK_YMAJOR << 0)); /* tile walk, FIXME: must be 1 ??? */ + OUT_BCS_BATCH(ctx, + (0 << 16) | /* must be 0 for interleave U/V */ + (obj_surface->height)); /* y offset for U(cb) */ + OUT_BCS_BATCH(ctx, 0); + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_pipe_buf_addr_state(VADriverContextP ctx, + struct decode_state *decode_state, + int standard_select) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct i965_media_state *media_state = &i965->media_state; + struct gen6_mfd_context *gen6_mfd_context = media_state->private_context; + int i; + + BEGIN_BCS_BATCH(ctx, 24); + OUT_BCS_BATCH(ctx, MFX_PIPE_BUF_ADDR_STATE | (24 - 2)); + if (gen6_mfd_context->pre_deblocking_output.valid) + OUT_BCS_RELOC(ctx, gen6_mfd_context->pre_deblocking_output.bo, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + 0); + else + OUT_BCS_BATCH(ctx, 0); + + if (gen6_mfd_context->post_deblocking_output.valid) + OUT_BCS_RELOC(ctx, gen6_mfd_context->post_deblocking_output.bo, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + 0); + else + OUT_BCS_BATCH(ctx, 0); + + OUT_BCS_BATCH(ctx, 0); /* ignore for decoding */ + OUT_BCS_BATCH(ctx, 0); /* ignore for decoding */ + + if (gen6_mfd_context->intra_row_store_scratch_buffer.valid) + OUT_BCS_RELOC(ctx, gen6_mfd_context->intra_row_store_scratch_buffer.bo, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + 0); + else + OUT_BCS_BATCH(ctx, 0); + + OUT_BCS_RELOC(ctx, gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + 0); + + /* DW 7..22 */ + for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) { + struct object_surface *obj_surface; + + if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) { + obj_surface = SURFACE(gen6_mfd_context->reference_surface[i].surface_id); + assert(obj_surface && obj_surface->bo); + + OUT_BCS_RELOC(ctx, obj_surface->bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); + } else { + OUT_BCS_BATCH(ctx, 0); + } + } + + OUT_BCS_BATCH(ctx, 0); /* ignore DW23 for decoding */ + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_ind_obj_base_addr_state(VADriverContextP ctx, + struct decode_state *decode_state, + int standard_select) +{ + BEGIN_BCS_BATCH(ctx, 9); + OUT_BCS_BATCH(ctx, MFX_IND_OBJ_BASE_ADDR_STATE | (9 - 2)); + OUT_BCS_BATCH(ctx, 0); /* MFX Indirect Bitstream Object Base Address */ + OUT_BCS_BATCH(ctx, 0); /* ignore upper Bound check */ + OUT_BCS_BATCH(ctx, 0); /* ignore for VLD mode */ + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); /* ignore for VLD mode */ + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); /* ignore for VLD mode */ + OUT_BCS_BATCH(ctx, 0); + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx, + struct decode_state *decode_state, + int standard_select) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct i965_media_state *media_state = &i965->media_state; + struct gen6_mfd_context *gen6_mfd_context = media_state->private_context; + + BEGIN_BCS_BATCH(ctx, 4); + OUT_BCS_BATCH(ctx, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); + + if (gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid) + OUT_BCS_RELOC(ctx, gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + 0); + else + OUT_BCS_BATCH(ctx, 0); + + if (gen6_mfd_context->mpr_row_store_scratch_buffer.valid) + OUT_BCS_RELOC(ctx, gen6_mfd_context->mpr_row_store_scratch_buffer.bo, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + 0); + else + OUT_BCS_BATCH(ctx, 0); + + if (gen6_mfd_context->bitplane_read_buffer.valid) + OUT_BCS_RELOC(ctx, gen6_mfd_context->bitplane_read_buffer.bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); + else + OUT_BCS_BATCH(ctx, 0); + + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_aes_state(VADriverContextP ctx, + struct decode_state *decode_state, + int standard_select) +{ + /* FIXME */ +} + +static void +gen6_mfd_wait(VADriverContextP ctx, + struct decode_state *decode_state, + int standard_select) +{ + BEGIN_BCS_BATCH(ctx, 1); + OUT_BCS_BATCH(ctx, MFX_WAIT | (1 << 8)); + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_avc_img_state(VADriverContextP ctx, struct decode_state *decode_state) +{ + int qm_present_flag; + int img_struct; + int mbaff_frame_flag; + unsigned int width_in_mbs, height_in_mbs; + VAPictureParameterBufferH264 *pic_param; + + assert(decode_state->pic_param && decode_state->pic_param->buffer); + pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; + assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID)); + + if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) + qm_present_flag = 1; + else + qm_present_flag = 0; /* built-in QM matrices */ + + if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD) + img_struct = 1; + else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD) + img_struct = 3; + else + img_struct = 0; + + if ((img_struct & 0x1) == 0x1) { + assert(pic_param->pic_fields.bits.field_pic_flag == 0x1); + } else { + assert(pic_param->pic_fields.bits.field_pic_flag == 0x0); + } + + if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */ + assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0); + assert(pic_param->pic_fields.bits.field_pic_flag == 0); + } else { + assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */ + } + + mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag && + !pic_param->pic_fields.bits.field_pic_flag); + + width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff); + height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */ + assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */ + + /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */ + assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */ + pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */ + assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */ + + BEGIN_BCS_BATCH(ctx, 13); + OUT_BCS_BATCH(ctx, MFX_AVC_IMG_STATE | (13 - 2)); + OUT_BCS_BATCH(ctx, + ((width_in_mbs * height_in_mbs) & 0x7fff)); + OUT_BCS_BATCH(ctx, + (height_in_mbs << 16) | + (width_in_mbs << 0)); + OUT_BCS_BATCH(ctx, + ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) | + ((pic_param->chroma_qp_index_offset & 0x1f) << 16) | + (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */ + (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */ + (1 << 12) | /* always 1, hardware requirement */ + (qm_present_flag << 10) | + (img_struct << 8) | + (16 << 0)); + OUT_BCS_BATCH(ctx, + (pic_param->seq_fields.bits.chroma_format_idc << 10) | + (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) | + ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) | + (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) | + (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) | + (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) | + (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) | + (mbaff_frame_flag << 1) | + (pic_param->pic_fields.bits.field_pic_flag << 0)); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_avc_qm_state(VADriverContextP ctx, struct decode_state *decode_state) +{ + int cmd_len; + VAIQMatrixBufferH264 *iq_matrix; + VAPictureParameterBufferH264 *pic_param; + + if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer) + return; + + iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer; + + assert(decode_state->pic_param && decode_state->pic_param->buffer); + pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; + + cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */ + + if (pic_param->pic_fields.bits.transform_8x8_mode_flag) + cmd_len += 2 * 16; /* load two 8x8 scaling matrices */ + + BEGIN_BCS_BATCH(ctx, cmd_len); + OUT_BCS_BATCH(ctx, MFX_AVC_QM_STATE | (cmd_len - 2)); + + if (pic_param->pic_fields.bits.transform_8x8_mode_flag) + OUT_BCS_BATCH(ctx, + (0x0 << 8) | /* don't use default built-in matrices */ + (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */ + else + OUT_BCS_BATCH(ctx, + (0x0 << 8) | /* don't use default built-in matrices */ + (0x3f << 0)); /* six 4x4 scaling matrices */ + + intel_batchbuffer_data_bcs(ctx, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4); + + if (pic_param->pic_fields.bits.transform_8x8_mode_flag) + intel_batchbuffer_data_bcs(ctx, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4); + + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_avc_directmode_state(VADriverContextP ctx, + VAPictureParameterBufferH264 *pic_param, + VASliceParameterBufferH264 *slice_param) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct i965_media_state *media_state = &i965->media_state; + struct gen6_mfd_context *gen6_mfd_context = media_state->private_context; + struct object_surface *obj_surface; + struct gen6_mfd_surface *gen6_mfd_surface; + VAPictureH264 *va_pic; + int i, j; + + BEGIN_BCS_BATCH(ctx, 69); + OUT_BCS_BATCH(ctx, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); + + /* reference surfaces 0..15 */ + for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) { + if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) { + obj_surface = SURFACE(gen6_mfd_context->reference_surface[i].surface_id); + assert(obj_surface); + gen6_mfd_surface = obj_surface->private_data; + + if (gen6_mfd_surface == NULL) { + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + } else { + OUT_BCS_RELOC(ctx, gen6_mfd_surface->dmv_top, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); + + if (gen6_mfd_surface->dmv_bottom_flag == 1) + OUT_BCS_RELOC(ctx, gen6_mfd_surface->dmv_bottom, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); + else + OUT_BCS_RELOC(ctx, gen6_mfd_surface->dmv_top, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); + } + } else { + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + } + } + + /* the current decoding frame/field */ + va_pic = &pic_param->CurrPic; + assert(!(va_pic->flags & VA_PICTURE_H264_INVALID)); + obj_surface = SURFACE(va_pic->picture_id); + assert(obj_surface && obj_surface->bo && obj_surface->private_data); + gen6_mfd_surface = obj_surface->private_data; + + OUT_BCS_RELOC(ctx, gen6_mfd_surface->dmv_top, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + 0); + + if (gen6_mfd_surface->dmv_bottom_flag == 1) + OUT_BCS_RELOC(ctx, gen6_mfd_surface->dmv_bottom, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + 0); + else + OUT_BCS_RELOC(ctx, gen6_mfd_surface->dmv_top, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + 0); + + /* POC List */ + for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) { + if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) { + int found = 0; + for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) { + va_pic = &pic_param->ReferenceFrames[j]; + + if (va_pic->flags & VA_PICTURE_H264_INVALID) + continue; + + if (va_pic->picture_id == gen6_mfd_context->reference_surface[i].surface_id) { + found = 1; + break; + } + } + + assert(found == 1); + assert(!(va_pic->flags & VA_PICTURE_H264_INVALID)); + + OUT_BCS_BATCH(ctx, va_pic->TopFieldOrderCnt); + OUT_BCS_BATCH(ctx, va_pic->BottomFieldOrderCnt); + } else { + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + } + } + + va_pic = &pic_param->CurrPic; + OUT_BCS_BATCH(ctx, va_pic->TopFieldOrderCnt); + OUT_BCS_BATCH(ctx, va_pic->BottomFieldOrderCnt); + + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_avc_slice_state(VADriverContextP ctx, + VAPictureParameterBufferH264 *pic_param, + VASliceParameterBufferH264 *slice_param, + VASliceParameterBufferH264 *next_slice_param) +{ + int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; + int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; + int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos; + int num_ref_idx_l0, num_ref_idx_l1; + int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag && + pic_param->seq_fields.bits.mb_adaptive_frame_field_flag); + int weighted_pred_idc = 0; + int first_mb_in_slice = 0, first_mb_in_next_slice = 0; + int slice_type; + + if (slice_param->slice_type == SLICE_TYPE_I || + slice_param->slice_type == SLICE_TYPE_SI) { + slice_type = SLICE_TYPE_I; + } else if (slice_param->slice_type == SLICE_TYPE_P || + slice_param->slice_type == SLICE_TYPE_SP) { + slice_type = SLICE_TYPE_P; + } else { + assert(slice_param->slice_type == SLICE_TYPE_B); + slice_type = SLICE_TYPE_B; + } + + if (slice_type == SLICE_TYPE_I) { + assert(slice_param->num_ref_idx_l0_active_minus1 == 0); + assert(slice_param->num_ref_idx_l1_active_minus1 == 0); + num_ref_idx_l0 = 0; + num_ref_idx_l1 = 0; + } else if (slice_type == SLICE_TYPE_P) { + assert(slice_param->num_ref_idx_l1_active_minus1 == 0); + num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; + num_ref_idx_l1 = 0; + weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag; + } else { + num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; + num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; + weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc; + } + + first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture; + slice_hor_pos = first_mb_in_slice % width_in_mbs; + slice_ver_pos = first_mb_in_slice / width_in_mbs; + + if (next_slice_param) { + first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture; + next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs; + next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs; + } else { + next_slice_hor_pos = 0; + next_slice_ver_pos = height_in_mbs; + } + + BEGIN_BCS_BATCH(ctx, 11); /* FIXME: is it 10??? */ + OUT_BCS_BATCH(ctx, CMD_AVC_BSD_SLICE_STATE | (11 - 2)); + OUT_BCS_BATCH(ctx, slice_type); + OUT_BCS_BATCH(ctx, + (num_ref_idx_l1 << 24) | + (num_ref_idx_l0 << 16) | + (slice_param->chroma_log2_weight_denom << 8) | + (slice_param->luma_log2_weight_denom << 0)); + OUT_BCS_BATCH(ctx, + (weighted_pred_idc << 30) | + (slice_param->direct_spatial_mv_pred_flag << 29) | + (slice_param->disable_deblocking_filter_idc << 27) | + (slice_param->cabac_init_idc << 24) | + ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) | + ((slice_param->slice_beta_offset_div2 & 0xf) << 8) | + ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0)); + OUT_BCS_BATCH(ctx, + (slice_ver_pos << 24) | + (slice_hor_pos << 16) | + (first_mb_in_slice << 0)); + OUT_BCS_BATCH(ctx, + (next_slice_ver_pos << 16) | + (next_slice_hor_pos << 0)); + OUT_BCS_BATCH(ctx, + (next_slice_param == NULL) << 19); /* last slice flag */ + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_avc_phantom_slice_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param) +{ + int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; + int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */ + + BEGIN_BCS_BATCH(ctx, 11); /* FIXME: is it 10??? */ + OUT_BCS_BATCH(ctx, CMD_AVC_BSD_SLICE_STATE | (11 - 2)); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, + height_in_mbs << 24 | + width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag)); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_avc_ref_idx_state(VADriverContextP ctx, + VAPictureParameterBufferH264 *pic_param, + VASliceParameterBufferH264 *slice_param) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct i965_media_state *media_state = &i965->media_state; + struct gen6_mfd_context *gen6_mfd_context = media_state->private_context; + int i, j, num_ref_list; + struct { + unsigned char bottom_idc:1; + unsigned char frame_store_index:4; + unsigned char field_picture:1; + unsigned char long_term:1; + unsigned char non_exist:1; + } refs[32]; + + if (slice_param->slice_type == SLICE_TYPE_I || + slice_param->slice_type == SLICE_TYPE_SI) + return; + + if (slice_param->slice_type == SLICE_TYPE_P || + slice_param->slice_type == SLICE_TYPE_SP) { + num_ref_list = 1; + } else { + num_ref_list = 2; + } + + for (i = 0; i < num_ref_list; i++) { + VAPictureH264 *va_pic; + + if (i == 0) { + va_pic = slice_param->RefPicList0; + } else { + va_pic = slice_param->RefPicList1; + } + + BEGIN_BCS_BATCH(ctx, 10); + OUT_BCS_BATCH(ctx, MFX_AVC_REF_IDX_STATE | (10 - 2)); + OUT_BCS_BATCH(ctx, i); + + for (j = 0; j < 32; j++) { + if (va_pic->flags & VA_PICTURE_H264_INVALID) { + refs[j].non_exist = 1; + refs[j].long_term = 1; + refs[j].field_picture = 1; + refs[j].frame_store_index = 0xf; + refs[j].bottom_idc = 1; + } else { + int frame_idx; + + for (frame_idx = 0; frame_idx < ARRAY_ELEMS(gen6_mfd_context->reference_surface); frame_idx++) { + if (gen6_mfd_context->reference_surface[frame_idx].surface_id != VA_INVALID_ID && + va_pic->picture_id == gen6_mfd_context->reference_surface[frame_idx].surface_id) { + assert(frame_idx == gen6_mfd_context->reference_surface[frame_idx].frame_store_id); + break; + } + } + + assert(frame_idx < ARRAY_ELEMS(gen6_mfd_context->reference_surface)); + + refs[j].non_exist = 0; + refs[j].long_term = !!(va_pic->flags & VA_PICTURE_H264_LONG_TERM_REFERENCE); + refs[j].field_picture = !!(va_pic->flags & + (VA_PICTURE_H264_TOP_FIELD | + VA_PICTURE_H264_BOTTOM_FIELD)); + refs[j].frame_store_index = frame_idx; + refs[j].bottom_idc = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD); + } + + va_pic++; + } + + intel_batchbuffer_data_bcs(ctx, refs, sizeof(refs)); + ADVANCE_BCS_BATCH(ctx); + } +} + +static void +gen6_mfd_avc_weightoffset_state(VADriverContextP ctx, + VAPictureParameterBufferH264 *pic_param, + VASliceParameterBufferH264 *slice_param) +{ + int i, j, num_weight_offset_table = 0; + short weightoffsets[32 * 6]; + + if ((slice_param->slice_type == SLICE_TYPE_P || + slice_param->slice_type == SLICE_TYPE_SP) && + (pic_param->pic_fields.bits.weighted_pred_flag == 1)) { + num_weight_offset_table = 1; + } + + if ((slice_param->slice_type == SLICE_TYPE_B) && + (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) { + num_weight_offset_table = 2; + } + + for (i = 0; i < num_weight_offset_table; i++) { + BEGIN_BCS_BATCH(ctx, 98); + OUT_BCS_BATCH(ctx, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2)); + OUT_BCS_BATCH(ctx, i); + + if (i == 0) { + for (j = 0; j < 32; j++) { + weightoffsets[j * 6 + 0] = slice_param->luma_offset_l0[j]; + weightoffsets[j * 6 + 1] = slice_param->luma_weight_l0[j]; + weightoffsets[j * 6 + 2] = slice_param->chroma_offset_l0[j][0]; + weightoffsets[j * 6 + 3] = slice_param->chroma_weight_l0[j][0]; + weightoffsets[j * 6 + 4] = slice_param->chroma_offset_l0[j][1]; + weightoffsets[j * 6 + 5] = slice_param->chroma_weight_l0[j][1]; + } + } else { + for (j = 0; j < 32; j++) { + weightoffsets[j * 6 + 0] = slice_param->luma_offset_l1[j]; + weightoffsets[j * 6 + 1] = slice_param->luma_weight_l1[j]; + weightoffsets[j * 6 + 2] = slice_param->chroma_offset_l1[j][0]; + weightoffsets[j * 6 + 3] = slice_param->chroma_weight_l1[j][0]; + weightoffsets[j * 6 + 4] = slice_param->chroma_offset_l1[j][1]; + weightoffsets[j * 6 + 5] = slice_param->chroma_weight_l1[j][1]; + } + } + + intel_batchbuffer_data_bcs(ctx, weightoffsets, sizeof(weightoffsets)); + ADVANCE_BCS_BATCH(ctx); + } +} + +static int +gen6_mfd_avc_get_slice_bit_offset(uint8_t *buf, int mode_flag, int in_slice_data_bit_offset) +{ + int out_slice_data_bit_offset; + int slice_header_size = in_slice_data_bit_offset / 8; + int i, j; + + for (i = 0, j = 0; i < slice_header_size; i++, j++) { + if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3) { + i++, j += 2; + } + } + + out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8; + + if (mode_flag == ENTROPY_CABAC) + out_slice_data_bit_offset = ALIGN(out_slice_data_bit_offset, 0x8); + + return out_slice_data_bit_offset; +} + +static void +gen6_mfd_avc_bsd_object(VADriverContextP ctx, + VAPictureParameterBufferH264 *pic_param, + VASliceParameterBufferH264 *slice_param, + dri_bo *slice_data_bo) +{ + int slice_data_bit_offset; + uint8_t *slice_data = NULL; + + dri_bo_map(slice_data_bo, 0); + slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset); + slice_data_bit_offset = gen6_mfd_avc_get_slice_bit_offset(slice_data, + pic_param->pic_fields.bits.entropy_coding_mode_flag, + slice_param->slice_data_bit_offset); + dri_bo_unmap(slice_data_bo); + + BEGIN_BCS_BATCH(ctx, 6); + OUT_BCS_BATCH(ctx, MFD_AVC_BSD_OBJECT | (6 - 2)); + OUT_BCS_BATCH(ctx, + ((slice_param->slice_data_size - (slice_data_bit_offset >> 3)) << 0)); + OUT_BCS_RELOC(ctx, slice_data_bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + (slice_param->slice_data_offset + (slice_data_bit_offset >> 3))); + OUT_BCS_BATCH(ctx, + (0 << 31) | + (0 << 14) | + (0 << 12) | + (0 << 10) | + (0 << 8)); + OUT_BCS_BATCH(ctx, + (0 << 16) | + (0 << 6) | + ((0x7 - (slice_data_bit_offset & 0x7)) << 0)); + OUT_BCS_BATCH(ctx, 0); + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_avc_phantom_slice_bsd_object(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param) +{ + BEGIN_BCS_BATCH(ctx, 6); + OUT_BCS_BATCH(ctx, MFD_AVC_BSD_OBJECT | (6 - 2)); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + OUT_BCS_BATCH(ctx, 0); + ADVANCE_BCS_BATCH(ctx); +} + +static void +gen6_mfd_avc_phantom_slice(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param) +{ + gen6_mfd_avc_phantom_slice_state(ctx, pic_param); + gen6_mfd_avc_phantom_slice_bsd_object(ctx, pic_param); +} + +static void +gen6_mfd_avc_decode_init(VADriverContextP ctx, struct decode_state *decode_state) +{ + VAPictureParameterBufferH264 *pic_param; + VASliceParameterBufferH264 *slice_param; + VAPictureH264 *va_pic; + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct i965_media_state *media_state = &i965->media_state; + struct gen6_mfd_context *gen6_mfd_context; + struct object_surface *obj_surface; + dri_bo *bo; + int i, j, enable_avc_ildb = 0; + + for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) { + assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); + slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; + + assert(decode_state->slice_params[j]->num_elements == 1); + for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { + assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); + assert((slice_param->slice_type == SLICE_TYPE_I) || + (slice_param->slice_type == SLICE_TYPE_SI) || + (slice_param->slice_type == SLICE_TYPE_P) || + (slice_param->slice_type == SLICE_TYPE_SP) || + (slice_param->slice_type == SLICE_TYPE_B)); + + if (slice_param->disable_deblocking_filter_idc != 1) { + enable_avc_ildb = 1; + break; + } + + slice_param++; + } + } + + assert(decode_state->pic_param && decode_state->pic_param->buffer); + pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; + gen6_mfd_context = media_state->private_context; + + if (gen6_mfd_context == NULL) { + gen6_mfd_context = calloc(1, sizeof(struct gen6_mfd_context)); + media_state->private_context = gen6_mfd_context; + + for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) { + gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID; + gen6_mfd_context->reference_surface[i].frame_store_id = -1; + } + } + + /* Current decoded picture */ + va_pic = &pic_param->CurrPic; + assert(!(va_pic->flags & VA_PICTURE_H264_INVALID)); + obj_surface = SURFACE(va_pic->picture_id); + assert(obj_surface); + obj_surface->flags = (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0); + gen6_mfd_init_mfx_surface(ctx, pic_param, obj_surface); + + if (obj_surface->bo == NULL) { + obj_surface->bo = dri_bo_alloc(i965->intel.bufmgr, + "vaapi surface", + obj_surface->size, + 0x1000); + } + + dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo); + gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo; + dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo); + gen6_mfd_context->post_deblocking_output.valid = enable_avc_ildb; + + dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo); + gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo; + dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo); + gen6_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb; + + dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo); + bo = dri_bo_alloc(i965->intel.bufmgr, + "intra row store", + 128 * 64, + 0x1000); + assert(bo); + gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo; + gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1; + + dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); + bo = dri_bo_alloc(i965->intel.bufmgr, + "deblocking filter row store", + 4 * 64, + 0x1000); + assert(bo); + gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo; + gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1; + + dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); + bo = dri_bo_alloc(i965->intel.bufmgr, + "bsd mpc row store", + 11520, /* 1.5 * 120 * 64 */ + 0x1000); + assert(bo); + gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; + gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; + + dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo); + bo = dri_bo_alloc(i965->intel.bufmgr, + "mpr row store", + 7680, /* 1. 0 * 120 * 64 */ + 0x1000); + assert(bo); + gen6_mfd_context->mpr_row_store_scratch_buffer.bo = bo; + gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 1; + + gen6_mfd_avc_frame_store_index(ctx, pic_param); +} + +static void +gen6_mfd_avc_decode_picture(VADriverContextP ctx, struct decode_state *decode_state) +{ + VAPictureParameterBufferH264 *pic_param; + VASliceParameterBufferH264 *slice_param, *next_slice_param; + dri_bo *slice_data_bo; + int i, j; + + assert(decode_state->pic_param && decode_state->pic_param->buffer); + pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; + + gen6_mfd_avc_decode_init(ctx, decode_state); + intel_batchbuffer_start_atomic_bcs(ctx, 0x1000); + intel_batchbuffer_emit_mi_flush_bcs(ctx); + gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC); + gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC); + gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC); + gen6_mfd_ind_obj_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC); + gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC); + gen6_mfd_avc_img_state(ctx, decode_state); + gen6_mfd_avc_qm_state(ctx, decode_state); + + for (j = 0; j < decode_state->num_slice_params; j++) { + assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); + slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; + slice_data_bo = decode_state->slice_datas[j]->bo; + + if (j == decode_state->num_slice_params - 1) + next_slice_param = NULL; + else + next_slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer; + + assert(decode_state->slice_params[j]->num_elements == 1); + for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { + assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); + assert((slice_param->slice_type == SLICE_TYPE_I) || + (slice_param->slice_type == SLICE_TYPE_SI) || + (slice_param->slice_type == SLICE_TYPE_P) || + (slice_param->slice_type == SLICE_TYPE_SP) || + (slice_param->slice_type == SLICE_TYPE_B)); + + if (i < decode_state->slice_params[j]->num_elements - 1) + next_slice_param = slice_param + 1; + + gen6_mfd_avc_directmode_state(ctx, pic_param, slice_param); + gen6_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param); + gen6_mfd_avc_ref_idx_state(ctx, pic_param, slice_param); + gen6_mfd_avc_weightoffset_state(ctx, pic_param, slice_param); + gen6_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo); + slice_param++; + } + } + + gen6_mfd_avc_phantom_slice(ctx, pic_param); + intel_batchbuffer_end_atomic_bcs(ctx); + intel_batchbuffer_flush_bcs(ctx); +} + +static void +gen6_mfd_mpeg2_decode_picture(VADriverContextP ctx, struct decode_state *decode_state) +{ + +} + +static void +gen6_mfd_vc1_decode_picture(VADriverContextP ctx, struct decode_state *decode_state) +{ + +} + +void +gen6_mfd_decode_picture(VADriverContextP ctx, + VAProfile profile, + struct decode_state *decode_state) +{ + switch (profile) { + case VAProfileMPEG2Simple: + case VAProfileMPEG2Main: + gen6_mfd_mpeg2_decode_picture(ctx, decode_state); + break; + + case VAProfileH264Baseline: + case VAProfileH264Main: + case VAProfileH264High: + gen6_mfd_avc_decode_picture(ctx, decode_state); + break; + + case VAProfileVC1Simple: + case VAProfileVC1Main: + case VAProfileVC1Advanced: + gen6_mfd_vc1_decode_picture(ctx, decode_state); + break; + + default: + assert(0); + break; + } +} + +Bool +gen6_mfd_init(VADriverContextP ctx) +{ + return True; +} + +Bool +gen6_mfd_terminate(VADriverContextP ctx) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct i965_media_state *media_state = &i965->media_state; + struct gen6_mfd_context *gen6_mfd_context = media_state->private_context; + + dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo); + gen6_mfd_context->post_deblocking_output.bo = NULL; + + dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo); + gen6_mfd_context->pre_deblocking_output.bo = NULL; + + dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo); + gen6_mfd_context->intra_row_store_scratch_buffer.bo = NULL; + + dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); + gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; + + dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); + gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; + + dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo); + gen6_mfd_context->mpr_row_store_scratch_buffer.bo = NULL; + + dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo); + gen6_mfd_context->bitplane_read_buffer.bo = NULL; + + return True; +} + diff --git a/gen6_mfd.h b/gen6_mfd.h new file mode 100644 index 0000000..dba1d07 --- /dev/null +++ b/gen6_mfd.h @@ -0,0 +1,95 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Xiang Haihao + * + */ + +#ifndef _GEN6_MFD_H_ +#define _GEN6_MFD_H_ + +#include +#include +#include +#include + +struct gen6_mfd_surface +{ + dri_bo *dmv_top; + dri_bo *dmv_bottom; + int dmv_bottom_flag; +}; + +#define MAX_MFX_REFERENCE_SURFACES 16 +struct gen6_mfd_context +{ + struct { + VASurfaceID surface_id; + int frame_store_id; + } reference_surface[MAX_MFX_REFERENCE_SURFACES]; + + struct { + dri_bo *bo; + int valid; + } post_deblocking_output; + + struct { + dri_bo *bo; + int valid; + } pre_deblocking_output; + + struct { + dri_bo *bo; + int valid; + } intra_row_store_scratch_buffer; + + struct { + dri_bo *bo; + int valid; + } deblocking_filter_row_store_scratch_buffer; + + struct { + dri_bo *bo; + int valid; + } bsd_mpc_row_store_scratch_buffer; + + struct { + dri_bo *bo; + int valid; + } mpr_row_store_scratch_buffer; + + struct { + dri_bo *bo; + int valid; + } bitplane_read_buffer; +}; + +struct decode_state; + +Bool gen6_mfd_init(VADriverContextP ctx); +Bool gen6_mfd_terminate(VADriverContextP ctx); +void gen6_mfd_decode_picture(VADriverContextP ctx, + VAProfile profile, + struct decode_state *decode_state); +#endif /* _GEN6_MFD_H_ */ diff --git a/i965_defines.h b/i965_defines.h index 4cf591d..d743688 100644 --- a/i965_defines.h +++ b/i965_defines.h @@ -44,13 +44,14 @@ (sub_opa) << 21 | \ (sub_opb) << 16) -#define MFX_STATE_PONTER MFX(2, 0, 0, 6) #define MFX_PIPE_MODE_SELECT MFX(2, 0, 0, 0) -#define MFX_SURFACE_STATE MFX(0, 0, 0, 2) /* FIXME: right ? */ +#define MFX_SURFACE_STATE MFX(2, 0, 0, 1) #define MFX_PIPE_BUF_ADDR_STATE MFX(2, 0, 0, 2) #define MFX_IND_OBJ_BASE_ADDR_STATE MFX(2, 0, 0, 3) #define MFX_BSP_BUF_BASE_ADDR_STATE MFX(2, 0, 0, 4) #define MFX_AES_STATE MFX(2, 0, 0, 5) +#define MFX_STATE_POINTER MFX(2, 0, 0, 6) + #define MFX_WAIT MFX(1, 0, 0, 0) #define MFX_AVC_IMG_STATE MFX(2, 1, 0, 0) diff --git a/i965_drv_video.c b/i965_drv_video.c index 18e2196..0a4a265 100644 --- a/i965_drv_video.c +++ b/i965_drv_video.c @@ -119,6 +119,7 @@ i965_QueryConfigProfiles(VADriverContextP ctx, VAProfile *profile_list, /* out */ int *num_profiles) /* out */ { + struct i965_driver_data *i965 = i965_driver_data(ctx); int i = 0; profile_list[i++] = VAProfileMPEG2Simple; @@ -127,6 +128,12 @@ i965_QueryConfigProfiles(VADriverContextP ctx, profile_list[i++] = VAProfileH264Main; profile_list[i++] = VAProfileH264High; + if (IS_GEN6(i965->intel.device_id)) { + profile_list[i++] = VAProfileVC1Simple; + profile_list[i++] = VAProfileVC1Main; + profile_list[i++] = VAProfileVC1Advanced; + } + /* If the assert fails then I965_MAX_PROFILES needs to be bigger */ assert(i <= I965_MAX_PROFILES); *num_profiles = i; @@ -156,6 +163,13 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx, entrypoint_list[0] = VAEntrypointVLD; break; + case VAProfileVC1Simple: + case VAProfileVC1Main: + case VAProfileVC1Advanced: + *num_entrypoints = 1; + entrypoint_list[0] = VAEntrypointVLD; + break; + default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; *num_entrypoints = 0; @@ -262,6 +276,17 @@ i965_CreateConfig(VADriverContextP ctx, break; + case VAProfileVC1Simple: + case VAProfileVC1Main: + case VAProfileVC1Advanced: + if (VAEntrypointVLD == entrypoint) { + vaStatus = VA_STATUS_SUCCESS; + } else { + vaStatus = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT; + } + + break; + default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; break; @@ -724,14 +749,18 @@ i965_CreateContext(VADriverContextP ctx, return vaStatus; } - switch (obj_config->profile) { - case VAProfileH264Baseline: - case VAProfileH264Main: - case VAProfileH264High: + if (IS_GEN6(i965->intel.device_id)) render_state->interleaved_uv = 1; - break; - default: - render_state->interleaved_uv = 0; + else { + switch (obj_config->profile) { + case VAProfileH264Baseline: + case VAProfileH264Main: + case VAProfileH264High: + render_state->interleaved_uv = 1; + break; + default: + render_state->interleaved_uv = 0; + } } obj_context->context_id = contextID; @@ -978,6 +1007,12 @@ i965_BeginPicture(VADriverContextP ctx, vaStatus = VA_STATUS_SUCCESS; break; + case VAProfileVC1Simple: + case VAProfileVC1Main: + case VAProfileVC1Advanced: + vaStatus = VA_STATUS_SUCCESS; + break; + default: assert(0); vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; diff --git a/i965_media.c b/i965_media.c index 036c452..172dde5 100644 --- a/i965_media.c +++ b/i965_media.c @@ -39,6 +39,7 @@ #include "i965_defines.h" #include "i965_media_mpeg2.h" #include "i965_media_h264.h" +#include "gen6_mfd.h" #include "i965_media.h" #include "i965_drv_video.h" @@ -273,6 +274,11 @@ i965_media_decode_picture(VADriverContextP ctx, struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_media_state *media_state = &i965->media_state; + if (IS_GEN6(i965->intel.device_id)) { + gen6_mfd_decode_picture(ctx, profile, decode_state); + return; + } + i965_media_decode_init(ctx, profile, decode_state); assert(media_state->media_states_setup); media_state->media_states_setup(ctx, decode_state); @@ -282,6 +288,11 @@ i965_media_decode_picture(VADriverContextP ctx, Bool i965_media_init(VADriverContextP ctx) { + struct i965_driver_data *i965 = i965_driver_data(ctx); + + if (IS_GEN6(i965->intel.device_id)) + return gen6_mfd_init(ctx); + return True; } @@ -292,6 +303,9 @@ i965_media_terminate(VADriverContextP ctx) struct i965_media_state *media_state = &i965->media_state; int i; + if (IS_GEN6(i965->intel.device_id)) + return gen6_mfd_terminate(ctx); + if (media_state->free_private_context) media_state->free_private_context(&media_state->private_context);