From: Jesse Natalie Date: Mon, 12 Jun 2023 21:26:24 +0000 (-0700) Subject: nir_lower_mem_access_bit_sizes: Move options into a struct X-Git-Tag: upstream/23.3.3~7138 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=082eba61653d2989800bdb034bdfacfadf3ebf18;p=platform%2Fupstream%2Fmesa.git nir_lower_mem_access_bit_sizes: Move options into a struct Reviewed-by: Alyssa Rosenzweig Part-of: --- diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index dcc6b15..5ccb9c7 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -2379,12 +2379,13 @@ agx_compile_shader_nir(nir_shader *nir, struct agx_shader_key *key, out->tag_write_disable = true; /* Late sysval lowering creates large loads. Load lowering creates unpacks */ - NIR_PASS_V(nir, nir_lower_mem_access_bit_sizes, - nir_var_mem_ssbo | nir_var_mem_constant | - nir_var_mem_task_payload | nir_var_shader_temp | - nir_var_function_temp | nir_var_mem_global | - nir_var_mem_shared, - mem_access_size_align_cb, NULL); + nir_lower_mem_access_bit_sizes_options lower_mem_access_options = { + .modes = nir_var_mem_ssbo | nir_var_mem_constant | + nir_var_mem_task_payload | nir_var_shader_temp | + nir_var_function_temp | nir_var_mem_global | nir_var_mem_shared, + .callback = mem_access_size_align_cb, + }; + NIR_PASS_V(nir, nir_lower_mem_access_bit_sizes, &lower_mem_access_options); NIR_PASS_V(nir, nir_lower_pack); /* Late blend lowering creates vectors */ diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index b8d0fce..0fa2107 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -5112,10 +5112,14 @@ typedef nir_mem_access_size_align bool offset_is_const, const void *cb_data); +typedef struct { + nir_lower_mem_access_bit_sizes_cb callback; + nir_variable_mode modes; + void *cb_data; +} nir_lower_mem_access_bit_sizes_options; + bool nir_lower_mem_access_bit_sizes(nir_shader *shader, - nir_variable_mode modes, - nir_lower_mem_access_bit_sizes_cb cb, - const void *cb_data); + const nir_lower_mem_access_bit_sizes_options *options); typedef bool (*nir_should_vectorize_mem_func)(unsigned align_mul, unsigned align_offset, diff --git a/src/compiler/nir/nir_lower_mem_access_bit_sizes.c b/src/compiler/nir/nir_lower_mem_access_bit_sizes.c index 3939ad4..55613e5 100644 --- a/src/compiler/nir/nir_lower_mem_access_bit_sizes.c +++ b/src/compiler/nir/nir_lower_mem_access_bit_sizes.c @@ -317,12 +317,6 @@ lower_mem_store(nir_builder *b, nir_intrinsic_instr *intrin, return true; } -struct lower_mem_access_state { - nir_variable_mode modes; - nir_lower_mem_access_bit_sizes_cb cb; - const void *cb_data; -}; - static nir_variable_mode intrin_to_variable_mode(nir_intrinsic_op intrin) { @@ -361,7 +355,7 @@ intrin_to_variable_mode(nir_intrinsic_op intrin) static bool lower_mem_access_instr(nir_builder *b, nir_instr *instr, void *_data) { - struct lower_mem_access_state *state = _data; + const nir_lower_mem_access_bit_sizes_options *state = _data; if (instr->type != nir_instr_type_intrinsic) return false; @@ -380,14 +374,14 @@ lower_mem_access_instr(nir_builder *b, nir_instr *instr, void *_data) case nir_intrinsic_load_shared: case nir_intrinsic_load_scratch: case nir_intrinsic_load_task_payload: - return lower_mem_load(b, intrin, state->cb, state->cb_data); + return lower_mem_load(b, intrin, state->callback, state->cb_data); case nir_intrinsic_store_global: case nir_intrinsic_store_ssbo: case nir_intrinsic_store_shared: case nir_intrinsic_store_scratch: case nir_intrinsic_store_task_payload: - return lower_mem_store(b, intrin, state->cb, state->cb_data); + return lower_mem_store(b, intrin, state->callback, state->cb_data); default: return false; @@ -396,18 +390,10 @@ lower_mem_access_instr(nir_builder *b, nir_instr *instr, void *_data) bool nir_lower_mem_access_bit_sizes(nir_shader *shader, - nir_variable_mode modes, - nir_lower_mem_access_bit_sizes_cb cb, - const void *cb_data) + const nir_lower_mem_access_bit_sizes_options *options) { - struct lower_mem_access_state state = { - .modes = modes, - .cb = cb, - .cb_data = cb_data - }; - return nir_shader_instructions_pass(shader, lower_mem_access_instr, nir_metadata_block_index | nir_metadata_dominance, - (void *)&state); + (void *)options); } diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index ef174ff..60a6194 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1495,15 +1495,17 @@ brw_vectorize_lower_mem_access(nir_shader *nir, } } - OPT(nir_lower_mem_access_bit_sizes, - nir_var_mem_ssbo | - nir_var_mem_constant | - nir_var_mem_task_payload | - nir_var_shader_temp | - nir_var_function_temp | - nir_var_mem_global | - nir_var_mem_shared, - get_mem_access_size_align, NULL); + nir_lower_mem_access_bit_sizes_options mem_access_options = { + .modes = nir_var_mem_ssbo | + nir_var_mem_constant | + nir_var_mem_task_payload | + nir_var_shader_temp | + nir_var_function_temp | + nir_var_mem_global | + nir_var_mem_shared, + .callback = get_mem_access_size_align, + }; + OPT(nir_lower_mem_access_bit_sizes, &mem_access_options); while (progress) { progress = false; diff --git a/src/panfrost/compiler/bifrost_compile.c b/src/panfrost/compiler/bifrost_compile.c index a13557b..d925aff 100644 --- a/src/panfrost/compiler/bifrost_compile.c +++ b/src/panfrost/compiler/bifrost_compile.c @@ -4726,12 +4726,13 @@ bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id) NIR_PASS_V(nir, pan_nir_lower_store_component); } - NIR_PASS_V(nir, nir_lower_mem_access_bit_sizes, - nir_var_mem_ubo | nir_var_mem_ssbo | nir_var_mem_constant | - nir_var_mem_task_payload | nir_var_shader_temp | - nir_var_function_temp | nir_var_mem_global | - nir_var_mem_shared, - mem_access_size_align_cb, NULL); + nir_lower_mem_access_bit_sizes_options mem_size_options = { + .modes = nir_var_mem_ubo | nir_var_mem_ssbo | nir_var_mem_constant | + nir_var_mem_task_payload | nir_var_shader_temp | + nir_var_function_temp | nir_var_mem_global | nir_var_mem_shared, + .callback = mem_access_size_align_cb, + }; + NIR_PASS_V(nir, nir_lower_mem_access_bit_sizes, &mem_size_options); NIR_PASS_V(nir, nir_lower_ssbo); NIR_PASS_V(nir, pan_lower_sample_pos);