From: Wolfgang Grandegger Date: Wed, 11 Feb 2009 17:38:25 +0000 (+0100) Subject: MPC85xx: TQM8548: use cache for AG and BE variants X-Git-Tag: v2009.03-rc1~57 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=080408fdc71706adcb883d22125637c54f6010b1;p=platform%2Fkernel%2Fu-boot.git MPC85xx: TQM8548: use cache for AG and BE variants This patch makes accesses to the system memory cachable by removing the caching-inhibited and guarded flags from the relevant TLB entries for the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards are configured similarly. This results in a big averall performace improvement. TFTP downloads, NAND Flash accesses, kernel boots, etc. are much faster. Signed-off-by: Wolfgang Grandegger --- diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index ad96dd1..71fe3ab 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -128,12 +128,12 @@ struct fsl_e_tlb_entry tlb_table[] = { * Without SPD EEPROM configured DDR, this must be setup manually. */ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_1G, 1), SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), #else /*