From: Russell King Date: Tue, 25 Oct 2011 07:19:29 +0000 (+0100) Subject: Merge branches 'arnd-randcfg-fixes', 'debug', 'io' (early part), 'l2x0', 'p2v', ... X-Git-Tag: v3.2-rc1~189^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=06afb1a087d49ae0f676b2e5b9ffe5f4b3aba355;p=profile%2Fcommon%2Fkernel-common.git Merge branches 'arnd-randcfg-fixes', 'debug', 'io' (early part), 'l2x0', 'p2v', 'pgt' (early part) and 'smp' into for-linus --- 06afb1a087d49ae0f676b2e5b9ffe5f4b3aba355 diff --cc arch/arm/Kconfig index 3146ed3,ed69fcd,3269576,2c71a8f,3269576,272eadc,5ebc5d9,c208fd9..380e4f0 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@@@@@@@@ -195,7 -195,7 -195,7 -195,8 -195,7 -195,8 -195,7 -195,7 +195,8 @@@@@@@@@ config VECTORS_BAS The base address of exception vectors. config ARM_PATCH_PHYS_VIRT --- - -- bool "Patch physical to virtual translations at runtime" - bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)" - depends on EXPERIMENTAL +++++ ++ bool "Patch physical to virtual translations at runtime" if EMBEDDED +++++ ++ default y depends on !XIP_KERNEL && MMU depends on !ARCH_REALVIEW || !SPARSEMEM help @@@@@@@@@ -1271,32 -1276,6 -1271,18 -1272,6 -1271,18 -1267,6 -1271,6 -1271,18 +1272,32 @@@@@@@@@ config ARM_ERRATA_75432 This workaround defines cpu_relax() as smp_mb(), preventing correctly written polling loops from denying visibility of updates to memory. + + ++ config ARM_ERRATA_364296 + + ++ bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" + + ++ depends on CPU_V6 && !SMP + + ++ help + + ++ This options enables the workaround for the 364296 ARM1136 + + ++ r0p2 erratum (possible cache data corruption with + + ++ hit-under-miss enabled). It sets the undocumented bit 31 in + + ++ the auxiliary control register and the FI bit in the control + + ++ register, thus disabling hit-under-miss without putting the + + ++ processor into full low interrupt latency mode. ARM11MPCore + + ++ is not affected. + + ++ +++++++config ARM_ERRATA_764369 +++++++ bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" +++++++ depends on CPU_V7 && SMP +++++++ help +++++++ This option enables the workaround for erratum 764369 +++++++ affecting Cortex-A9 MPCore with two or more processors (all +++++++ current revisions). Under certain timing circumstances, a data +++++++ cache line maintenance operation by MVA targeting an Inner +++++++ Shareable memory region may fail to proceed up to either the +++++++ Point of Coherency or to the Point of Unification of the +++++++ system. This workaround adds a DSB instruction before the +++++++ relevant cache maintenance functions and sets a specific bit +++++++ in the diagnostic control register of the SCU. +++++++ endmenu source "arch/arm/common/Kconfig" diff --cc arch/arm/Kconfig.debug index 81cbe40,0c7a4f5,b3dc1fa,81cbe40,81cbe40,81cbe40,81cbe40,81cbe40..df3eb3c --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@@@@@@@@ -80,21 -80,21 -138,9 -80,21 -80,21 -80,21 -80,21 -80,21 +138,9 @@@@@@@@@ config EARLY_PRINT kernel low-level debugging functions. Add earlyprintk to your kernel parameters to enable this console. -- -----config DEBUG_ICEDCC -- ----- bool "Kernel low-level debugging via EmbeddedICE DCC channel" -- ----- depends on DEBUG_LL -- ----- help -- ----- Say Y here if you want the debug print routines to direct their -- ----- output to the EmbeddedICE macrocell's DCC channel using -- ----- co-processor 14. This is known to work on the ARM9 style ICE -- ----- channel and on the XScale with the PEEDI. -- ----- -- ----- It does include a timeout to ensure that the system does not -- ----- totally freeze when there is nothing connected to read. -- ----- config OC_ETM bool "On-chip ETM and ETB" - ------ select ARM_AMBA + ++++++ depends on ARM_AMBA help Enables the on-chip embedded trace macrocell and embedded trace buffer driver that will allow you to collect traces of the