From: Tom Tromey <tom@tromey.com>
Date: Thu, 9 Aug 2018 16:46:01 +0000 (-0600)
Subject: Minor formatting fixes in riscv-tdep.h
X-Git-Tag: users/ARM/embedded-binutils-master-2018q4~1118
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=06ab921988f5dfd64630a0b92d05dd94792e0a08;p=external%2Fbinutils.git

Minor formatting fixes in riscv-tdep.h

This fixes some minor formatting issues in riscv-tdep.h, including one
pointed out by ARI.

ChangeLog
2018-08-09  Tom Tromey  <tom@tromey.com>

	* riscv-tdep.h: Minor formatting fixes.
---

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 0a05299..b405915 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,7 @@
+2018-08-09  Tom Tromey  <tom@tromey.com>
+
+	* riscv-tdep.h: Minor formatting fixes.
+
 2018-08-09  Simon Marchi  <simon.marchi@ericsson.com>
 
 	* common/scoped_mmap.c (mmap_file): Silence ARI warning.
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 8591116..8358d4e 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -1,4 +1,5 @@
-/* Target-dependent header for the RISC-V architecture, for GDB, the GNU Debugger.
+/* Target-dependent header for the RISC-V architecture, for GDB, the
+   GNU Debugger.
 
    Copyright (C) 2018 Free Software Foundation, Inc.
 
@@ -39,7 +40,8 @@ enum
   RISCV_LAST_FP_REGNUM = 64,	/* Last Floating Point Register */
 
   RISCV_FIRST_CSR_REGNUM = 65,  /* First CSR */
-#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
+#define DECLARE_CSR(name, num) \
+  RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
 #include "opcode/riscv-opc.h"
 #undef DECLARE_CSR
   RISCV_LAST_CSR_REGNUM = 4160,
@@ -80,7 +82,7 @@ struct gdbarch_tdep
 extern int riscv_isa_xlen (struct gdbarch *gdbarch);
 
 /* Single step based on where the current instruction will take us.  */
-extern std::vector<CORE_ADDR>
-riscv_software_single_step (struct regcache *regcache);
+extern std::vector<CORE_ADDR> riscv_software_single_step
+  (struct regcache *regcache);
 
 #endif /* RISCV_TDEP_H */