From: Artur Pilipenko Date: Sat, 22 Apr 2017 07:24:52 +0000 (+0000) Subject: Fix for PR32740 - Invalid floating type, unreachable between r300969 and r301029 X-Git-Tag: llvmorg-5.0.0-rc1~6960 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0632bdc6483dabd0f37134cc8d69bc102e93b213;p=platform%2Fupstream%2Fllvm.git Fix for PR32740 - Invalid floating type, unreachable between r300969 and r301029 The bug was introduced by r301018 "[InstCombine] fadd double (sitofp x), y check that the promotion is valid". The patch didn't expect that fadd can be on vectors not necessarily scalars. Add vector support along with the test. llvm-svn: 301070 --- diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index 99c90b8..05f34e9 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -1391,11 +1391,14 @@ Instruction *InstCombiner::visitFAdd(BinaryOperator &I) { // analysis can tell us that the result of the addition has less significant // bits than the integer type can hold. auto IsValidPromotion = [](Type *FTy, Type *ITy) { + Type *FScalarTy = FTy->getScalarType(); + Type *IScalarTy = ITy->getScalarType(); + // Do we have enough bits in the significand to represent the result of // the integer addition? unsigned MaxRepresentableBits = - APFloat::semanticsPrecision(FTy->getFltSemantics()); - return ITy->getIntegerBitWidth() <= MaxRepresentableBits; + APFloat::semanticsPrecision(FScalarTy->getFltSemantics()); + return IScalarTy->getIntegerBitWidth() <= MaxRepresentableBits; }; // (fadd double (sitofp x), fpcst) --> (sitofp (add int x, intcst)) diff --git a/llvm/test/Transforms/InstCombine/add-sitofp.ll b/llvm/test/Transforms/InstCombine/add-sitofp.ll index 1de06c3..105c9ef 100644 --- a/llvm/test/Transforms/InstCombine/add-sitofp.ll +++ b/llvm/test/Transforms/InstCombine/add-sitofp.ll @@ -100,3 +100,42 @@ define float @test_3(i32 %a, i32 %b) { %p = fadd float %o, 1.0 ret float %p } + +define <4 x double> @test_4(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: @test_4( +; CHECK-NEXT: [[A_AND:%.*]] = and <4 x i32> [[A:%.*]], +; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], +; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]] +; CHECK-NEXT: [[RES:%.*]] = sitofp <4 x i32> [[ADDCONV]] to <4 x double> +; CHECK-NEXT: ret <4 x double> [[RES]] +; + ; Drop two highest bits to guarantee that %a + %b doesn't overflow + %a_and = and <4 x i32> %a, + %b_and = and <4 x i32> %b, + + %a_and_fp = sitofp <4 x i32> %a_and to <4 x double> + %b_and_fp = sitofp <4 x i32> %b_and to <4 x double> + + %res = fadd <4 x double> %a_and_fp, %b_and_fp + ret <4 x double> %res +} + +define <4 x float> @test_4_neg(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: @test_4_neg( +; CHECK-NEXT: [[A_AND:%.*]] = and <4 x i32> [[A:%.*]], +; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], +; CHECK-NEXT: [[A_AND_FP:%.*]] = sitofp <4 x i32> [[A_AND]] to <4 x float> +; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float> +; CHECK-NEXT: [[RES:%.*]] = fadd <4 x float> [[A_AND_FP]], [[B_AND_FP]] +; CHECK-NEXT: ret <4 x float> [[RES]] +; + ; Drop two highest bits to guarantee that %a + %b doesn't overflow + %a_and = and <4 x i32> %a, + %b_and = and <4 x i32> %b, + + %a_and_fp = sitofp <4 x i32> %a_and to <4 x float> + %b_and_fp = sitofp <4 x i32> %b_and to <4 x float> + + %res = fadd <4 x float> %a_and_fp, %b_and_fp + ret <4 x float> %res +}