From: Craig Topper <craig.topper@sifive.com>
Date: Wed, 19 Oct 2022 22:54:28 +0000 (-0700)
Subject: [RISCV] Remove -enable-unsafe-fp-math from machine combiner tests. NFC
X-Git-Tag: upstream/17.0.6~30074
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=061566d954bade4c3c6020aca097ebd493ce2ee0;p=platform%2Fupstream%2Fllvm.git

[RISCV] Remove -enable-unsafe-fp-math from machine combiner tests. NFC

The optimization is using fast math flags on the instructions instead.
---

diff --git a/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll b/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
index 3b4db5c..adb05ee 100644
--- a/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
+++ b/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \
-; RUN: -O3 -enable-unsafe-fp-math -riscv-enable-machine-combiner=true        \
+; RUN: -O3 -riscv-enable-machine-combiner=true        \
 ; RUN: -stop-after machine-combiner < %s | FileCheck %s
 
 define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {
diff --git a/llvm/test/CodeGen/RISCV/machine-combiner.ll b/llvm/test/CodeGen/RISCV/machine-combiner.ll
index 0821643..6d9a7e9 100644
--- a/llvm/test/CodeGen/RISCV/machine-combiner.ll
+++ b/llvm/test/CodeGen/RISCV/machine-combiner.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \
-; RUN: -O3 -enable-unsafe-fp-math -riscv-enable-machine-combiner=true < %s | \
+; RUN: -O3 -riscv-enable-machine-combiner=true < %s | \
 ; RUN: FileCheck %s
 
 define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {