From: Steve MacLean, Qualcomm Datacenter Technologies, Inc <sdmaclea@qti.qualcomm.com>
Date: Fri, 26 May 2017 00:08:39 +0000 (+0000)
Subject: [Arm64] stlr for JIT_WriteBarrier
X-Git-Tag: accepted/tizen/base/20180629.140029~1083^2~509
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=057686e1789897e453100086209a72d9e3353073;p=platform%2Fupstream%2Fcoreclr.git

[Arm64] stlr for JIT_WriteBarrier
---

diff --git a/src/vm/arm64/asmhelpers.S b/src/vm/arm64/asmhelpers.S
index a3aec32..2e1d029 100644
--- a/src/vm/arm64/asmhelpers.S
+++ b/src/vm/arm64/asmhelpers.S
@@ -267,8 +267,7 @@ WRITE_BARRIER_END JIT_CheckedWriteBarrier
 //   x17  : trashed (ip1) if FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP
 //
 WRITE_BARRIER_ENTRY JIT_WriteBarrier
-    dmb  ish
-    str  x15, [x14]
+    stlr  x15, [x14]
 
 #ifdef WRITE_BARRIER_CHECK
     // Update GC Shadow Heap
diff --git a/src/vm/arm64/asmhelpers.asm b/src/vm/arm64/asmhelpers.asm
index f303f82..8da2151 100644
--- a/src/vm/arm64/asmhelpers.asm
+++ b/src/vm/arm64/asmhelpers.asm
@@ -326,8 +326,7 @@ NotInHeap
 ;   x15  : trashed
 ;
     WRITE_BARRIER_ENTRY JIT_WriteBarrier
-        dmb      ish
-        str      x15, [x14]
+        stlr     x15, [x14]
 
 #ifdef WRITE_BARRIER_CHECK
         ; Update GC Shadow Heap